JPS5945288B2 - Tuner tuning frequency automatic control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic tuning frequency control device for a tuner, and more particularly to an automatic tuning frequency control device for a tuner capable of preset tuning and automatic search tuning.

Tuners that use electronic tuning include, for example, preset tuners that allow preset tuning, and even automatic search tuners, but these devices digitally store the frequency information of the receiving station in advance. The specified information is read from the memory using the preset channel selection button and set in a reversible counter.The counter output is converted to an analog voltage by a D/A (digital/analog) converter and then applied to the tuning element of the tuning circuit. Preset channel selection is performed by controlling actance using this analog voltage.

In addition, in a tuner equipped with an auto search tuning function, a clock pulse generator with a constant frequency is installed, and the operation of the reversible counter is counted up or down in response to an up or down command, and analog (tuning) is performed based on the output of this counter. The voltage is used as the tuning control voltage.

Since such an electronic tuner has a so-called open-loop configuration, which is different from a closed-loop configuration such as a PLL (phase locked loop) synthesizer tuner system, compensation for temperature changes and changes over time is not sufficient.

Examples of conventional compensation methods include detecting a deviation in the received frequency and controlling the local oscillation frequency, and performing temperature compensation and other tuning on the power supply circuit of the digital control circuit for a frequency synthesizer. Voltage fluctuations are kept as small as possible.

This method requires highly accurate parts and has drawbacks such as variations from device to device.

SUMMARY OF THE INVENTION The object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable automatic tuning frequency control device.

The automatic tuning frequency control device for a tuner of the present invention is directed to an automatic tuning frequency control device for a tuner that has an up/down counter and controls the tuning frequency of a tuning circuit according to the count contents of this counter, an out-of-tune state detection means for detecting an out-of-tune state and generating a detection signal during that time;
a clock signal sending means for sending a predetermined clock signal to the reversible counter during the existence period of the detection signal; and a clock signal having different signal widths using the clock signal to control up and down operations of the reversible counter during the existence period of the detection signal. The apparatus is characterized in that it includes a command signal generating means for sequentially generating up and down command signals.

In this configuration, if the tuning voltage deviates due to temperature changes during preset tuning and the desired receiving station is tuned to the wrong receiving station, the tuning voltage is automatically adjusted by repeating the up and down operations of the reversible counter a predetermined number of times. It is possible to find the optimum tuning point by changing the value up and down in steps.

In addition, the same operation can be performed for detuning after tuning to correct the tuning deviation.

The present invention will be explained below using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and shows an example in which the present invention is applied to an auto-search type voltage synthesizer tuner.

1 indicates an input latch circuit, which includes an up command switch S1,
Down command switch S2 and stop command switch S3
are respectively provided in series with resistors R1, R2 and R3 between the positive power supply and ground as shown in the figure.

A set-reset flip-flop is configured by NAND gates 11 and 12 and an inverter 13, and a switch S1
is set and the up command is latched by the suppression of , but it is reset by the stop switch S3 or the down switch S2.

Similarly, the NAND gates 14 and 15 and the inverter 16 constitute a flip-flop that latches the down command caused by suppressing the switch S2, and the stop switch S3
Or it is reset by the up switch S1.

Reference numeral 2 denotes a clock pulse generator for generating clock pulses for tuning, which has a well-known configuration consisting of a NAND gate 21, inverters 22 and 23, a capacitor C1, and resistors R4 and R.

This clock pulse is generated by one AND gate 31 and 32 forming the gate circuit 3.

The outputs of the flip-flops of the latch circuit 1 are applied to the exclusive OR gate 33 of the gate circuit 3, and the output of the exclusive OR gate 33 is applied to the output of the AND gate 31. In addition, the NOR gate 34 and the muting signal layer AND gate 35 are operated by one person, and furthermore, the AND gate 37 is operated by one person via the inverter 36.

A NOR gate 38 is provided which outputs the output of this AND gate 37 and the previous down command latch output, and the output of this NOR gate becomes an up and down command signal for the reversible counter 4.

The output of the OR gate 39 is used as the clock input of the counter 4, and the outputs of the AND gates 31 and 32 are applied as the two inputs of the OR gate 39.

Reference numeral 5 indicates a detuning state detection circuit, which includes, for example, a well-known frequency discriminator whose output voltage exhibits so-called S-curve characteristics with respect to frequency changes, and a smoothing circuit that smoothes this S-curve output to generate an average voltage. and a waveform shaping circuit that converts this smoothed voltage into a digital signal, and generates a high-level detection signal when tuning the tuner, and this detection signal becomes the input of the AND gate 51.

The inputs of this gate 51 are up and down switches S.

The output of the AND gate 52 that detects the pressed state of S2 and S2 is used.

The output of the AND gate 51 serves as a single input to the NOR gate 34 of the gate circuit 3, and also serves as an input to the monostable multi 6.

The width of the output pulse Q of this multi-6 is determined by the capacitor C2 and the resistor R6, and operates as a hold circuit that blocks input of the clock pulse to the reversible counter 4 during that period and stops the change in the tuning voltage.

Reference numeral 7 denotes an up/down command signal generation circuit, which includes a No. 2 and a second counter 7a and 7b.

AND gate 3 is used as the clock input of the first counter 7a.
2 outputs are applied via the inverter 11, and a 4-bit output A is generated depending on the number of clock inputs.

~A3 changes.

Clear input of first counter 7a and second counter 7
The output of a NAND gate 72 is applied to the clock input of b, and the output of an AND gate 73 which uses the output Q of the hold circuit 6 as one input is supplied to one output of this gate 12.

Further, the output of the AND gate 73 becomes a clear input to the second counter 7b via an inverter 74, and also serves as an input to the AND gates 31 and 35 of the gate circuit 3.

Similarly, the second counter 7b outputs 4 bits B in response to the clock input.

-B3 changes, and both count outputs are supplied to a coincidence detection circuit IC which compares the count contents and generates a coincidence signal when the two match.

This coincidence detection circuit 7c consists of a 4-bit comparator 100 and a monostable multi-channel 110, and the 4-bit comparator 100 consists of exclusive OR gates 75 to 78 that require two people to operate each bit, and these gates, as shown in the figure. The monostable multi 110 includes an OR gate 79 whose output is input, and is configured to be triggered by the output of this gate 79 to generate an output with a predetermined pulse width.
12°OR gate 113, capacitor C3 and resistor R6
It is made from ゜R7.

Output pulse A of monostable multi 110 is NAND gate 1
2 serves as a clear input to the first counter 7a, and also serves as a clock input to the second counter 7b.

Further, the output of the AND gate 73 is the output of the first stage gate 111 of the monostable multi 110.

The output pulse A of the monostable multi 110 becomes the trigger input of the binary output generation circuit 7d consisting of a flip-flop, and its output Q is sent to the up/down counter 4 via the AND gate 37 and NOR gate 38 of the gate circuit 3. This becomes an up/down command signal.

The count output of the counter 4 is converted into an analog voltage by the D/A converter 8 and used as a tuning voltage to control the actance of a tuning element of a tuning circuit (not shown).

Note that the inverter 1 in the up/down command signal generation circuit 7
14. AND gates 115 and 116 and NAND gate 117 are for setting the number of up/down repetitions, as will be described later. When the set number of times is reached, the circuit is reset to the initial state and repeats up/down again. It is intended to do so.

In such a configuration, the content of the first counter 7a is cleared to (o, o, o, o) at the time of synchronization, and the content of the second counter 7b is preset to (0, 0° 0.1). has been done.

In this case, when the tuning frequency of the tuning circuit deviates due to a change in temperature or the like, a detection signal is output from the detuning state detection circuit 5 during that time.

At this time, the switch S of the input launch circuit 1. Since S2 is open, the AND gate 51 is opened and the detection signal is output.

Therefore, the clock pulse is applied to the first counter 7a via the AND gate 32 by the operation of the gate circuit 3.

By applying the first clock pulse, the contents of the first counter 7a become (0, 0, 0, 1) and match the contents of the second counter.

Therefore, a coincidence output is generated at the output of the output gate 79 of the comparator 100, and a single pulse A is output from the output of the monostable multi 110 in synchronization with the generation timing.

The first counter 7a is cleared by this coincidence output pulse A, and the second counter 7b counts up (0, 0).
,1,0)(!l- becomes.

At the same time, flip-flop 7d is set and its Q output is inverted.

This inverted output changes the counting operation of the up/down counter 4 from the up state to the down state via the AND gate 37 and the NOR gate 38 of the gate circuit 3.

In this state, the contents of the counter 4 increase by one from the initial state, and the tuning voltage increases accordingly.

At this time, if the out-of-tune state is still present, the out-of-tune state detection circuit 5
Since the detection signal is successively output from , a clock pulse is applied to the first counter 7a.

Therefore, if two of these clock pulses arrive and the contents of the counter become (o, o, i, o), it will match the contents of the second counter 7b, and a coincidence output pulse A will be generated, which will cause the flip-flop 7d to match. It is reversed again and the up/down counter 4 is operated down.

Therefore, the counter 4 becomes (+1)-2=-1 from the initial state, and its content decreases by 1, and as a result, the tuning output similarly decreases.

At this time, the first counter is cleared, and the contents of the second counter count up to (0, 0, 1, 1).

In this way, up and down count commands are alternately issued until accurate synchronization is achieved, and each time the set value of the second counter 7b increases by 91111, the period during which the coincidence signal is generated also increases by 1 pulse period. Therefore, the count contents of the up/down counter 4 change before and after the initial value, and the tuning voltage also changes accordingly.

This situation is shown in FIG. 2, where each number indicates the count content of the up/down counter 4 in each case.

When the contents of the counter 7b are (1, 1, 1, 1), the contents of the counter 7a indicate 7 steps.

(0, 1, 1, 1), the output of the AND gate 115 is inverted and the circuit is reset to the initial state via the NAND gate 117, etc., and the amplifier is operated down until the synchronization is achieved again from the initial state. will be done.

This operation is also applied when tuning to the desired receiving station cannot be achieved during preset tuning.
Accurate tuning control becomes possible.

Furthermore, when the hold circuit using the monostable multi-6 receives a predetermined station during amplifier or down operation, it blocks the transmission of clock pulses to the counter 4 for a period determined by the capacitor C2 and resistor R3 of this circuit, unless there is a stop command. Hold and start searching again.

Also, even during hold, the hold is canceled by issuing an amplifier or down command, and the search starts again.

By continuing to press the up or down switch, the up or down search operation continues even if there is a receiving station.

According to the present invention, automatic frequency control is possible using a digital circuit, so there is an advantage that there is no need to provide a temperature compensation circuit or the like with high accuracy, and it is easy to integrate the circuit and achieve miniaturization.

Furthermore, it is possible to track more accurately over a wider range than conventional analog AFC circuits, making it ideal for voltage synthesizer tuners.

In addition, in the above, the up and down operations each have 7 steps, but are not limited to this.
The monostable multi 110 can also be omitted by making the second counter 7b a presettable counter.

Furthermore, various modifications are possible without being limited to the illustrated circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a diagram explaining the operation of FIG. 1. Explanation of symbols of main parts, 2... Clock pulse, generator, 4... Up/down counter, 5.
...Out-of-tuning state detection circuit, 7a, 7b...
・Counter, 7c... Comparison circuit, 7d...
··flip flop.

Claims (1)

[Scope of Claims] 1. An automatic tuning frequency control device for a tuner that has a reversible counter that can freely count up and down, and controls the tuning frequency of a tuning circuit according to the count content of the reversible counter, comprising:
Out-of-tuning state detection means detects an out-of-tuning state and generates a detection signal during that time, and sends a predetermined clock signal to the reversible counter whose initial value is the counting content immediately before the detection signal is generated during the existence period of the detection signal. and a clock signal sending means, each period of up and down operation is sequentially carried out in order to control up and down operations of the reversible counter during the existence period of the detection signal, and these up and down operations are repeated alternately. 1. An automatic tuning frequency control device for a tuner, comprising command signal generating means for generating up and down command signals such as UP and DOWN command signals using the clock signal. 2. The command signal generating means includes a first counter that counts the clock signal during the existence period of the detection signal, and a second counter whose contents are preset to a predetermined value and that adds and counts the number of input signals from this preset value. and a coincidence detection means for comparing the counts of the first and second counters and generating a coincidence signal when they match, and using the signal as an input signal of the second counter and clearing the first counter; Claim 1 further comprising an output signal generating means whose output state changes each time the coincidence signal is generated, and controlling up and down counting operations of the reversible counter according to the output signal state. Apparatus described in section.