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JPS5945992B2 - Electrode manufacturing method for matrix-driven elements - Google Patents
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JPS5945992B2 - Electrode manufacturing method for matrix-driven elements - Google Patents

Electrode manufacturing method for matrix-driven elements

Info

Publication number
JPS5945992B2
JPS5945992B2 JP55037573A JP3757380A JPS5945992B2 JP S5945992 B2 JPS5945992 B2 JP S5945992B2 JP 55037573 A JP55037573 A JP 55037573A JP 3757380 A JP3757380 A JP 3757380A JP S5945992 B2 JPS5945992 B2 JP S5945992B2
Authority
JP
Japan
Prior art keywords
electrode
matrix
manufacturing
connection wiring
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55037573A
Other languages
Japanese (ja)
Other versions
JPS56135887A (en
Inventor
浩雄 堀
俊夫 柳沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP55037573A priority Critical patent/JPS5945992B2/en
Publication of JPS56135887A publication Critical patent/JPS56135887A/en
Publication of JPS5945992B2 publication Critical patent/JPS5945992B2/en
Expired legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明はマトリクス、駆動形の表示素子、撮像素l 子
の電極製造方法に係わり、特に電極の良否を検査しやす
いように構成したマトリクス駆動形素子の電極製造方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing electrodes for matrix, drive type display elements, and image pickup elements, and particularly relates to a method for manufacturing electrodes for matrix drive type elements configured to facilitate inspection of the quality of the electrodes. .

マトリクス形表示素子は液晶、エレクトロルミネセンス
、螢光体発光等を用いたものの研究が盛んになされ、す
でに技術発表もされている。
Matrix-type display elements using liquid crystals, electroluminescence, fluorescent light, etc. are being actively researched, and some technical announcements have already been made.

MOSトランジスタとコンデンサのアレイを集積したシ
リコンチップを一方の基板とするものは例えば特開昭5
0−10993に、薄膜トランジスタとコンデンサのア
レイをガラス板に配設したものを同″じく一方の基板と
するものは例えばIEEETra−ns、onElec
tronDevices第20巻995〜1001頁に
、液晶の動作特性を改善するために酸化亜鉛等の層状バ
リスタを電極間に介在させるものは例えばIEEETr
ans、onElectronDe−、vices第2
6巻1123頁〜1128頁にそれぞれ詳細に記載され
ている。撮像素子はホトダイオード受光部とMOSトラ
ンジスタのアレイをシリコンチップ上に集積したものが
例えばテレビジョン学会誌第33巻第7号548頁〜5
53頁に記フ載されている。次にこのようなマトリクス
駆動形素子について、先ずMOSトランジスタを用いた
スイッチマトリクス形液晶表示素子を例にとり本発明の
説明に必要な構成、動作を説明する。
For example, one in which one substrate is a silicon chip with an integrated array of MOS transistors and capacitors is disclosed in Japanese Patent Application Laid-open No. 5
0-10993, one of the substrates is an array of thin film transistors and capacitors arranged on a glass plate, such as IEEE Tra-ns and onElec.
In tronDevices, Vol. 20, pages 995-1001, IEEE Tr.
ans, onElectronDe-, vices 2nd
They are described in detail in Volume 6, pages 1123 to 1128. An image sensor is one in which a photodiode light receiving section and an array of MOS transistors are integrated on a silicon chip, as described in, for example, the Journal of the Television Society, Vol. 33, No. 7, pp. 548-5.
It is described on page 53. Next, regarding such a matrix drive type element, first, the structure and operation necessary for explaining the present invention will be explained using a switch matrix type liquid crystal display element using MOS transistors as an example.

5 第1図はスイッチマトリクス形液晶表示素子の概略
平面図であり、MOSトランジスタおよび蓄積コンデン
サは等価回路で示した。
5. FIG. 1 is a schematic plan view of a switch matrix type liquid crystal display element, and MOS transistors and storage capacitors are shown as an equivalent circuit.

スイツチマトりクズ形液晶表示素子は内表面に酸化イン
ジウム透明電極1を被着せしめた前面ガラス基板2と、
該ガラス基板2とほぼ10μm離れて対向し集積回路を
形成した後面シリコン基板3、該シリコン基板3と前記
ガラス基板2の間に挿入された液晶層(図示ぜず)から
構成される。シリコン基板3上には、酸化硅素膜等で該
シリコン基板3と電気的に絶縁し平行に等間隔で配設さ
れた信号電極4群と、該信号電極母線4群とほぼ直交し
しかも酸化硅素等の層間絶縁膜(図示せず)で信号電極
母線4群と電気的に絶縁された走査電極母線5群、各信
号電極母線と各走査電極母線とのそれぞれの交点付近に
マトリクス状に配置された表示画素6群が形成されてい
る。表示画素6はMOSトランジスタ7と蓄積コンデン
サ8から構成され、該MOSトランジスタ7のゲート電
極は走査電極母線5に、ソース電極は信号電極母線4に
、ドレイン電極は蓄積コンデンサ8の一力の電極および
透明電極1と対向する表示電極9にそれぞれ接続されて
いる。次にこのスイツチマトリクス形液晶表示素子の動
作を簡単に説明する。
The switch-shaped liquid crystal display element has a front glass substrate 2 having an indium oxide transparent electrode 1 coated on its inner surface,
It consists of a rear silicon substrate 3 facing the glass substrate 2 at a distance of approximately 10 μm and on which an integrated circuit is formed, and a liquid crystal layer (not shown) inserted between the silicon substrate 3 and the glass substrate 2. On the silicon substrate 3, there are four groups of signal electrodes that are electrically insulated from the silicon substrate 3 by a silicon oxide film or the like and arranged in parallel at equal intervals, and a silicon Five groups of scanning electrode busbars are electrically insulated from four groups of signal electrode busbars by an interlayer insulating film (not shown), and are arranged in a matrix near the respective intersections of each signal electrode busbar and each scanning electrode busbar. Six groups of display pixels are formed. The display pixel 6 is composed of a MOS transistor 7 and a storage capacitor 8. The gate electrode of the MOS transistor 7 is connected to the scanning electrode bus 5, the source electrode is connected to the signal electrode bus 4, and the drain electrode is connected to the single-power electrode of the storage capacitor 8. The transparent electrode 1 and the display electrode 9 facing each other are connected to each other. Next, the operation of this switch matrix type liquid crystal display element will be briefly explained.

走査電極母線5の端部に配設されたボンデイングパツト
等の端子Yl,Y2,Y3,・・・・・・Yj,・・・
・・・Ylll)およびY{・,Y:,Yく・・・Y1
・・・・・・YITl)の少なくとも一方にフレーム周
波数が例えば30Hzの走査電圧パルスを順々に印加し
、走査電極母線5に接続されているMOSトランジスタ
7を各走査電極母線ごとに導通状態とする。同時に信号
電極母線4群に端子Xl,X2,X3,・・・・・・X
i,・・・・・・XO)およびXl,X≦,X6・・・
・・・マ。・・・・・・Xln)の少なくとも一方を介
してアナログ信号を例えば約60μs間印加し、それぞ
れの前記蓄積コンデンサ8に表示内容に応じた電荷を蓄
積する。そして次の走査を受けるまでの約33msの間
中、透明電極1と表示電極9との間に挟持された液晶を
電気的に励起し、いわゆる線順次走査方式によつて、画
像表示を行う。このような形式の表示素子の大きさを例
えば3礪×4CTL1表示画素の数を500×500と
すれば、電極母線の全長は35mにも及び、電極母線の
断線あるいはシリコン基板3との電気的短絡により、表
示に線状の欠陥が生じることが多く、従来は電極母線を
一本ずつ、端子XiXl(1=1〜n)間およびYjY
′j(j−1〜m)間で試験する必要があつた。
Terminals Yl, Y2, Y3, . . . Yj, . . . such as bonding pads arranged at the ends of the scanning electrode bus bar 5
...Yllll) and Y{・,Y:,Yku...Y1
A scanning voltage pulse having a frame frequency of, for example, 30 Hz is sequentially applied to at least one of YITl), and the MOS transistors 7 connected to the scanning electrode bus 5 are made conductive for each scanning electrode bus. do. At the same time, terminals Xl, X2, X3,...X are connected to four groups of signal electrode busbars.
i,...XO) and Xl,X≦,X6...
···Ma. . During about 33 ms until receiving the next scan, the liquid crystal sandwiched between the transparent electrode 1 and the display electrode 9 is electrically excited, and an image is displayed by a so-called line sequential scanning method. If the size of a display element of this type is, for example, 3 cm x 4 CTL, and the number of display pixels is 500 x 500, the total length of the electrode bus bar will be as much as 35 m, and there may be a disconnection of the electrode bus bar or electrical contact with the silicon substrate 3. Short circuits often cause linear defects in the display, and conventionally, the electrode busbars were connected one by one between terminals XiXl (1=1 to n) and between YjY
It was necessary to test between 'j (j-1 to m).

しかしながら、同時に多数のプロ一を並べることは実際
上不可能であり、またプローブの数が少ない場合は検査
時間が長くなり実用上問題があつて、電極母線の欠陥の
有無が不明のま\表示素子が製造され、最終的な機能検
査で欠陥が見出されるという無5駄があつた。本発明は
このような欠点に鑑みなされたものであり、その目的と
するところは平行に並べられた多数の電極母線の断線お
よび基板との短絡という欠陥の有無を容易に判別し得る
ように改良したマトリクス駆動形素子の電極製造方法を
提供することにある。
However, it is practically impossible to line up a large number of probes at the same time, and when the number of probes is small, the inspection time becomes long, which poses a practical problem, and the presence or absence of defects in the electrode bus bar is unknown. There was a lot of waste when the device was manufactured and defects were found during the final functional test. The present invention has been made in view of these drawbacks, and its purpose is to improve the ability to easily determine the presence or absence of defects such as disconnection of a large number of parallel electrode busbars and short circuits with the substrate. An object of the present invention is to provide a method for manufacturing electrodes of a matrix-driven element.

本発明によれば上述の目的は、電極母線の端部をそれぞ
れ延長し、かつ二本ずつ電気的に接続し、配線が蛇行す
るように形成し、電極母線全体にわたつての欠陥の有無
を検査し、前記電極母線の延長部を除去することによつ
て達成される。
According to the present invention, the above-mentioned object is to extend the ends of the electrode busbars, electrically connect two wires at a time, form the wiring in a meandering manner, and check for defects across the entire electrode busbar. This is accomplished by inspecting and removing the extension of the electrode busbar.

以下、図面を参照して本発明のマトリクス,駆動形素子
の電極製造方法について説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing electrodes of a matrix and drive type element according to the present invention will be explained with reference to the drawings.

第2図は本発明に係るスイツチマトリクス形液晶表示素
子を形成するシリコン基板の平面図であり説明の都合上
、信号電極母線4群および端子(X1・・・・・・Xn
,)(X′1・・・・・・X二 )だけを示し、走査電
極母線群、MOSトランジスタ、蓄積コンデンサ、表示
電極等は省略した。これらの電極母線群はMOSトラン
ジスタ、蓄積コンデンサ、表示電極等のそれぞれの一剖
,分と同時にあるいは前後して製造されるのが一般的で
あるが、先ず通常シリコン基板3上にCVD(Chem
icalVapOrDepOsitiOn)法により略
1μm厚の酸化硅素から成る絶縁膜10を形成した後、
該絶縁膜10上に真空蒸着法によりアルミニウム層(図
示せず)を設ける。しかる後にホトレジストをアルミニ
ウム層全面に塗布し、さらにホトマスクを用いてホトレ
ジストを露光し、電極母線4に相当した部分を除く他の
部分のホトレジストを除去する。引続いて燐酸を全体と
したAlエツチング液を用いて露出したアルミニウム層
をエツチングすることによつて、電極母線群はストライ
プ状に作られる。この場合、電極母線4の端がそれぞれ
にしアルミニウムの端子(X1〜Xn,)(Xζ〜X′
n)を経て延長され、しかも隣りの二本ずつの電極母線
を母線接続配線部11によりそれぞ電気的に接続して、
さらに端子Xl,X′nの母線延長上には端子X。およ
びX≦を設けるようにしたホトマスクを使用する。した
がつて電極母線は第2図に示すように端子X。と端子X
6間が電気的に接続される。しかる後、図中のABCD
部12およびA/B7C7D7部13を除き、シリコン
基板3上に例えばPSG(PhOsphiSilica
teGlass)を被着せしめる。この工程には通常の
CVD法、ホトエツチングプロセスが使用される。次に
、上記の製造工程後、端子X。
FIG. 2 is a plan view of a silicon substrate forming a switch matrix type liquid crystal display element according to the present invention.
, ) (X'1... Generally, these electrode busbar groups are manufactured at the same time or around the same time as the MOS transistors, storage capacitors, display electrodes, etc.
After forming an insulating film 10 made of silicon oxide with a thickness of about 1 μm by the icalVapOrDepOsitiOn method,
An aluminum layer (not shown) is provided on the insulating film 10 by vacuum evaporation. Thereafter, a photoresist is applied to the entire surface of the aluminum layer, and the photoresist is further exposed to light using a photomask to remove the photoresist in other parts except for the part corresponding to the electrode bus bar 4. Subsequently, the exposed aluminum layer is etched using a phosphoric acid-based Al etching solution, thereby forming the electrode busbars in the form of stripes. In this case, the ends of the electrode busbars 4 are made of aluminum terminals (X1 to Xn,) (Xζ to X'
n) and electrically connects each two adjacent electrode busbars by the busbar connection wiring part 11,
Further, there is a terminal X on the busbar extension of the terminals Xl and X'n. and X≦. Therefore, the electrode busbar is terminal X as shown in FIG. and terminal
6 are electrically connected. After that, ABCD in the diagram
For example, PSG (PhOsphiSilica) is formed on the silicon substrate 3 except for the part 12 and the A/B7C7D7 part 13
teGlass). This step uses the usual CVD method and photoetching process. Next, after the above manufacturing process, terminal X is formed.

と端子X≦間の導通を試験することによつて電極母線4
全体にわたつて断線の有無が確認される。また、端子X
OまたはX二とシリコン基板3との導通を試験すること
によつて電極母線4全体にわたつて短絡の有無が確認さ
れる。電極母線4に欠陥がないとわかつたシリコン基板
3は引続いて、燐酸を主体としたAlエツチング液等を
用いた湿式エツチングにより、ABCD部12およびA
/B′C′D/部13にある母線接続配線部11を除去
し、その後に端子Xl,X2・・・・・・Xn,X},
X≦・・・・・・X二の表面を覆うPSGを弗化アンモ
ニウム緩衝液によつて除去し、スイツチマトリクス形液
晶表示素子の電極形成を完了する。上記方法では母線接
続配線部11の除去は湿式エツチングを用いて行つたが
、HCI,HF等使用のガスエツチング、CF4,CH
F3等使用のプラズマエツチング、Ar,Xe等使用の
イオンエツチング等のいわゆるドライエツチングによつ
て行うこともできる。
By testing the continuity between the electrode busbar 4 and the terminal
The presence or absence of disconnection is checked throughout. Also, terminal
By testing the continuity between O or X2 and the silicon substrate 3, the presence or absence of a short circuit across the entire electrode bus bar 4 is confirmed. The silicon substrate 3, which was found to have no defects in the electrode bus bar 4, was then wet-etched using an Al etching solution mainly containing phosphoric acid to remove the ABCD portion 12 and the A.
/B'C'D/ Remove the bus connection wiring section 11 in the section 13, and then connect the terminals Xl, X2...Xn, X},
X≦...The PSG covering the surface of X2 is removed using an ammonium fluoride buffer solution to complete the electrode formation of the switch matrix type liquid crystal display element. In the above method, the busbar connection wiring part 11 was removed using wet etching, but gas etching using HCI, HF, etc., CF4, CH
It can also be carried out by so-called dry etching such as plasma etching using F3 or the like or ion etching using Ar, Xe or the like.

次に、本発明によるマトリクス1駆動形素子の電極製造
方法の他の実施例について第3図を用いて説明する。
Next, another embodiment of the electrode manufacturing method for a matrix 1 drive type element according to the present invention will be described with reference to FIG.

ただし、第2図と同一部には同じ番号・符号をつけその
説明を省くとともにシリコン基板3上にABCD部12
とA′B7C′D′部13を除きPSGを被着せしめる
までの工程は第2図の場合と同じであるのでその説明も
省略する。PSGをつけた後)端子XO9XlPX「1
0Xn9X璧X(,X(・・・・・・X′nの表面のP
SGをエツチングして除去する。ついで、端子X。と端
子X≦間の導通試1験による電極母線4の断線有無およ
び端子X。または端子X二とシリコン基板3との導通試
験による電極母線4とシリコン基板3との短絡有無の検
査を実施し、電極母線4に欠陥がないものは、図中のE
FおよびE′F′に沿つてダイヤモンドスクライバある
いはレーザスクライバ等によつて切り、それぞれABC
D部12、A′B′CID′部13をシリコン基板3か
ら除去することによつて電極母線4をそれぞれ独立せし
め、電極形成の工程を終える。シリコン基板は通常円形
であり、プロセス工程を終えたシリコン基板はダイヤモ
ンドスクライバレーザスクライバ、極薄ダイヤモンド砥
石等により方形状の素子に切断されるので前記母線接続
配線部11を素子周囲のダイシング領域に配設すること
が製造上きわめて有利であり、この点を考慮し案出した
本発明の他の実施例を、第4図を用いて説明する。
However, the same parts as those in FIG.
The steps up to the application of PSG except for the A'B7C'D' portions 13 are the same as in the case of FIG. 2, so the explanation thereof will be omitted. After attaching PSG) terminal XO9XlPX "1
0Xn9XP X(,X(...P on the surface of
Etch and remove SG. Next, terminal X. The presence or absence of disconnection of the electrode bus bar 4 and the terminal X by one continuity test between and terminal X≦. Or conduct a continuity test between the terminal
Cut along F and E'F' with a diamond scriber or laser scriber, respectively.
By removing the D section 12 and the A'B'CID' section 13 from the silicon substrate 3, the electrode busbars 4 are made independent, and the electrode forming process is completed. The silicon substrate is usually circular, and the silicon substrate after the process is cut into rectangular elements using a diamond scriber laser scriber, an ultra-thin diamond grindstone, etc. Therefore, the busbar connection wiring portion 11 is arranged in the dicing area around the elements. Another embodiment of the present invention devised in consideration of this point will be described with reference to FIG. 4.

この場合も前記の例と同様、MOSトランジスタ、蓄積
コンデンサ等は省略し、電極母線4および5の接続の様
子を主体に説明する。また、前出の図面と同一部には同
じ番号・符号を付した。3は円形のシリコン基板であり
、該シリコン基板3上には酸化硅素の絶縁膜10を形成
し、この上に信号電極母線4を配設し、さらに該電極母
線4との交点は酸化硅素等の層間絶縁膜(図示せず)を
形成した後に走査電極母線5を形成する。
In this case as well, as in the previous example, the MOS transistors, storage capacitors, etc. will be omitted, and the connection between the electrode buses 4 and 5 will be mainly explained. In addition, the same numbers and symbols are given to the same parts as in the previous drawings. Reference numeral 3 designates a circular silicon substrate, on which an insulating film 10 of silicon oxide is formed, on which a signal electrode bus 4 is arranged, and furthermore, the intersection with the electrode bus 4 is made of silicon oxide, etc. After forming an interlayer insulating film (not shown), scanning electrode busbars 5 are formed.

この場合、線分1J,JK,KL,L,MN,N0,0
P,PMで囲まれたダイシング領域14に母線接続配線
部11が位置するように電極母線4,5を形成する。こ
の後に、端子X。,Xl,・・・…XO9X≦9X(゜
″″″。゜X合,YO9Yl9”1″Yr]19Y工,
Y:,・・・・・・YITlの表面を除いて、シリコン
基板3表面にPSGを被着する。次に、電極母線4,5
の断線の有無を端子X。と端子X二間、端子Y。と端子
Y二間でそれぞれ検査しさらに電極母線4,5それぞれ
とシリコン基板3との短絡の有無を端子X。あるいはx
二とシリコン基板3との間で検査する。引続いて電極母
線4,5に欠陥がないものについて、ダイシング領域を
EF,E/F/,HG,H′G′に沿つてダイヤモンド
スクライバ等で切断し、電極形成の工程を終える。次に
、第5図を用いて、シリコン基板3から複数の素子特に
二つの素子16,17を製造する場合に適用する本発明
実施例を説明する。
In this case, line segment 1J, JK, KL, L, MN, N0, 0
The electrode busbars 4 and 5 are formed so that the busbar connection wiring portion 11 is located in the dicing region 14 surrounded by P and PM. After this, terminal X. ,Xl,...
Y:, . . . PSG is deposited on the surface of the silicon substrate 3 except for the surface of YITl. Next, electrode bus bars 4, 5
Check whether there is a disconnection at terminal X. Between terminal X and terminal Y. Terminal X and terminal Y are inspected for short circuits between each of the electrode busbars 4 and 5 and the silicon substrate 3. Or x
2 and the silicon substrate 3. Subsequently, for electrode busbars 4 and 5 with no defects, the dicing area is cut along EF, E/F/, HG, and H'G' with a diamond scriber or the like to complete the electrode forming process. Next, an embodiment of the present invention applied to manufacturing a plurality of elements, particularly two elements 16 and 17, from the silicon substrate 3 will be described with reference to FIG.

線分J,JK,KL,LI,MN,NO,OP,PM,
QR,RS,ST,TQで囲まれたダイシング領域14
に母線接続配線部11と母線延長部15が位置するよう
にして、電極母線4を形成し、上記実施例と同じく、電
極母線4の断線と、電極母線4とシリコン基板3との間
の短絡の有無を検査する。そして、シリコン基板3のダ
イシング領域14をEF,E′F′,U,IJ,KLに
沿つて切断して電極形成を終えて二つの素子16,17
を製造する。以上、スイツチマトリタス形液晶表示素子
を例にとり、断線および基板との短絡の有無の検査が容
易な構成の電極母線の製造方法について説明したが、表
示素子に限らず、本発明は平行な電極母線を有する素子
であれば撮像素子等にも適用できる。
Line segment J, JK, KL, LI, MN, NO, OP, PM,
Dicing area 14 surrounded by QR, RS, ST, and TQ
The electrode busbar 4 is formed such that the busbar connection wiring part 11 and the busbar extension part 15 are located at , and as in the above embodiment, there is no possibility of disconnection of the electrode busbar 4 and short circuit between the electrode busbar 4 and the silicon substrate 3. Inspect for the presence of. Then, the dicing area 14 of the silicon substrate 3 is cut along EF, E'F', U, IJ, and KL to complete the electrode formation, and the two elements 16, 17 are cut.
Manufacture. The above has described a method for manufacturing an electrode busbar having a configuration that allows easy inspection of disconnections and short circuits with the substrate using a switch matrices type liquid crystal display element as an example. However, the present invention is not limited to display elements. The present invention can also be applied to an image sensor or the like as long as the device has a bus bar.

また、上記実施例では、電極母線が単結晶シリコンの基
板上に形成されるものについて記述したが、基板はガラ
ス板上にアモルフアスシリコン、酸化亜鉛層等を被着せ
しめたものでもよい。以上説明したように本発明は、基
板の絶縁膜上に多数の平行な電極母線を製造するにあた
り、電極母線の端部をそれぞれ延長しかつ二本ずつ電気
的に接続し、配線が蛇行するようにして、電極母線の断
線および基板との短絡の検査を容易に行い、その後に電
極母線の延長部の配線を除去するので、製造プロセスの
途中で電極母線の欠陥の有無がわかり、不良品を組立て
続けるという無1駄がなくなり、マトリクス駆動形素子
の生産性向上、価格低減に大いに寄与する。
Further, in the above embodiments, the electrode busbar is formed on a single crystal silicon substrate, but the substrate may be a glass plate with a layer of amorphous silicon, zinc oxide, etc. applied thereto. As explained above, in manufacturing a large number of parallel electrode busbars on an insulating film of a substrate, the present invention extends the ends of each electrode busbar and electrically connects them two by two, so that the wiring meanders. This makes it easy to inspect the electrode bus for disconnections and short circuits with the board, and then removes the wiring at the extension of the electrode bus, allowing you to identify defects in the electrode bus during the manufacturing process and identify defective products. This eliminates the waste of continuous assembly, and greatly contributes to improving productivity and reducing costs of matrix-driven elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のマトリクス駆動形素子の概略平面図、第
2図、第3図、第4図及び第5図はそれぞれ本発明のマ
トリクス駆動形素子の電極製造方法を説明するための電
極形成基板の概略平面図である。 図において、3・・・・・・基板、4,5・・・・・・
電極母線、10・・・・・・絶縁膜、11,15・・・
・・・母線接続配線部、14・・・・・・ダイシング領
域。
FIG. 1 is a schematic plan view of a conventional matrix-driven element, and FIGS. 2, 3, 4, and 5 each illustrate electrode formation for explaining the electrode manufacturing method of a matrix-driven element of the present invention. FIG. 3 is a schematic plan view of the substrate. In the figure, 3...board, 4, 5...
Electrode bus bar, 10... Insulating film, 11, 15...
. . . Bus bar connection wiring section, 14 . . . Dicing area.

Claims (1)

【特許請求の範囲】 1 半導体基板上もしくは絶縁性基板の上に形成された
半導体層上に、該半導体基板もしくは該半導体層から絶
縁膜により絶縁分離され、それぞれほぼ平行に配線され
た多数の電極母線を有するマトリクス駆動形素子を製造
するに際し、前記個々の電極母線の端部をそれぞれ延長
し、かつ二本ずつ電気的に接続するための母線接続配線
部を設け配線が連続的に蛇行するように形成し、前記電
極母線の断線と該電極母線−半導体基板間もしくは電極
母線−半導体層間の短絡とを前記配線の両端間の通電と
配線端部と前記半導体基板との間の通電もしくは配線端
部と前記半導体層との間の通電とにより検査した後前記
母線接続配線部を除去するようにしたことを特徴とする
マトリクス駆動形素子の電極製造方法。 2 前記母線接続配線部の除去は湿式エッチングあるい
はドライエッチングによるものである特許請求範囲第1
項記載のマトリクス駆動形素子の電極製造方法。 3 前記母線接続配線部の除去は前記半導体基板もしく
は前記半導体層の切断によるものである特許請求範囲第
1項記載のマトリクス駆動形素子の電極製造方法。 4 前記母線接続配線部を前記半導体基板もしくは前記
半導体層のダイシング領域に設けるようにした特許請求
範囲第1項記載のマトリクス駆動形素子の電極製造力法
[Claims] 1. On a semiconductor layer formed on a semiconductor substrate or an insulating substrate, a large number of electrodes are insulated and separated from the semiconductor substrate or the semiconductor layer by an insulating film and each wired approximately in parallel. When manufacturing a matrix-driven element having busbars, the ends of the individual electrode busbars are extended, and busbar connection wiring portions are provided for electrically connecting two electrode busbars so that the wiring meander continuously. The disconnection of the electrode bus bar and the short circuit between the electrode bus bar and the semiconductor substrate or between the electrode bus bar and the semiconductor layer can be prevented by conducting current between both ends of the wiring and passing current between the wiring end and the semiconductor substrate or the wiring end. 1. A method of manufacturing an electrode for a matrix-driven element, characterized in that the bus-bar connection wiring section is removed after being inspected by passing current between the bus-bar connection wiring section and the semiconductor layer. 2. The removal of the busbar connection wiring portion is performed by wet etching or dry etching.
A method for manufacturing electrodes of a matrix-driven element as described in . 3. The method of manufacturing an electrode for a matrix-driven element according to claim 1, wherein the removal of the busbar connection wiring portion is performed by cutting the semiconductor substrate or the semiconductor layer. 4. The electrode manufacturing method for a matrix-driven element according to claim 1, wherein the busbar connection wiring portion is provided in a dicing area of the semiconductor substrate or the semiconductor layer.
JP55037573A 1980-03-26 1980-03-26 Electrode manufacturing method for matrix-driven elements Expired JPS5945992B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55037573A JPS5945992B2 (en) 1980-03-26 1980-03-26 Electrode manufacturing method for matrix-driven elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55037573A JPS5945992B2 (en) 1980-03-26 1980-03-26 Electrode manufacturing method for matrix-driven elements

Publications (2)

Publication Number Publication Date
JPS56135887A JPS56135887A (en) 1981-10-23
JPS5945992B2 true JPS5945992B2 (en) 1984-11-09

Family

ID=12501267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55037573A Expired JPS5945992B2 (en) 1980-03-26 1980-03-26 Electrode manufacturing method for matrix-driven elements

Country Status (1)

Country Link
JP (1) JPS5945992B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112019002141B4 (en) 2018-04-25 2022-12-15 Toyota Shatai Kabushiki Kaisha Shock-absorbing element and its manufacturing process

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0830820B2 (en) * 1986-03-07 1996-03-27 セイコー電子工業株式会社 Matrix display
JP2015050327A (en) * 2013-09-02 2015-03-16 株式会社東芝 Photoelectric conversion substrate and radiation detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112019002141B4 (en) 2018-04-25 2022-12-15 Toyota Shatai Kabushiki Kaisha Shock-absorbing element and its manufacturing process

Also Published As

Publication number Publication date
JPS56135887A (en) 1981-10-23

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