JPS5947895B2 - analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel analog-to-digital converter (hereinafter referred to as A/
(referred to as a D converter), in particular, the level of the input signal is roughly detected in advance by an auxiliary comparator,
The present invention relates to a low power consumption type parallel A/D converter that appropriately operates only a group of comparators divided into a predetermined number based on the results.

In recent years, the need for high speed A/D converters used in the video band has increased.

There are various types of A/D converters, such as successive approximation type, follow-up comparison type, and parallel comparison type, each having its own characteristics.

Here, the parallel comparison type prepares a reference voltage source and a comparator in parallel for each quantization level, and compares the analog human input signal with the reference voltage of each quantization level at the same time. Conversion can be made faster during conversion.

In other words, this parallel type requires (2n-1) comparators to achieve n-bit resolution accuracy, but it is ideal as a high-speed A/D converter for video bands because it compares input analog signals simultaneously. I can say it.

However, the major disadvantage of parallel A/D converters is that they require (2n-1) comparators as mentioned above, so increasing the number of bits dramatically increases the number of comparators, resulting in extremely high power consumption. It's about getting bigger.

For example, in the case of 8 bits, the number of comparators is 255, which is 1
If the current consumption per comparator is 1mA, the total is 255m.
A, and assuming the power supply voltage is 6■, the power consumption is approximately 1.
It becomes 5W.

Therefore, the entire A/D converter requires a power consumption of about 2 W, and if a parallel A/D converter is constructed with high speed and high accuracy, the power consumption becomes extremely large, making it impractical.

This drawback was proposed in Japanese Patent Application No. 54-24005, the basic idea of which is to use a plurality of comparators arranged in parallel and having a reference voltage corresponding to each quantization level. Prior to the comparison operation of the comparator, the analog signals are compared by an auxiliary comparator, and based on the comparison result, only a predetermined group is operated for comparison.

Figure 1 shows its basic configuration. In FIG. 1, 1 is an analog signal input terminal, 2 is an auxiliary comparator, and 3 is a current driver that operates only the corresponding comparator group of the comparators 4 in accordance with the comparison result of the auxiliary comparator.

5 is a matrix encoder that encodes the output of the comparator into an n-bit digital signal.

6 is an output buffer and 7 is a digital output terminal.

Although this method is an effective method for reducing power consumption without reducing conversion speed, problems arise when the input signal has a maximum amplitude and a high frequency.

FIGS. 2A to 2C show charts explaining the reason.

As shown in Fig. 2A and B, after the input signal IN exceeds the reference level (comparison level) RL of the auxiliary comparator, the current RI of the predetermined comparator group of the regular comparator 4 rises and the comparator operates. A certain delay time "t," occurs until the start of the process.

However, the input signal IN has been changing rapidly during this time, and the input signal level when the regular comparator judges the input signal has shifted by at least A,/l since the auxiliary comparator makes a judgment. Become.

Moreover, when the frequency of the input signal is high, this deviation Ad'' becomes considerably large.

Note that R3 is a latch signal, by which the input signal IN is input.

For example, if the input signal is a 4MHz sine wave and the amplitude is the maximum amplitude, then if td = 10ns, Ad = sinω・
Since td(1), Ad:0.25.

In other words, the deviation is approximately 0.25M5B.

If we use an 8-bit A/D converter, IMSB=256L
Since it is SB, the deviation is 64LSB.

Therefore, in order to compensate for this deviation, at least 64 comparators must operate simultaneously.

In other words, the number of divisions of a regular comparator can only be made into four blocks at most, and the power consumption can only be reduced by 100% compared to the conventional parallel comparison type in which all comparators work.

On the other hand, ideally, this method should be able to reduce power consumption by approximately ↑.

Therefore, the present invention attempts to solve the above problem by providing a phase circuit to minimize the level difference between the input signal determined by the auxiliary comparator and the input signal of the regular comparator. be.

The details of the present invention will be explained below with reference to the drawings.

FIG. 3 shows an embodiment of the invention.

In FIG. 3, numerals 1 to 7 are the same components as those in FIG. 1.

Reference numeral 8 denotes a phase circuit which is a feature of the present invention and is intended to correct the delay caused by the auxiliary comparator 2 and the current driver 3 by advancing the phase of the input signal of the instrument.

FIG. 4 shows an example of a specific circuit configuration of the phase circuit.

1 in the figure is the same as that in FIG. 3, and is an input terminal for analog signals.

101 and 102 are resistors, 103 are capacitors,
104 is an amplification circuit.

Next, the characteristics of the phase compensation performed by the circuit shown in FIG. 4 will be explained.

Assuming that the gain of the amplifier 104 is A and the delay time td in the auxiliary comparator and current driver, the transfer characteristic of the entire circuit is expressed by the following equation.

Note that here, τ and α are τ=R1・co(3) R2 (4) R1+R2 It is a constant expressed as .

The phase P and absolute value Ab of the transfer function expressed by equation (2) are expressed by the following equation.

Therefore, the analog input signal applied to terminal 1 and (
2) The difference from the signal having the transfer characteristic expressed by the equation is expressed by the following equation.

△Ab=1+Ab'-2・AbcosP (7) Ideally, the values of R1, R2, and C and the amplification rate A of the amplifier 104 should be selected so that △Ab becomes O. A/
It is impossible to set the input signal to O over the entire band of the input signal of the D converter.

However, by choosing the above constants appropriately, △
It is possible to make the value of A sufficiently small, thereby reducing the number of comparators that must be operated at the same time, and making the power consumption lower than the conventional sound.

For example, when td=15ns, R1=3Ω, R2=
Ω to 1.3.

If Co=5PF and A=3.2, △Ab is 0.05M5B up to the input signal frequency of 5MHz as shown in Figure 5.
It can be placed within.

In other words, the number of comparators that can be operated simultaneously can be reduced to six, which is the total number of comparators.

On the other hand, in view of total power consumption, it is actually most efficient to set the number of operational comparators to 29, so it is necessary to determine the number of comparators to be operated simultaneously according to the number of bits.

Next, a circuit showing a more specific embodiment of the present invention is shown in the sixth section.
As shown in the figure.

FIG. 6 shows an example of a 6-bit A/D converter.

In FIG. 6, 1 is an analog terminal, which is the same as that in FIGS. 1 and 3, 202 is a matrix encoder circuit, and 203 is a reference voltage input terminal.

C1 to C63 are 63 regular comparators, which compare the analog input voltage VIN and a voltage obtained by dividing the reference voltage.

R is a reference voltage dividing resistor provided corresponding to the comparators C1 to C63.

■N■2 to ■N■63 are inverters that invert the output signals of the comparators C2 to C63, respectively.

A1 to A63 are 3 provided corresponding to comparators C1 to C63.
In the manual AND gate, the first input directly applies the output of the corresponding comparator, the second input applies the output of the adjacent comparator through an inverter, and the third input applies the output of the auxiliary comparator, which will be described later. Apply.

L1 to L6 are output buffers provided for lowering the output impedance and converting the output level.

SC1 to SC3 are auxiliary comparators and regular comparators C1 to C6
It is provided at a position where a reference voltage that divides 3 into approximately 4 equal parts is input.

In this case, the 16th and 32nd of regular comparators C1 to C63
The same reference voltage as the 48th and 48th is used as one input.

Therefore, the auxiliary comparator SC1 is at the same comparison level as the comparator C16, the auxiliary comparator SC2 is at the same comparison level as the comparator C32, and the auxiliary comparator SC3 is at the same comparison level as the comparator C48.

Next, INV'1 to ■N■'3 are inverters, which invert the outputs of the auxiliary comparators SC1 to SC3, respectively.

Also, A'1 to A'4 are AND gates, A'1 inputs the output of the auxiliary comparator SC1, and A'2 is the inverter INV.
The output of '1 and the output of the auxiliary comparator S02 are input, A'3 is the input of the output of the inverter IN■'2 and the output of the auxiliary comparator S03, and A'4 is the input of the inverter I
The output of NV'3 is used as input.

Here, the two AND gates A'1 and A'4 are not necessarily required.

In the case of this embodiment, the AND gates A'2 and A'3 are provided in order to match their outputs, amplitudes, impedances, etc.

Buffer drivers L'1 to L'4 are provided to turn on and off the currents of the comparators for each block using the outputs of the AND gates A'1 to A'4.

Here, comparators 01 to C16 are assigned to A block, comparator 01
7 to C3□ are designated as a B block, comparators C33 to C48 are designated as a C block, and comparators C48 to C63 are designated as a D block.

The configuration up to this point is the configuration described in Japanese Patent Application No. 54-24005, and the following parts are newly added elements according to the present invention.

R1 and R2 are resistors C8 are capacitors which are the same as those shown in FIG. 4, and AMP is an amplification circuit indicated by 104 in FIG.

Next, the operation of the embodiment shown in FIG. 6 will be explained.

The analog input signal applied to terminal 1 is first applied to R1, R
2, co, auxiliary comparators SC1 to SC3, AND gates A'1 to A'4°, and delay times at drivers L'1 to L'4 and comparators C1 to C.
The phase is advanced in a pseudo manner so as to compensate for the total rise time of 63 currents.

Thereafter, the voltage is appropriately amplified by the amplifying circuit AMP, and then applied to the auxiliary comparators SC1 to SC3, where it is compared with the voltage corresponding to each auxiliary comparator.

Now, if the reference voltage IHIV is applied to the terminal 203, the comparison judgment levels of the auxiliary comparators SC1 to S03 are 0 and 7, respectively.
5V, 0.5V, 0.25V.

For example, if the analog input signal is 0.6V, the auxiliary comparator SC1 determines that it is lower than the comparison level and outputs "
0", and the auxiliary comparators SC2 and SC3 determine that it is higher than the comparison level and output "1".

Therefore, the output of each inverter is INV'1 is l'', I
N■'2 becomes "0", INV'3 becomes "0'", and the input of each AND gate is "1", only the input of A'2 becomes "1", and the other AND gate A'l , A'3
．． The input of A'4 is "0" and "'1" or "'0".
'' and ``0'', and each output of the AND gate is ``1'' for A''2 and ``0'' for the others.
The output of '4 is connected to the third input of AND gates A1 to A63 provided between the regular comparator and the matrix encoder 202.

More specifically, A1-A16 of block A of A'l
to the input of A'2, the output of A'2 is A1□~A of block B
32, the output of A'3 is A33 to A of block C.
48, the output of A'4 is A4g to A of block D.
63 input.

Therefore, the output of A'2 becomes "1"', and A'1.
A'3. Since the output of A'4 is "0", only the AND gates A17 to A32 of block B are open, and the outputs of the AND gates of other blocks are all forced to "0". It has become.

This is a circuit for maintaining the input of the matrix encoder 12 in a correct state, no matter what the output state of the non-operating regular comparator is.

Next, buffer drivers L'1 to L'4 control the operating currents of ratios C1 to C63 for each block.

Now, the input of buffer drivers L'1 to L'4 is "1"
If the configuration is configured such that current flows through comparators 01 to C63 and the comparators are operated only when , all other comparators stop working.

On the other hand, the analog input signal applied to terminal 1 is
1 to C63, and only the comparator in block B is operating, so only the comparators C17 to C32 compare the voltage corresponding to each comparator and convert it into a digital signal. be done.

At this time, what is different from that in the specification of Japanese Patent Application No. 54-24005 is that the analog input signal directly applied to the comparators C1 to C63 and the auxiliary comparators SC1 to SC
After being compared in step 3, the error due to time delay between the current turned on and off for each block of the comparator is extremely small, and as a result, there is no error when using high-speed analog input signals. It is.

This embodiment shows an example in which all comparators are divided into 4 blocks in the case of 6 bits, but this is for the purpose of simplifying the explanation.
In reality, a greater effect can be expected when the comparator is divided into many blocks with higher precision (larger number of bits).

As explained above based on the embodiments, the present invention provides a phase advance circuit composed of a resistor and a capacitor between the auxiliary comparator and the input signal terminal, thereby reducing the delay time generated between the auxiliary comparator and the current driver. This is an attempt to minimize the phase difference and absolute value difference between the input signal terminal and the signal directly led to the regular comparator. The same effect can also be achieved by providing it between the input device and the input device.

However, passing the input signal to a regular comparator through a phase circuit directly leads to deterioration of the accuracy of the A/D converter itself, and the delay circuit is usually one with excellent group delay characteristics. The drawback is that it requires the use of inductance to construct it, making it unsuitable for integrated circuits.

In contrast, the present invention is capable of maintaining accuracy because the input signal itself applied to the comparator is not modified, and because the phase circuit can be configured with a resistor and a capacitor, integration into an integrated circuit is possible. It has the feature of being easy.

In the embodiment shown in FIG. 4, the overall transfer function was set by providing an amplification circuit 104, but in order to provide gain A, it is not necessary to use an amplification circuit, and an auxiliary comparator and a regular A similar effect can be obtained by setting the ratio of the reference voltages of the comparator to A.

As described above in detail, the present invention can significantly reduce power consumption without deteriorating conversion speed and accuracy, has a simple configuration, and is suitable for integrated circuit implementation. This provides a parallel comparison type A/D converter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an A/D converter that has already been applied for.
2A to 2C are timing charts showing the problems of the A/D converter that has already been applied for, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a specific example of the phase circuit according to the present invention. FIG. 5 is a characteristic diagram illustrating a detailed explanation of the present invention, and FIG. 6 is a circuit diagram showing a specific embodiment of the present invention. 1...Input terminal, 2...Auxiliary comparator,
3... Current driver, 4... Comparator,
5... Matrix encoder, 6...
Output sofa, 7... Output terminal, 8...
・Phase circuit.

Claims (1)

[Claims] 1. A plurality of comparators having reference voltages corresponding to each quantization level and arranged in parallel, and dividing the plurality of comparators into a predetermined number, and each of the divided comparators having a reference voltage corresponding to each quantization level. an auxiliary comparator provided for each comparator group, the input signals are compared by the auxiliary comparator, and each of the comparators in the comparator group In the analog-to-digital converter that operates based on the comparison result of the auxiliary comparator, the input signal is applied to the auxiliary comparator via a phase circuit, and is also directly input to the comparator group. Characteristic analog/digital converter. 2. In the analog-to-digital converter according to claim 1, the phase circuit connects a first resistor and a capacitor in parallel, and connects a second resistor to the first resistor and capacitor. An analog-to-digital converter characterized in that the converter is connected in series with the converter. 3. In the analog-to-digital converter according to claim 1, the phase circuit connects a first resistor and a capacitor in parallel, and connects a second resistor in series with the first resistor and capacitor. 1. An analog-to-digital converter comprising: an amplification circuit for amplifying the output signal of the phase circuit; 4. In the analog-to-digital converter according to claim 1, the phase circuit connects a first resistor and a capacitor in parallel, and connects a second resistor in series with the first resistor and capacitor. An analog-to-digital converter characterized in that the reference voltage of the auxiliary comparator and the reference voltage of the comparator are set at a predetermined ratio.