JPS5947894B2 - analog to digital converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter (hereinafter referred to as an A/B converter), and in particular to a parallel type analog converter that simultaneously compares a human signal with a reference signal using a plurality of comparators.・Regarding digital converters, more specifically, parallel analog-to-digital conversion that achieves the most efficient reduction in power consumption by dividing and driving comparators arranged in parallel by weighted numbers. It is related to vessels.

In recent years, the need for high speed A/B converters used in the video band has increased.

Now, there are various types of A/D converters, such as successive approximation type, follow-up comparison type, and parallel comparison type, each with its own characteristics.

Here, the parallel comparison type prepares a reference power supply and a comparator in parallel for each quantization level, and simultaneously compares the analog input signal with the reference voltage of each quantum level. Among them, i is also the fastest.

In other words, this parallel type requires (2°-1) comparators to achieve n-bit resolution accuracy, but since the input analog signals are compared simultaneously, it is a high-speed A/D for analog input signals in the video band. It can be said that a parallel comparison type is optimal as a converter.

The 8-bit parallel A/D converter will be explained below with reference to the drawings.

FIG. 1 is a block diagram of an 8-bit A/D converter,
In the case of 8 bits, the comparator and reference power supply are 28-1=25
There are 5 pieces.

In the same figure: R is a resistance for generating the reference voltage, C1, C
2, . . . C25° are comparators that compare the reference voltage and the input analog signal, and each has the same resolution.

A1. A2. ...A255 is an AND circuit, Ll
, L2. ...L8 is a latch circuit.

1 is an analog signal input terminal, 2 is a die; an encoder circuit consisting of an ode matrix, etc., and 3 and 4 are clock pulse generation circuits, CI, C2, etc., respectively.
C255 and Ll, L2. ...Connected to L8.

Next, the operation will be explained using FIG. 2 showing waveforms of each part.

Assume that an analog input signal a and a reference signal S are applied to the comparator C4 on plywood.

Pulses c and d are applied to the comparator C4 by the clock pulse generation circuit 3, and a comparison operation is performed when the pulse C is at a high level, and a latch operation is performed when the pulse d is at a high level.

Therefore, the comparator C4 generates a comparison signal such as e, performs waveform shaping, and outputs an output signal such as f.

Here, at time T1, if the outputs of only the comparators 01 to C4 are at a high level, the output of only the AND circuit A4 is at a high level and is input to the encoder circuit 2.

The output of encoder circuit 2 is latch circuit L1...
The signal is input to L8, and output to terminals D1...D8 as A/D conversion outputs in synchronization with clock pulses c and d.

Now, the parallel type A/D converter mentioned above has 8 bits and 2
It is composed of 55 comparators, so if a current of 1 mA is supplied to each comparator, a large current of 255 mA is required, and if a 5 V power supply is used, the power consumption of the comparators alone is about 1.3 W. Therefore, a total power consumption of about 2W is required.

Therefore, if a high-speed, high-precision parallel A/D converter is constructed, the power consumption becomes extremely large, making it impractical.

In order to compensate for this drawback, in the specification of Japanese Patent Application No. 54-24005, a plurality of comparators having reference voltages corresponding to each quantization level and arranged in parallel are divided into a plurality of groups, and the We have proposed an A/D converter in which analog signals are compared by an auxiliary comparator prior to the comparison operation of the converter, and based on the comparison result, only a predetermined group is operated for comparison.

A conceptual diagram of the A/D converter shown in FIG. 3 is shown.

In FIG. 3, C is a comparator arranged in parallel corresponding to each quantization level, and SCI to SC3 are auxiliary comparators, respectively.

The basic configuration of the present invention is that the comparator C arranged in parallel with the analog input signal is divided into several blocks as shown in Figure 3 (in the case of the embodiment shown in Figure 3, it is divided into four blocks A to D). ),
Auxiliary comparators SC1 to SC3 are provided that have the same judgment level as the comparator that detects the voltage at the boundary of the block. , D, and as a result of that judgment, only the comparator group of the predetermined block is operated, and the operating current of all the comparator groups of other blocks is cut off or reduced. This is intended to reduce the current consumption of the entire A/D converter.

Table 1 shows the status of the auxiliary comparators and blocks.

For example, when the analog input voltage is equal to the judgment level (quantization level) of the comparator in block B, the auxiliary comparator S01 judges that the analog input voltage is lower than the judgment level of the auxiliary comparator SCI, and the output is 0'' becomes.

The auxiliary comparators SC2 and SC3 determine that the level is higher than the determination level of the auxiliary comparators SC2 and SC3, and both outputs become "1".

Therefore, at this time, only the regular comparator in block B operates, all others stop operating, and the comparator in block B accurately determines the analog signal voltage and converts it into a digital signal. be.

Therefore, in this case, if the operating current of the comparators in blocks A, C, and D is completely reduced to 0, the current consumption of the entire A/D converter will be approximately 174 times lower than that of the conventional method in which all comparators are always working. can be reduced to

Of course, as the number of blocks and the number of auxiliary comparators increases, the current reduction rate also increases.

Conversely, however, if the number of auxiliary comparators is increased beyond a certain point, the current consumption of the auxiliary comparators increases to exceed the amount due to the reduction in the number of regular comparators.

For example, in the case of an 8-bit A/D converter with 255 comparators, the current consumption can be minimized when divided into 16 blocks, and the current consumption in this case is about 17
It becomes 8.

As explained above, the A/D converter described in Japanese Patent Application No. 54-24005 is an extremely effective converter for reducing power consumption without reducing conversion speed.

However, if power consumption is reduced by increasing the number of comparator blocks, a problem may arise in accuracy if the input signal has a high frequency.

This is because a delay time actually occurs between the comparison operation of the auxiliary comparator and the start of operation of the regular comparator, so when a high frequency input signal is applied, the input determined by the auxiliary comparator There will be a difference between the signal level and the signal level manually applied to the regular comparator, and in the unlikely event that the level of the input signal applied to the regular comparator and the group of regular comparators that have started operating are different. This is because if the levels of the corresponding reference voltages do not match, an error will occur.

If, in order to prevent this problem, the number of blocks in the comparator group is reduced and the number of comparators in each block is increased, a sufficient reduction in power consumption will not be achieved.

Therefore, the present invention is proposed in order to solve this problem, and when the comparators are grouped, a certain weighting is applied, and a group of comparators corresponding to a level where the input signal changes rapidly within a certain time is set. The block contains many comparators, and conversely, the comparator group that corresponds to the level where the input signal changes only slowly within a certain period of time contains fewer comparators in the block, which reduces power consumption. This is intended to improve efficiency.

That is, the present invention weights and divides a plurality of comparators having reference voltages corresponding to each quantization level and arranged in parallel into a plurality of groups, and prior to the comparison operation of the comparators, Analog signals are compared by an auxiliary comparator, and based on the comparison result, only a predetermined group is operated for comparison.

The present invention will be described below with reference to drawings and embodiments.

Considering a video signal as an analog signal input to an A/D converter, the color subcarrier has the highest frequency, and its waveform may be a sine wave.

In other words, with the NTSC system, if a 3.58 MHz sine wave can be converted, it is possible to convert a video signal into a digital signal.

Now, as shown in FIG. 4, the amplitude of the sine wave changes within the same time period differs depending on each signal level.

In other words, the widest change occurs around the time when it crosses "0", and if the total period is 8to, then t.

While the total amplitude changes by 0.35 during the period, there is a difference of 0.15L or no change around the peak.

Therefore, regarding the division of comparator blocks, configuring the number of comparators included in an l block in such a ratio is as follows:
Most efficient.

A specific configuration in which the comparators are divided into blocks at such a ratio is shown in FIG. 5, and its operation will be explained.

Note that FIG. 5 shows an example of a 6-bit A/D converter.

In FIG. 5, 11 is an analog input terminal, 12 is a matrix encoder circuit, and 13 is a reference voltage input terminal.

C'1 to C'63 are 63 regular comparators, which compare the analog input voltage ln with a voltage obtained by dividing the reference voltage.

R' is a reference voltage dividing resistor provided corresponding to the comparators C'1 to C'63.

INV2 to INV63 are inverters that invert the output signals of the comparators C'2 to C'63, respectively.

A''1 to A'63 are three-man powered AND gates provided corresponding to the comparators C'1 to C'63, the first input directly applies the output of the corresponding comparator, and the second input The input is the output of an adjacent comparator applied through an inverter, and the third input is applied the output of an auxiliary comparator, which will be described later.

L'1 to L'6 are output cover sofas provided for lowering the output impedance and converting the output level.

Although the conventional parallel comparison type A/D converter has the same configuration as before, the present invention adds a new part to be described below.

First, S01 to SC3 are auxiliary comparators and are regular comparators C'
1 to C'63 are provided at positions where reference voltages to be divided into four by weighted comparison described above are input.

In this case, the 10th of regular comparators C'l to C'63,
The same reference voltage as the 32nd and 42nd ones is used as one input.

Therefore, the auxiliary comparator SC1 is at the same comparison level as the comparator C'10, the auxiliary comparator SC2 is at the same comparison level as the comparator C'32, and the auxiliary comparator SC3 is at the same comparison level as the comparator C'32.

Next, INV'l to INV'3 are inverters that invert the outputs of the auxiliary comparators SC1 to SC3, respectively.

Also, A″1 to A″4 are AND gates, A″1 inputs the output of the auxiliary comparator SC1, and A″2 is the inverter INV.
'l output and the output of auxiliary comparator SC2 are input, A"3 has the output of inverter INV'2 and auxiliary comparator SC3 as input, and A"4 has inverter INV'2 and the output of auxiliary comparator SC3 as input.
The output of NV'3□ is used as input.

Here, the two AND gates A″1 and A″4 are not necessarily required.

In this embodiment, the AND gates A''2 and A''3 are provided in order to match their outputs, amplitudes, impedances, etc.

L″1 to L″4 are buffer drivers and gate A
It is provided to turn on and off the current of the comparator for each block with the output of "1 to A"4.

Here, comparators C'1 to C'IO are placed in A block, comparators C'11 to C'32 are placed in B block, and comparators C'33 to C'32 are placed in B block.
Let C42 be a C block, and comparators C'43 to C'63 be a D block.

Next, the operation of the embodiment shown in FIG. 5 will be explained.

The analog input signal applied to terminal 1 is first compared with the voltage corresponding to each auxiliary comparator in auxiliary comparators SC1 to SC3.

Now, if the reference voltage IV is applied to the terminal 13, the comparison judgment level of each of the auxiliary comparators SC1 to SC3 is 0.844.
V, 0.5V, 0.156V.

For example, if the analog human input signal is 0.6V, the auxiliary comparator SCI determines that it is lower than the comparison level and outputs "0.
'', and the auxiliary comparators SC2 and SC3 determine that the level is higher than the comparison level, and set the output to ``1''.

Therefore, the output of each inverter is INV' 1 = 441
99, INV'2 is tg Ott, INV'3 is gg
Ott, and the input of each AND gate is only the input of A″2, both inputs are 1″, and the other gates are 1″.
A” 1. A” 3. A” 4 inputs are “0” and 1”
Or '0' and PA0'', and each output of the AND gate becomes '1' for A'''2 and '0' for the others.

The outputs of the antenna gates t4''1 to A''4 are connected to an amplifier provided between the regular comparator and the matrix encoder 12.

It is connected to the third input of gates A'1 to A'63.

More specifically, A'l to A' of block A of A″1
To the input of IO, the output of A″2 is A′11~ of block B.
to the input of A'32, A''3 is A'33 of output block C
~A′42 input, A″4 output is A of block 1D
It is connected to the inputs of '43 to A'63.

Therefore, the output of A"2 becomes "1", and A"1.
Since the output of A"3゜A"4 is 0', only the AND gates A'11 to A'32 of block B are in the open state, and the gates of the AND gates of the other blocks are in the open state. All outputs are forced to "0".

This is a circuit for maintaining the input of the matrix encoder 12 in a correct state, no matter what the output state of the non-operating regular comparator is.

Next, buffer drivers L''1 to L''4 control the operating currents of comparators C'1 to C'63 for each block, respectively.

Now, the input of buffer driver Lll~L″4 is “1”
If the configuration is such that current flows through comparators C'1 to C'63 and the comparators operate only when , AND gate A
When the output of "2" is "1", comparators C'11 to C'32
only one comparator operates, and all other comparators stop operating.

The subsequent operations are performed in exactly the same manner as before.

At this time, if the operation of the other comparators is stopped by not allowing the comparison current to flow, only the 22 comparators in block B are actually operating, so the current consumption of the entire comparator is approximately It can be reduced to 1/3.

However, since the three auxiliary comparators must be operated at all times, this will increase the number of comparators, but this will not be a problem as it is small compared to the number of regular comparators.

Note that in the above case, block B is activated.

As a result, the current consumption is only about 173, which is disadvantageous compared to the case where the comparator is divided evenly like the ND converter that has already been applied for. Since the number is 10 each, the power consumption is approximately 176, which approaches 1/4 on average.

Also, in this example, 6 bits are divided into 4, and there is no big advantage compared to the ND converter that has already been applied for. However, this is done for convenience of explanation, and is divided into 8, 16, etc. As the amount of data increases, in the case of the previous A/D converter, the risk of errors increases and the number of divisions cannot be increased too much, whereas in the case of the present invention, even if the number of divisions is increased, errors do not occur. This allows for a higher frequency A/D conversion.

Table 2 shows the state when comparator blocks other than block B are moved in the embodiment shown in FIG.

As specifically described in the embodiments above, the feature of the present invention is that by using a weighted auxiliary comparator,
This method operates only some comparators and reduces the operating current of other comparators to 0 or decreases for a certain hour.
In addition, many comparators are used for areas where the input signal changes significantly, allowing for high precision and high power consumption without losing the high speed that is the excellent feature of the parallel comparison method. It is possible to realize an A/D converter with a small number of digits.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional parallel A/D converter, Figure 2 is a block diagram of a conventional parallel A/D converter.
The figure is a timing diagram showing the operation of the A/D converter, Figure 3 is a basic conceptual diagram of the A/D converter, and Figure 4 is the A/D converter of the present invention.
FIG. 5 is a block diagram showing an embodiment of the present invention. C'1 to C'63... Comparator, SC1 to SC
3...Auxiliary comparator, A'1 to A'63...
...3 person Kaand gate, A″1~A″4...
- Two-person gate, L'1 to L'6...output buffer, L''1 to L''4...buffer driver, INVI to INV63. INV″1～INV'3
...Inverter, R'...Resistor, 11
... Analog input terminal, 12 ... Matrix encoder, 13 ... Reference voltage source.

Claims (1)

[Claims] 1. A plurality of comparators having reference voltages corresponding to each quantization level and arranged in parallel, and dividing the plurality of comparators into weighted numbers, and dividing the plurality of comparators into weighted numbers. and an auxiliary comparator provided for each comparator group, and the input signal is compared by the auxiliary comparator, and each pre-comparator in the comparator group is connected to the comparator group. An analog-to-digital converter that operates based on the comparison result of the corresponding auxiliary comparator. 2. The analog-to-digital converter according to claim 1, wherein the weighting ratio corresponds to the amount of change in the level of the sine wave at the same time.・Digital converter.