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JPS5948542B2 - Method for measuring deep impurity levels in semiconductors - Google Patents
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JPS5948542B2 - Method for measuring deep impurity levels in semiconductors - Google Patents

Method for measuring deep impurity levels in semiconductors

Info

Publication number
JPS5948542B2
JPS5948542B2 JP55160208A JP16020880A JPS5948542B2 JP S5948542 B2 JPS5948542 B2 JP S5948542B2 JP 55160208 A JP55160208 A JP 55160208A JP 16020880 A JP16020880 A JP 16020880A JP S5948542 B2 JPS5948542 B2 JP S5948542B2
Authority
JP
Japan
Prior art keywords
impurity levels
capacitance
temperature
deep impurity
semiconductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55160208A
Other languages
Japanese (ja)
Other versions
JPS5784145A (en
Inventor
秀世 大串
洋三 徳丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP55160208A priority Critical patent/JPS5948542B2/en
Publication of JPS5784145A publication Critical patent/JPS5784145A/en
Publication of JPS5948542B2 publication Critical patent/JPS5948542B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices

Landscapes

  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 本発明は、半導体中に含まれる深い不純物準位の測定方
法の改良に関し、深い不純物準位の情報をより正確に、
かつ簡単に得られるようにしたものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for measuring deep impurity levels contained in a semiconductor, and the present invention relates to improving a method for measuring deep impurity levels contained in a semiconductor.
And it is designed to be easily obtained.

深い不純物準位の測定を行うのに、pn接合やショット
キ・バリヤにおける空乏層にもとづく電気容量の時間変
化を調べる方法があり、最近この原理にもとづくいろい
ろな測定方法が提案され、半導体の評価技術として実行
されている。
To measure deep impurity levels, there is a method of examining the time change in capacitance based on the depletion layer in a pn junction or Schottky barrier.Recently, various measurement methods based on this principle have been proposed, and semiconductor evaluation technology has improved. is being run as.

これらの測定方法では、電気容量の時間変化の時定数が
直接に深い不純物準位の熱放射割合(emission
rate)の逆数に対応するという仮定に基づいており
、従つて、実際には電気容量の時間変化、dC(を)を
直接に電圧の時間変化に変換した信号を’測定し、これ
を解析することによつて測定をなしている。従来のこの
種測定法の具体的一例として、p゛n接合の場合につい
て説明する。
In these measurement methods, the time constant of the temporal change in capacitance is directly determined by the thermal radiation rate (emission) of deep impurity levels.
It is based on the assumption that it corresponds to the reciprocal of the rate), and therefore, in reality, the time change in capacitance, dC, is directly converted into the time change in voltage, and a signal is measured and analyzed. Measurements are made by As a specific example of this type of conventional measurement method, the case of a pn junction will be described.

逆バイアスVRを印加している時のp”n接合の空乏層
による電気容量Coは、C”←゜■qksε。
The electric capacitance Co due to the depletion layer of the p''n junction when applying the reverse bias VR is C''←゜■qksε.

A″N、O/ 2(VD+VR)・・・・・・(1)で
与えられる。ここでqは電荷量、に、ε。はp″’n接
合を形成している半導体の誘電率、Aは接合の断面積、
N、Oは空乏層におけるネットのイオン化された不純物
濃度、qVDは拡散ポテンシャルである。今、この状態
の接合に少数キャリヤあるいは多数キャリヤの注入パル
スを印加し、その後の時間を秒における電気容量の変化
Δc(を)を求めると、ΔC(を)■Co((1+ΔN
、(を)/N、O)”−1)・・・・・・・・・・・・
(2)あるいは、ΔNi(を)〈Nloであれば近似的
にΔC(を)■ −ΣΔN2(を) 2N、oi =−ΣΔN、O(O)exp(−−)・・・・・・・・
・・・(3)2N10iτ1で与えられる。
A″N, O/ 2 (VD + VR) (1) where q is the amount of charge, and ε is the dielectric constant of the semiconductor forming the p″’n junction. A is the cross-sectional area of the joint,
N and O are the net ionized impurity concentrations in the depletion layer, and qVD is the diffusion potential. Now, if we apply an injection pulse of minority carriers or majority carriers to the junction in this state and then calculate the change in capacitance Δc() in seconds, we get ΔC()■Co((1+ΔN
, (wo)/N, O)”-1)・・・・・・・・・・・・
(2) Or, if ΔNi()<Nlo, approximately ΔC()■ -ΣΔN2() 2N, oi =-ΣΔN, O(O)exp(--)...・
...(3) Given by 2N10iτ1.

ここで、ΔNi(O)はを=0でのΔN、(を)の値で
ありτ、はi番目の不純物準位での熱放射割合(電子及
び正孔に関してのこの値は夫々en及びepで定義され
る)による時定数でで与えられる。
Here, ΔNi(O) is the value of ΔN, () when = 0, and τ is the thermal radiation rate at the i-th impurity level (this value for electrons and holes is en and ep, respectively). is given by the time constant (defined by ).

この様に第(2)式あるいは第(3)式によれば電気容
量の時間変化の時定数が直接深い不純物準位の熱放射割
合の逆数τ”であることが示される。
In this way, Equation (2) or Equation (3) shows that the time constant of the change in capacitance over time is directly the reciprocal of the heat radiation rate of the deep impurity level τ''.

そこで、従来は、まず電気容量の時間変化Δc (t)
を電圧の時間変化に変換した信号として直接に取り出し
、これを適当な解析装置を通じて深い不純物準位の熱放
射割合を求めていた。この時、信号の解析方法としては
、大きく区別して次に述べる2つの方法が採用されてき
た。まず、1番目としてはアナログ信号であるΔC(t
)の内容をある特定の時間T,とT2の値だけ選んでア
ナログ的に処理して行う方法で、DLTS法と一般に呼
ばれている解析方法である。
Therefore, conventionally, first, the time change in capacitance Δc (t)
This was directly extracted as a signal converted into a voltage change over time, and this was used to determine the heat radiation rate of deep impurity levels using an appropriate analysis device. At this time, the following two methods, which are broadly classified, have been adopted as signal analysis methods. First, the analog signal ΔC(t
) is analyzed in an analog manner by selecting only the values of certain times T and T2, and is an analysis method generally called the DLTS method.

もう1つの方法は、アナログ信号をA/Dコンバータを
通じてデイジタル信号に変換し、この値を電子計算機に
記憶させ、これを解析することによつて情報を得ようと
するもので、ICTS法と名付けられている。
Another method is to obtain information by converting an analog signal into a digital signal through an A/D converter, storing this value in a computer, and analyzing it. This method is called the ICTS method. It is being

DLTS法の大きな特徴は、深い不純物準位のエネルギ
ーギヤツプ内の分布プロフアイルを求めるのに、試料の
温度を連続的に変化させながら行うことで、このため求
めるプロフアイルが簡単に得られるという利点がある。
A major feature of the DLTS method is that the distribution profile within the energy gap of deep impurity levels is determined by continuously changing the temperature of the sample, which makes it easy to obtain the desired profile. There is an advantage.

しかし、温度を連続的に変化させることは測定の精度の
点からすると大きな問題であり、また測定の自動化とい
う点でも困難な面があつた。一方、ICTS法は前述の
DLTS法の欠点を改善するために提案された方法で、
温度を連続的に変化させなくても一定温度において、ギ
ヤツプ内の不純物準位のプロフアイルを求めるものであ
るが、多くの利点を持つものの現在の測定器の能力から
DLTS法の様に広範囲のエネルギー分布の測定には適
していない。
However, continuously changing the temperature is a big problem in terms of measurement accuracy, and it is also difficult to automate the measurement. On the other hand, the ICTS method is a method proposed to improve the shortcomings of the above-mentioned DLTS method.
This method obtains the profile of the impurity level in the gap at a constant temperature without continuously changing the temperature, but although it has many advantages, it is not possible to use a wide range of methods such as the DLTS method due to the capabilities of current measuring instruments. Not suitable for measuring energy distribution.

この様に現状ではエネルギー分布を簡便に求めるのであ
ればDLTS法がよく、正確に深い不純物準位のパラメ
ータを決定したい時は、ICTS法が適していると云え
る。
As described above, at present, the DLTS method is suitable for simply determining the energy distribution, and the ICTS method is suitable for accurately determining parameters of deep impurity levels.

本発明は上記の点にかんがみ、両者の方法が同時に実行
できる新規な測定方法を提供することを目的とするもの
である。
In view of the above points, it is an object of the present invention to provide a novel measuring method in which both methods can be performed simultaneously.

以下本発明について説明する。添付図面はこの発明を実
施するための装置の一例を示すもので、Sは試料、1は
電圧パルスまたは光パルスを発生し試料Sに加えるパル
ス発生器、2は過渡容量計、3はシグナルアバレジヤま
たはロツキングアンプ等のアンプ、4はX−Yプロツタ
で、試料Sの温度に対するアンプ3の出力を記録する。
The present invention will be explained below. The attached drawings show an example of an apparatus for carrying out the present invention, in which S is a sample, 1 is a pulse generator that generates a voltage pulse or a light pulse and applies it to the sample S, 2 is a transient capacitance meter, and 3 is a signal aperture. 4 is an X-Y plotter that records the output of the amplifier 3 relative to the temperature of the sample S.

以上で従来のDLTS法による測定部Iが構成される。
また、5は高速A/Dコンバータ、6はインターフエー
ス、7は電子計算機、8Jはデイスプレイ装置、9はA
/Dコンバータであり、これらで、従来のICTS法に
よる測定部11が構成される。次に動作について説明す
る。
The measuring section I using the conventional DLTS method is configured as described above.
Also, 5 is a high-speed A/D converter, 6 is an interface, 7 is an electronic computer, 8J is a display device, and 9 is an A/D converter.
/D converter, and these constitute a measuring section 11 based on the conventional ICTS method. Next, the operation will be explained.

まず、第(2)式の左辺のΔc (t)を、試料S中・
の逆バイアス電圧VRを印加したp゛n接合、あるいは
シヨツトキ・バリヤから、光パルスまたは電圧パルスを
パルス発生器1から印加することにより取り出す。
First, let Δc (t) on the left side of equation (2) be
A light pulse or a voltage pulse is extracted from the pn junction or shot barrier to which the reverse bias voltage VR is applied by applying it from the pulse generator 1.

これ自体は在来の過渡容量計2や、その他のΔc (t
)またはc (t)を取り出すこノとができる容量計を
用いることによつてなされる。過渡容量計2から取り出
されたc(t)のアナログ信号に対して、シグナルアバ
レジヤやロツキングアンプ等のアンプ3を用いることに
よつて、・ある定められた時間T,とT。
This itself can be used with the conventional transient capacitance meter 2 or other Δc (t
) or c (t) by using a capacitance meter. By using an amplifier 3 such as a signal averager or a locking amplifier for the analog signal c(t) taken out from the transient capacitance meter 2, a certain predetermined time T and T are obtained.

での容量c(T,)とC(T。)の信号をアナログ的に
平均して求め、両容量c(T,)とc(T。)の差を試
料Sの温度の変化に対応してX−Yプロツタ4に記録さ
せて、いわゆるDLTS信号を得る。こ・までは従来の
DLTS法と同じであるが、本発明では、上記DLTS
法によつて温度をパラメータとして電気容量の時間変化
信号をアナログ的に処理して不純物準位の種類の個数を
測定し、これにより半導体中の深い不純物準位の概略を
把握・し、次に不純物準位の種類の個数のうち、精密に
測定したい不純物準位の種類が測定できる温度に試料で
ある半導体の温度を保ち、同時に過渡容量計2からのア
ナログ信号を高速A/Dコンバータ5を通してデイジタ
ル信号に変換し、これをマイ’クロコンピユータを内蔵
したインターフエイス6を介在して、波形解析の能力を
もつ電子計算機7に記録させ、深い不純物準位のパラメ
ータを第(4)式にもとづいて決定させ、その結果をデ
イスプレイ装置8に現出させる。
The signals of capacitances c(T,) and C(T.) at The signal is recorded on the X-Y plotter 4 to obtain a so-called DLTS signal. This is the same as the conventional DLTS method, but in the present invention, the above DLTS method is the same as the conventional DLTS method.
By analog method, the time-varying signal of capacitance is processed using temperature as a parameter to measure the number of types of impurity levels, and from this we can grasp the outline of deep impurity levels in the semiconductor, and then The temperature of the semiconductor sample is maintained at a temperature at which the type of impurity level that is desired to be precisely measured among the number of types of impurity levels is maintained, and at the same time, the analog signal from the transient capacitance meter 2 is passed through the high-speed A/D converter 5. The digital signal is converted into a digital signal, which is recorded in an electronic computer 7 capable of waveform analysis via an interface 6 with a built-in microcomputer, and the parameters of the deep impurity level are calculated based on equation (4). The result is displayed on the display device 8.

これがICTS法の解析方法によるICTS信号である
。図中の点線は制御線である。なお、第1図では、DL
TS法による解析を容易にするため、X−Yプロツタ4
に入力される信号をA/Dコンバータ9を介して電子計
算機7に同時に入力してデイジタル的に解析することも
できるようにしている。
This is the ICTS signal obtained by the ICTS analysis method. The dotted line in the figure is a control line. In addition, in Figure 1, DL
To facilitate analysis using the TS method, an X-Y plotter 4
It is also possible to simultaneously input the signals input to the electronic computer 7 via the A/D converter 9 and analyze them digitally.

上記1CTS法では、設定温度と過渡容量計2の過渡応
答速度の2つの条件で決まる不純物準位の情報を正確に
得ることができるが、通常は過渡容量計2の応答速度の
関係で1種類の不純物準位の情報に限られ、2種類以上
を同時に測定することは難しい。
In the above 1CTS method, it is possible to accurately obtain information on the impurity level determined by two conditions: the set temperature and the transient response speed of the transient capacitance meter 2, but usually there is only one type of impurity level information determined by the response speed of the transient capacitance meter 2. It is difficult to measure two or more types of impurity levels at the same time.

ところが、設定温度を変えては不純物準位の情報を得る
ような測定では1つの試料に対し莫大な測定回数と測定
時間を要することとなる。そこで、本発明ではDLTS
法によつて試料の設定温度を変えて不純物準位の種類の
個数を測定し、不純物準位の概略を把握してからICT
S法を適用するので、ICTS法を適用するときには設
定温度は決つているので、測定時間は大幅に短縮される
ことになる。
However, a measurement in which information on impurity levels is obtained by changing the set temperature requires a huge number of measurements and a huge amount of time for one sample. Therefore, in the present invention, DLTS
ICT method is used to measure the number of types of impurity levels by changing the set temperature of the sample, and after understanding the outline of the impurity levels.
Since the S method is applied, the set temperature is already determined when the ICTS method is applied, so the measurement time is significantly shortened.

以上述べたように、本発明は半導体のPn接合またはシ
ヨツトキ・バリヤ接合の空乏層の電気容量の変化信号を
アナログ的に取り扱うDLTS法によつて、まず未知の
試料に対して温度をパラメータにして深い不純物準位の
種類の個数を測定し、次いで、同じく電気容量の変化信
号をデイジタル的に取り扱い電子計算機を駆使するIC
TS法によつて、前記で求めた不純物準位の種類の個数
のうち所要の不純物準位が測定できる温度に試料を保ち
、その不純物準位の濃度、エネルギー位置、捕獲断面積
を求めるようにしたので、それぞれの特長を有効に使用
でき、また、それぞれの短所を補うことが可能となり、
両方法を単独に使用する場合と比較して格段と短時間に
、かつ、高精度に目的とする測定ができる利点がある。
As described above, the present invention first uses temperature as a parameter for an unknown sample using the DLTS method, which handles the change signal of the capacitance of the depletion layer of a semiconductor Pn junction or shot barrier junction in an analog manner. An IC that measures the number of types of deep impurity levels and then digitally handles the capacitance change signal and makes full use of an electronic computer.
Using the TS method, the sample is kept at a temperature at which the required impurity level can be measured among the number of types of impurity levels determined above, and the concentration, energy position, and capture cross section of that impurity level are determined. Therefore, it is possible to effectively use the features of each, and compensate for the weaknesses of each.
Compared to the case where both methods are used alone, there is an advantage that the desired measurement can be carried out in a much shorter time and with higher precision.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明を実施するための装置の一例を示すプロツ
タ図である。 図中、Sは試料、1はパルス発生器、2は過渡容量計、
3はアンプ、4はX−Yプロツタ、5は7高速A/Dコ
ンバータ、6はインターフエース、7は電子計算機、8
はデイスプレイ装置、9はA/Dコンバータ、IはDL
TS法による測定部、11はICTS法による測定部で
ある。
The drawing is a plotter diagram showing an example of an apparatus for carrying out the present invention. In the figure, S is the sample, 1 is the pulse generator, 2 is the transient capacitance meter,
3 is an amplifier, 4 is an X-Y plotter, 5 is a 7 high-speed A/D converter, 6 is an interface, 7 is a computer, 8
is the display device, 9 is the A/D converter, and I is the DL.
11 is a measuring section based on the TS method; and 11 is a measuring section based on the ICTS method.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体のpn接合またはショットキ・バリヤ接合の
空乏層の電気容量の変化から前記半導体中の深い不純物
準位の情報を測定するに際し、まず、DLTS法によつ
て温度をパラメータにして前記電気容量の時間変化信号
をアナログ的に処理して不純物準位の種類の個数を測定
し、次いでICTS法によつて前記で求めた不純物準位
の種類の個数のうち所要の不純物準位が測定できる温度
でその不純物準位の温度、エネルギー位置、捕獲断面積
を求めることを特徴とする半導体中の深い不純物準位の
測定方法。
1. When measuring information about deep impurity levels in a semiconductor from changes in the capacitance of the depletion layer of a pn junction or Schottky barrier junction of a semiconductor, first, the capacitance is measured using temperature as a parameter using the DLTS method. The time-varying signal is processed in an analog manner to measure the number of types of impurity levels, and then the ICTS method is used to measure the required impurity level among the number of types of impurity levels determined above. A method for measuring deep impurity levels in semiconductors, which is characterized by determining the temperature, energy position, and capture cross section of the impurity levels.
JP55160208A 1980-11-14 1980-11-14 Method for measuring deep impurity levels in semiconductors Expired JPS5948542B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55160208A JPS5948542B2 (en) 1980-11-14 1980-11-14 Method for measuring deep impurity levels in semiconductors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55160208A JPS5948542B2 (en) 1980-11-14 1980-11-14 Method for measuring deep impurity levels in semiconductors

Publications (2)

Publication Number Publication Date
JPS5784145A JPS5784145A (en) 1982-05-26
JPS5948542B2 true JPS5948542B2 (en) 1984-11-27

Family

ID=15710089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55160208A Expired JPS5948542B2 (en) 1980-11-14 1980-11-14 Method for measuring deep impurity levels in semiconductors

Country Status (1)

Country Link
JP (1) JPS5948542B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114834A (en) * 1982-12-21 1984-07-03 Agency Of Ind Science & Technol Method for measuring deep impurity level or crystal defect level contained in semiconductor device
JPS6034028A (en) * 1983-08-06 1985-02-21 Tokyo Daigaku Adaptive measurement of semiconductor trapping center
CN102944588A (en) * 2012-11-23 2013-02-27 中国科学院微电子研究所 A method for measuring the interface state parameters induced by etching of AlGaN materials with high Al composition

Also Published As

Publication number Publication date
JPS5784145A (en) 1982-05-26

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