JPS5941303B2 - Method for measuring deep impurity levels in semiconductors - Google Patents
Method for measuring deep impurity levels in semiconductorsInfo
- Publication number
- JPS5941303B2 JPS5941303B2 JP55101637A JP10163780A JPS5941303B2 JP S5941303 B2 JPS5941303 B2 JP S5941303B2 JP 55101637 A JP55101637 A JP 55101637A JP 10163780 A JP10163780 A JP 10163780A JP S5941303 B2 JPS5941303 B2 JP S5941303B2
- Authority
- JP
- Japan
- Prior art keywords
- deep impurity
- capacitance
- impurity levels
- equation
- semiconductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
Landscapes
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
本発明は、半導体中に含まれる深い不純物準位の測定方
法の改良に関し、深い不純物準位の情報をより正確に且
つ簡単に得るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for measuring deep impurity levels contained in a semiconductor, and is intended to more accurately and easily obtain information on deep impurity levels.
深い不純物準位の測定を行うのに、pn接合やショット
キ・バリヤにおける空乏層にもとづく電気容量の時間変
化を調べる方法があり、最近この原理にもとづくいろい
ろな測定方法が提案され、半導体の評価技術として実行
されている。To measure deep impurity levels, there is a method of examining the time change in capacitance based on the depletion layer in a pn junction or Schottky barrier.Recently, various measurement methods based on this principle have been proposed, and semiconductor evaluation technology has improved. is being run as.
これらの測定方法では、電気容量の時間変化の時定数が
直接に深い不純物準位の熱放射割合(emission
rate)の逆数に対応するという仮定に基づいており
、従つて、実際には電気容量の時間変化ΔC(を)を直
接に電圧の時間変化に変換した信号を測定し、これを解
析することによつて測定をなしている。In these measurement methods, the time constant of the temporal change in capacitance is directly determined by the thermal radiation rate (emission) of deep impurity levels.
It is based on the assumption that it corresponds to the reciprocal of the capacitance change ΔC (rate), and therefore, in reality, the signal obtained by directly converting the time change ΔC of the capacitance into the time change of the voltage is measured and analyzed. This is how the measurements are taken.
従来のこの種測定法の具体的1例として、pfn接合の
場合について説明する。As a specific example of this type of conventional measurement method, the case of a pfn junction will be described.
逆バイアスVRを印加している時のpfn接合の空乏層
による電気容量Coは、C(5■qksεoA″NIO
/2(VD+VR) ・・・・・・(1)で与えられる
。The electric capacitance Co due to the depletion layer of the pfn junction when applying the reverse bias VR is C(5■qksεoA″NIO
/2(VD+VR)...Given by (1).
ここでqは電荷量、ksεOはp+n接合を形成してい
る半導体の誘電率、Aは接合の断面積、Nloは空乏層
におけるネットのイオン化された不純物濃度、qVDは
拡散ポテンシャルである。今、この状態の接合に少数キ
ャリヤあるいは多数キャリヤの注入パルスを印加し、そ
の後の時間を秒における電気容量の変化ΔC(を)を求
めると、
Δat:Co((1+ΔNi(tl//Nlo) −1
) ・・・・・・(2)で与えられる。Here, q is the amount of charge, ksεO is the dielectric constant of the semiconductor forming the p+n junction, A is the cross-sectional area of the junction, Nlo is the net ionized impurity concentration in the depletion layer, and qVD is the diffusion potential. Now, if we apply an injection pulse of minority carriers or majority carriers to the junction in this state and then calculate the change in capacitance ΔC() in seconds, we get Δat:Co((1+ΔNi(tl//Nlo) − 1
) ......Given by (2).
ここでΔNi(を)はを秒後におけるNloの変化分で
ある。ΔNi(を)は不純物準位がある場合、ΔNi(
を)■ΣΔNi(O)exp(−−)・・・・・・(3
)lτ・になる。Here, ΔNi() is the change in Nlo after . ΔNi( ) is ΔNi( ) when there is an impurity level.
)■ΣΔNi(O)exp(--)・・・・・・(3
) becomes lτ・.
ここでΔNi(O)はを=0でのΔNi(を)の直であ
りτiはi番目の不純物準位での熱放射割合(電子及び
正孔に関してのこの値は夫々en及びe で定義される
)による時定数で
で与えられる。Here, ΔNi(O) is the direct value of ΔNi(O) with The time constant is given by
若し、(2)式でΔNI(t)《NlOであるならば、
ΔC(t)は(2)式と(3)式を用いて近似的にで与
えられる。If ΔNI(t)〈NlO in equation (2), then
ΔC(t) is approximately given by using equations (2) and (3).
この様に(5)式によれば電気容量の時間変化の時定数
が直接深い不純物準位の熱放射割合の逆数τlであるこ
とが示される。そこで、従来は、まず電気容量の時間変
化ΔC(t)を電圧変化に変換した信号として直接に取
り出し、これを例えば電子計算機に記憶させるとか、あ
る特定の時間tlとT2の値だけ選んでアナログ的に処
理する等の方法を用いて、(5)式に基づいてτiある
いは熱放射割合Ep,enを求めていた。しかし、先に
も述べたように、従来の測定手法を完成している(5)
式は、ΔNI(t)《NlOなる条件が成立する時の近
似式である。In this way, equation (5) shows that the time constant of the capacitance change over time is directly the reciprocal of the heat radiation rate of the deep impurity level τl. Conventionally, therefore, first, the time change ΔC(t) of the capacitance is directly extracted as a signal converted into a voltage change, and this is stored in a computer, for example, or only the values of tl and T2 are selected at a certain time and the analog signal is converted into a voltage change. τi or the heat radiation ratios Ep, en were determined based on equation (5) using a method such as a method such as processing according to the method described above. However, as mentioned earlier, the conventional measurement method has been perfected (5)
The equation is an approximate equation when the condition ΔNI(t)<<NlO holds true.
これに対して、一般には半導体p+n接合がこの条件を
満足しているかどうかは判からない場合が多い。従つて
、上述した従来手法では必ずしも正確な測定、解析結果
が得られているとは限らず、誤認を起こしている場合も
少くない。On the other hand, in general, it is often unclear whether a semiconductor p+n junction satisfies this condition. Therefore, the conventional methods described above do not necessarily provide accurate measurement and analysis results, and often result in misunderstandings.
本発明は以上に鑑てなされたもので、従来のようにΔC
(t)の信号を直接に解析、処理するのを止め、正確な
Pn接合及びシヨツトキ・バリヤにおける理論に基づい
て正確且つ容易に深い不純物準9位の測定をなし得る測
定方法を提供せんとするものである。The present invention has been made in view of the above, and unlike the conventional
We aim to provide a measurement method that can accurately and easily measure the deep impurity quasi-9 position based on accurate Pn junction and Schottky barrier theory without directly analyzing and processing the (t) signal. It is something.
以下、本発明測定方法を、先の従来例の場合と同様にP
fn接合に対して施した実施例に就き、添付図面に即し
て説明する。Hereinafter, the measurement method of the present invention will be explained as follows, as in the case of the conventional example.
An embodiment applied to an fn junction will be described with reference to the accompanying drawings.
本発明では、従来手法におけるような数式的仮定が入ら
ない理論方程式としての(2)式を元に測定、解析をな
す。In the present invention, measurement and analysis are performed based on equation (2), which is a theoretical equation that does not include mathematical assumptions as in conventional methods.
そこで先づ、(2)式左辺のΔC(t)を、逆バイアス
VRを印加したp゛n接合試料1から、光パルス又は電
圧パルス2を印加することにより取出すが、これ自体は
在来の過渡容量計等、当該ΔC(t)又はC(t)を取
り出すことのできる容量計3に依れば良い。しかして、
このようにして取出したΔC(t)も、(2)式のまま
では、非指数関数的なこともあつて解析は困難である。Therefore, first, ΔC(t) on the left side of equation (2) is extracted by applying an optical pulse or voltage pulse 2 from the p-n junction sample 1 to which a reverse bias VR has been applied. It is sufficient to use a capacitance meter 3 such as a transient capacitance meter that can take out the ΔC(t) or C(t). However,
ΔC(t) extracted in this way is also difficult to analyze if the formula (2) is used as it is because it is a non-exponential function.
そこで、本発明では、アナログ関数発生器4を用いて処
理に適当な関数f(ΔC(t))となるようにアナログ
処理をなすことに一つの特徴があり、この実施例の場合
は、(2)式を次の(6)式に変形する。Therefore, one feature of the present invention is that analog processing is performed using the analog function generator 4 to obtain a function f(ΔC(t)) suitable for processing, and in the case of this embodiment, ( Transform the equation 2) into the following equation (6).
この(6)式は、ΔC(t)の代りに(ΔC(t)/C
O)2+2ΔC(t)/COの信号の時間変化がある温
度に於て求まれば、その時定数は正しく深い不純物準位
に基づく熱放射割合の逆数であるrlになることを示し
ている。そしてまた、このアナログ関数発生器4の出力
信号f(ΔC(t))=(ΔC(TVCO)゛+2ΔC
(t)/ COは、既存のミニコンピユータ等の解析装
置5により容易に解析可能である。このように、本発明
に依れば、上記(2)式を基本にしてしかもこれを解析
に都合の良い信号にアナログ処理するため、データ解析
が従来手法に比し非常に正確且つ容易という大きな効果
がある。 ※尚、上述の実施例はp゛n接合に就いての
ものであるが、一般に、Pn接合及びシヨツトキ接合に
おける空乏層の電気容量の評価法は、いろいろな場合の
各々について、正確な理論に基づいて行われており、接
合のでき方により(6)式に対応する方程式はそれぞれ
異なつたものでなる。例えば、p+n接合でn層の不純
物濃度に分布があるとき、逆バイアスVRを印加してい
るときのp+n接合の空乏層による電気容量COは(1
)式にならずになる。この場合は(6)式の代わりにな
る関数がΔNI(t)/NlOをあられすことになる。In this equation (6), instead of ΔC(t), (ΔC(t)/C
It is shown that if the time change of the signal O)2+2ΔC(t)/CO is determined at a certain temperature, the time constant will be rl, which is the reciprocal of the heat radiation rate based on the deep impurity level. And also, the output signal f(ΔC(t)) of this analog function generator 4=(ΔC(TVCO)゛+2ΔC
(t)/CO can be easily analyzed using an existing analysis device 5 such as a minicomputer. As described above, according to the present invention, since the above equation (2) is used as the basis and this is analog-processed into a signal convenient for analysis, data analysis is much more accurate and easier than conventional methods. effective. *Although the above examples relate to pn junctions, in general, evaluation methods for the capacitance of the depletion layer in pn junctions and shottock junctions are based on accurate theory for each of the various cases. The equations corresponding to equation (6) differ depending on the method of joining. For example, when there is a distribution in the impurity concentration of the n layer in a p+n junction, the electric capacitance CO due to the depletion layer of the p+n junction when applying a reverse bias VR is (1
) becomes the formula. In this case, a function that replaces equation (6) would be ΔNI(t)/NlO.
ΔC(t)の信号より(8)式の開数を得るためには、
入力信号が3乗になるアナログ関数発生器と入力信号が
自乗になるアナログ関数発生器の組合せによつて作るこ
とができる。このようにアナログ関数発生器4自体は公
知のものであるので、本発明の思想に則り現実に即した
処理し易い関数f(ΔC(t))を得ることは容易であ
る。In order to obtain the numerical value of equation (8) from the signal of ΔC(t),
It can be created by a combination of an analog function generator whose input signal is cubed and an analog function generator whose input signal is squared. As described above, since the analog function generator 4 itself is well-known, it is easy to obtain a function f(ΔC(t)) that is easy to process and corresponds to reality in accordance with the idea of the present invention.
図面は本発明方法を実施する装置の一例の概略構造図で
あり、図中、1は被測定試料、3は容量計、4はアナロ
グ関数発生器、5は解析装置、である。The drawing is a schematic structural diagram of an example of an apparatus for implementing the method of the present invention, and in the drawing, 1 is a sample to be measured, 3 is a capacitance meter, 4 is an analog function generator, and 5 is an analysis device.
Claims (1)
乏層の電気容量の時間変化から、該半導体中の深い不純
物準位の情報を測定する方法であつて、上記電気容量の
時間変化信号をアナログ関数発生器にてアナログ処理し
、解析に適した関数信号として解析装置に入力すること
を特徴とする、半導体中の深い不純物準位の測定方法。1. A method for measuring information on deep impurity levels in a semiconductor from time-based changes in the capacitance of depletion layers of p-n junctions and Schottky barrier junctions of a semiconductor, in which the time-varying signal of the capacitance is generated using an analog function. A method for measuring deep impurity levels in semiconductors, which is characterized by performing analog processing in a device and inputting it into an analysis device as a function signal suitable for analysis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55101637A JPS5941303B2 (en) | 1980-07-24 | 1980-07-24 | Method for measuring deep impurity levels in semiconductors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55101637A JPS5941303B2 (en) | 1980-07-24 | 1980-07-24 | Method for measuring deep impurity levels in semiconductors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5726451A JPS5726451A (en) | 1982-02-12 |
| JPS5941303B2 true JPS5941303B2 (en) | 1984-10-05 |
Family
ID=14305901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55101637A Expired JPS5941303B2 (en) | 1980-07-24 | 1980-07-24 | Method for measuring deep impurity levels in semiconductors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941303B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59114834A (en) * | 1982-12-21 | 1984-07-03 | Agency Of Ind Science & Technol | Method for measuring deep impurity level or crystal defect level contained in semiconductor device |
| JPS644124A (en) * | 1987-06-26 | 1989-01-09 | Oki Electric Ind Co Ltd | Echo canceller |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5337195B2 (en) * | 1974-10-31 | 1978-10-06 |
-
1980
- 1980-07-24 JP JP55101637A patent/JPS5941303B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5726451A (en) | 1982-02-12 |
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