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JPS5949689B2 - Anodizing method - Google Patents
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JPS5949689B2 - Anodizing method - Google Patents

Anodizing method

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Publication number
JPS5949689B2
JPS5949689B2 JP261877A JP261877A JPS5949689B2 JP S5949689 B2 JPS5949689 B2 JP S5949689B2 JP 261877 A JP261877 A JP 261877A JP 261877 A JP261877 A JP 261877A JP S5949689 B2 JPS5949689 B2 JP S5949689B2
Authority
JP
Japan
Prior art keywords
impurity concentration
thickness
oxide film
epitaxial layer
current source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP261877A
Other languages
Japanese (ja)
Other versions
JPS5387666A (en
Inventor
元基 近藤
公昭 勝川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP261877A priority Critical patent/JPS5949689B2/en
Publication of JPS5387666A publication Critical patent/JPS5387666A/en
Publication of JPS5949689B2 publication Critical patent/JPS5949689B2/en
Expired legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 本発明は半導体ウェーハの陽極酸化方法に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for anodizing semiconductor wafers.

一般に、半絶縁性CaAs結晶基板上に成長せしめた不
純物濃度の高いエピタキシャル層上に形成するショット
キー障壁型電界効果トランジスタ(FET)及び結晶基
板上に低不純物濃度層と該結晶基板より低くかつ該低不
純物濃度層より高い不純物濃度を有する層とをエピタキ
シャル法により順次形成したリード型インパットダイオ
ードの如き半導体素子の製造工程において、該エピタキ
シャル層の高不純物濃度領域の厚さを薄くかつ均一に制
御する場合に陽極酸化法が適用される。
In general, a Schottky barrier field effect transistor (FET) is formed on an epitaxial layer with a high impurity concentration grown on a semi-insulating CaAs crystal substrate, and a low impurity concentration layer is formed on a crystal substrate with a lower impurity concentration than the crystal substrate. In the manufacturing process of semiconductor devices such as lead-type implant diodes in which a layer with a higher impurity concentration than a layer with a lower impurity concentration is sequentially formed by an epitaxial method, the thickness of the high impurity concentration region of the epitaxial layer is controlled to be thin and uniform. In this case, anodizing method is applied.

例えば、半絶縁性GaAs結晶基板上に気相法で形成さ
れるn型エピタキシャル層の厚さはウェーハ内でバラツ
キが大きいために、該n型エピタキシャル層上に形成さ
れるショットキー障壁型FETのピンチオフ電圧のバラ
ツキが大きくなる。また、不純物濃度の極めて高いn゛
゛型GaAs結晶基板上に厚くて不純物濃度の低い層(
n一領域)と薄くて適当な不純物濃度を有するn層をエ
ピタキシャル法で順次形成するリード型インパットダイ
オードの場合には該n層の厚さを薄くかつ均一に制御す
ることが困難であるのでなだれブレイクダウン電圧のバ
ラツキが大きくなる。該ピンチオフ電圧やなだれブレイ
クダウン電圧のバラツキを少なくするためには高不純物
濃度を有するエピタキシャル層の厚さを薄くかつ均一に
する必要がある。従来、不均一な厚さ分布を有するエピ
タキシャル層を均一化する陽極酸化法において、暗状態
及び光照射状態とも同じ陽極酸化用回路が用いられてき
た。しかしながら、例えば可変電流源回路を用いた場合
には、光照射状態で該エピタキシャル層の厚さを均一に
薄くするとき問題があることが判明した。即ち、特に該
エピタキシャル層の不純物濃度が割合低い場合、暗状態
の陽極酸化法により均一化された該エピタキシャル層は
厚くなつている。従つて、光照射状態の陽極酸化法によ
り該エピタキシャル層を相当厚く除去しないとGaAs
・FET等のデバイスに使うことができない。ところで
、該エピタキシャル層を厚く除去したい場合、陽極酸化
時間が極めて長くなり、約数十分ないし1時間位要する
ことがしばしばある。酸化時間が長くなると陽極酸化液
中での酸化膜のエッチング効果が無視できなくなる。特
に、該エッチング効果の程度は暗状態に較べて光照射状
態の場合に顕著である。従つて、可変電流源回路のみを
用いた陽極酸化法では該エピタキシャル層を薄くかつ均
一に匍[する場合、特に、該エピタキシャル層の不純物
濃度が低いとき工数がかかるだけでなく、該エピタキシ
ヤル層の膜厚を正確に制御することが困難であるという
欠点があつた。一方、定電流源回路を用いた場合には、
暗状態での陽極酸化法に問題点があつた。即ち、不均一
な厚さ分布を有する該エピタキシヤル層の厚さを暗状態
の陽極酸化法により均一化する場合、定電流源回路を用
いると、該エピタキシヤル層の薄い部分で電流が流れな
くなるに従い、該エピタキシヤル層の厚い部分に電流が
集中するようになる。よつて、該エピタキシヤル層の厚
い部分では高電流密度となり、該エピタキシヤル領域内
に内含されている結晶欠陥が表面に露出する。また、該
エピタキシヤル層全面がある均一な厚さになつた瞬間に
、酸化膜に高電圧がかかり、該酸化膜の薄い部分が絶縁
破壊してしまう。
For example, since the thickness of an n-type epitaxial layer formed by a vapor phase method on a semi-insulating GaAs crystal substrate varies widely within a wafer, the thickness of a Schottky barrier FET formed on the n-type epitaxial layer is The variation in pinch-off voltage increases. In addition, a thick layer with a low impurity concentration (
In the case of a lead type implant diode in which a thin n-layer with an appropriate impurity concentration is sequentially formed by an epitaxial method, it is difficult to control the thickness of the n-layer to be thin and uniform. The variation in avalanche breakdown voltage increases. In order to reduce variations in the pinch-off voltage and avalanche breakdown voltage, it is necessary to make the thickness of the epitaxial layer having a high impurity concentration thin and uniform. Conventionally, in an anodic oxidation method for making an epitaxial layer having a non-uniform thickness distribution uniform, the same anodic oxidation circuit has been used both in a dark state and in a light irradiation state. However, it has been found that, for example, when a variable current source circuit is used, there is a problem when uniformly reducing the thickness of the epitaxial layer under light irradiation. That is, especially when the impurity concentration of the epitaxial layer is relatively low, the epitaxial layer that has been made uniform by the dark anodic oxidation method is thick. Therefore, unless the epitaxial layer is removed to a considerable thickness by anodic oxidation under light irradiation, the GaAs
-Cannot be used for devices such as FETs. By the way, when it is desired to remove the epitaxial layer thickly, the anodic oxidation time becomes extremely long and often takes about several tens of minutes to an hour. As the oxidation time becomes longer, the etching effect of the oxide film in the anodic oxidation solution cannot be ignored. In particular, the degree of the etching effect is more remarkable in the light irradiation state than in the dark state. Therefore, the anodic oxidation method using only a variable current source circuit not only requires a lot of man-hours when forming the epitaxial layer thinly and uniformly, especially when the impurity concentration of the epitaxial layer is low. The drawback was that it was difficult to accurately control the film thickness. On the other hand, when using a constant current source circuit,
There was a problem with the anodic oxidation method in the dark. That is, when the thickness of the epitaxial layer, which has a non-uniform thickness distribution, is made uniform by dark-state anodic oxidation, if a constant current source circuit is used, current will no longer flow in the thin portion of the epitaxial layer. Accordingly, current is concentrated in the thicker portion of the epitaxial layer. Therefore, the current density is high in the thick portion of the epitaxial layer, and crystal defects contained within the epitaxial region are exposed to the surface. Further, at the moment when the entire surface of the epitaxial layer reaches a certain uniform thickness, a high voltage is applied to the oxide film, causing dielectric breakdown in the thin portion of the oxide film.

そのため、該エピタキシヤル層上に高電圧が直接かかり
、該エピタキシヤル層表面上に結晶欠陥が露出する〇即
ち、定電流源回路を用いた暗状態の陽極酸化方法では該
エピタキシヤル層上に結晶欠陥が露出するという欠点が
あつた。本発明の目的は上記欠点を除去した陽極酸化方
法を提供することにある。
Therefore, a high voltage is directly applied on the epitaxial layer, exposing crystal defects on the surface of the epitaxial layer. In other words, in the dark state anodization method using a constant current source circuit, crystal defects are not formed on the epitaxial layer. The drawback was that the defects were exposed. An object of the present invention is to provide an anodizing method that eliminates the above-mentioned drawbacks.

本発明は、半絶縁性半導体結晶基板上に成長した高不純
物濃度領域、または極めて高い不純物濃度を有する半導
体結晶基板上に低不純物濃度領域及び高不純物濃度領域
が順次形成されている半導体ウエーハの高不純物濃度領
域の厚さを陽極酸化法を用いて薄くかつ均一に制御する
方法において、暗状態で可変電流源回路を用いて該高不
純物濃度領域の表面を陽極酸化し、生成した酸化膜を除
去して該高不純物濃度領域の厚さを均一化した後、光照
射状態で定電流源回路を用いて該高不純物濃度領域の表
面を陽極酸化し、生成した酸化膜を除去して該高濃度不
純物領域の厚さを一様に薄くすることを特徴とする。
The present invention provides high impurity concentration regions grown on a semi-insulating semiconductor crystal substrate, or semiconductor wafers in which a low impurity concentration region and a high impurity concentration region are sequentially formed on a semiconductor crystal substrate having an extremely high impurity concentration. In a method of controlling the thickness of an impurity concentration region to be thin and uniform using an anodizing method, the surface of the high impurity concentration region is anodized using a variable current source circuit in a dark state, and the generated oxide film is removed. After uniformizing the thickness of the high impurity concentration region, the surface of the high impurity concentration region is anodized using a constant current source circuit under light irradiation, and the generated oxide film is removed. It is characterized by uniformly reducing the thickness of the impurity region.

本発明によれば、以下に記載する4つの効果が得られる
According to the present invention, the following four effects can be obtained.

第1に、光照射状態での陽極酸化方法において定電流源
回路を用いるので、酸化膜厚の増大と共に酸化膜の成長
速度がほとんど変化しない0従つて、可変電流源回路を
用いた場合に比して陽極酸化工程に要する時間が大幅に
短縮される。第2に、光照射状態におけるエピタキシヤ
ル層の均一酸化の場合、定電流源回路を用いることによ
り酸化膜厚が増大しても電流密度が変化しない。電流密
度による酸化膜の組成変化が生じないので酸化膜の比抵
抗値は変化しない。従つて、酸化膜中での単位長さ当り
の電圧降下が一定であるので逆に電圧降下から酸化膜厚
が正確に求められ、エピタキシヤル層の膜厚制御が各易
になる。第3に光照射状態での定電流源回路使用により
陽極酸化時間が大幅に短縮されるので、陽極酸化液によ
る酸化膜のエツチング効果がほとんど無視できる。よつ
て、該エピタキシヤルウエーハのエピタキシヤル層の厚
さを精密制御することが可能である。第4に、暗状態及
び光照射状態共定電流源回路を用いた陽極酸化法に比較
して、暗状態で可変電流源回路を用いることにより該エ
ピタキシヤルウエーハ表面上の結晶欠陥露出を防止する
ことができる。本発明を実施例により説明する。
First, since a constant current source circuit is used in the anodization method under light irradiation, the growth rate of the oxide film hardly changes as the oxide film thickness increases. As a result, the time required for the anodic oxidation process is significantly reduced. Second, in the case of uniform oxidation of the epitaxial layer under light irradiation, the current density does not change even if the oxide film thickness increases by using a constant current source circuit. Since the composition of the oxide film does not change due to current density, the specific resistance value of the oxide film does not change. Therefore, since the voltage drop per unit length in the oxide film is constant, the thickness of the oxide film can be accurately determined from the voltage drop, making it easier to control the thickness of the epitaxial layer. Thirdly, since the anodic oxidation time is greatly shortened by using a constant current source circuit under light irradiation, the etching effect of the oxide film caused by the anodic oxidizing solution can be almost ignored. Therefore, it is possible to precisely control the thickness of the epitaxial layer of the epitaxial wafer. Fourth, compared to the anodization method that uses a constant current source circuit in the dark state and in the light irradiation state, exposure of crystal defects on the surface of the epitaxial wafer is prevented by using a variable current source circuit in the dark state. be able to. The present invention will be explained by examples.

半絶縁性のGaAs基板上に不純物濃度2X1〔17C
r1L−3で厚さ約0.29〜0.37μMO)n型G
aAs層をエピタキシヤル法で成長させたGaAsエピ
タキシヤルウエーハを用意する。
Impurity concentration 2X1 [17C
r1L-3, thickness approximately 0.29-0.37μMO) n-type G
A GaAs epitaxial wafer with an aAs layer grown by an epitaxial method is prepared.

このウエーハ表面を洗浄して清浄にした後、陽極酸化装
置にセツトする。第1図は半導体ウエーハを暗状態で陽
極酸化する方法を説明する図である。
After the wafer surface is cleaned and cleaned, it is set in an anodizing apparatus. FIG. 1 is a diagram illustrating a method of anodizing a semiconductor wafer in a dark state.

1は定電圧源であつて、陽極酸化するときに印加される
電圧は可変抵抗2により調整される。
1 is a constant voltage source, and the voltage applied during anodization is adjusted by a variable resistor 2.

陽極酸化が始まるときの印加電圧は120Vである。暗
箱3内に設置された容器4内には陽極酸化液5(水と酒
石酸とエチレングリコールの混合液)が満たされており
、その中にPt電極6とGaAsエピタキシヤルウエー
ハ7がセツトされている。GaAsエピタキシヤルウエ
ーハに酸化物が形成され始めると該酸化膜中の電圧降下
が増大し始め、該電圧降下量が電圧計8で測定される。
該電圧降下が約70Vになると電流計9で測定される電
流値が激減する。そのとき、暗状態の陽極酸化工程を停
止させる。溶器4から取出したGaAsエピタキシヤル
ウエーハ7には厚さ約0.03〜0.15μmの不均一
な酸化膜(酸化膜中へ消費されたGaAsの膜厚;0.
02〜0.1μm)が形成されている。第2図は暗状態
で陽極酸化されたGaAsエピタキシヤルウエーハの断
面図である。
The applied voltage when anodic oxidation begins is 120V. A container 4 placed in a dark box 3 is filled with an anodizing solution 5 (a mixture of water, tartaric acid, and ethylene glycol), and a Pt electrode 6 and a GaAs epitaxial wafer 7 are set therein. . When an oxide begins to form on the GaAs epitaxial wafer, the voltage drop in the oxide film begins to increase, and the amount of voltage drop is measured by a voltmeter 8.
When the voltage drop reaches approximately 70V, the current value measured by the ammeter 9 sharply decreases. At that time, the dark anodic oxidation process is stopped. The GaAs epitaxial wafer 7 taken out from the melter 4 has a non-uniform oxide film with a thickness of approximately 0.03 to 0.15 μm (film thickness of GaAs consumed in the oxide film; 0.03 μm to 0.15 μm).
02 to 0.1 μm) is formed. FIG. 2 is a cross-sectional view of a GaAs epitaxial wafer anodized in the dark.

酸化膜12を濃塩酸で除去した後、GaAsエピタキシ
ヤルウエーハの水洗を数回繰り返す。こうして、該エピ
タキシヤル層11の厚さは約0.27μmに均一化され
る。次に、該GaAsエピタキシヤルウエーハを光照射
状態で再び陽極酸化する゜第3図は半導体ウエーハを光
照射状態で陽極酸化する方法を説明する図である。
After removing the oxide film 12 with concentrated hydrochloric acid, the GaAs epitaxial wafer is washed with water several times. In this way, the thickness of the epitaxial layer 11 is made uniform to about 0.27 μm. Next, the GaAs epitaxial wafer is anodized again under light irradiation. FIG. 3 is a diagram illustrating a method of anodizing a semiconductor wafer under light irradiation.

GaAsエピタキシヤルウエーハ7を陽極酸化液5中に
セツトし、スポツトライト13を用いてウエーハ7の表
面に光を一様に照射しながら定電流源1を用いて2mA
/Cdの電流密度で陽極酸化を行なう。
A GaAs epitaxial wafer 7 is set in an anodic oxidation solution 5, and a spotlight 13 is used to uniformly irradiate the surface of the wafer 7 with light at 2 mA using a constant current source 1.
Anodic oxidation is performed at a current density of /Cd.

電圧降下が60Vになつたところで、陽極酸化を停止さ
せる。該陽極酸化によりGaAsエピタキシヤルウエー
ハ上には、約900Aの酸化膜が形成される。第4図は
光照射状態で陽極酸化された GaAsエピタキシヤル
ウエーハの断面図である。
When the voltage drop reaches 60V, the anodic oxidation is stopped. By this anodic oxidation, an oxide film of about 900 A is formed on the GaAs epitaxial wafer. FIG. 4 is a cross-sectional view of a GaAs epitaxial wafer anodized under light irradiation.

酸化膜14を濃塩酸で除去すると半絶縁性基板10上に
厚さ約0.18μmを有する均一なエピタキシヤル層1
1が形成される。以上詳細に説明したように、本発明に
よれば半導体基板の不純物濃度に比較して高い不純物濃
度を有するエピタキシヤル層の厚さを薄くかつ均一に制
御でき、シヨツトキー障壁型電界効果トランジスタ、あ
るいはリード型インパツトダイオードのような半導体素
子の製造に効果が大きい。
When the oxide film 14 is removed with concentrated hydrochloric acid, a uniform epitaxial layer 1 having a thickness of about 0.18 μm is formed on the semi-insulating substrate 10.
1 is formed. As described in detail above, according to the present invention, the thickness of the epitaxial layer having an impurity concentration higher than that of the semiconductor substrate can be controlled to be thin and uniform, and it is possible to control the thickness of the epitaxial layer to be thin and uniform. It is highly effective in manufacturing semiconductor devices such as type impact diodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体ウエーハを暗状態で陽極酸化する方法を
説明する図、第2図は暗状態で陽極酸化されたGaAs
ェピタキシヤルウエーハの断面図、第3図は半導体ウエ
ーハを光照射状態で陽極酸化する方法を説明する図、第
4図は光照射状態で陽極酸化された GaAsエピタキ
シヤルウエーハの断面図である。 1 ・・・・・・定電圧源、2・・・・・・可変抵抗、
3・・・・・・暗箱、4・・・・・・容器、5・・・・
・・陽極酸化液、6・・・・・・白金電極、7・・・・
・・ GaAsエピタキシヤルウエーハ、8・・・・・
・電圧計. 9・・・・・・電流計、10・・・・・・
GaAs基板、11・・・・・・エピタキシヤル層.
12,14・・・・・・酸化膜、13・・・・・・スポ
ツトライト。
Figure 1 is a diagram explaining the method of anodizing a semiconductor wafer in the dark, and Figure 2 shows GaAs anodized in the dark.
FIG. 3 is a cross-sectional view of an epitaxial wafer. FIG. 3 is a diagram explaining a method of anodizing a semiconductor wafer under light irradiation. FIG. 4 is a cross-sectional view of a GaAs epitaxial wafer anodized under light irradiation. . 1... Constant voltage source, 2... Variable resistance,
3...Dark box, 4...Container, 5...
...Anodic oxidation solution, 6...Platinum electrode, 7...
・・GaAs epitaxial wafer, 8・・・・
·voltmeter. 9... Ammeter, 10...
GaAs substrate, 11...Epitaxial layer.
12, 14...Oxide film, 13...Spotlight.

Claims (1)

【特許請求の範囲】[Claims] 1 低不純物濃度半導体領域上に形成した高不純物濃度
領域の厚さを陽極酸化法を用いて均一に制御する方法に
おいて、暗状態で前記高不純物濃度領域の表面を可変電
流源回路を用いて陽極酸化して生成した酸化膜を除去す
る工程と、光照射状態で前記高不純物濃度領域の表面を
定電流源回路を用いて陽極酸化して生成した酸化膜を除
去する工程とを併用したことを特徴とする陽極酸化方法
1 In a method for uniformly controlling the thickness of a high impurity concentration region formed on a low impurity concentration semiconductor region using an anodizing method, the surface of the high impurity concentration region is anodized using a variable current source circuit in a dark state. The process of removing the oxide film produced by oxidation and the process of removing the oxide film produced by anodic oxidizing the surface of the high impurity concentration region under light irradiation using a constant current source circuit are combined. Characteristic anodic oxidation method.
JP261877A 1977-01-12 1977-01-12 Anodizing method Expired JPS5949689B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP261877A JPS5949689B2 (en) 1977-01-12 1977-01-12 Anodizing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP261877A JPS5949689B2 (en) 1977-01-12 1977-01-12 Anodizing method

Publications (2)

Publication Number Publication Date
JPS5387666A JPS5387666A (en) 1978-08-02
JPS5949689B2 true JPS5949689B2 (en) 1984-12-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP261877A Expired JPS5949689B2 (en) 1977-01-12 1977-01-12 Anodizing method

Country Status (1)

Country Link
JP (1) JPS5949689B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125735U (en) * 1989-03-20 1990-10-17

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5595329A (en) * 1979-01-12 1980-07-19 Matsushita Electric Ind Co Ltd Preparation of semiconductor device
JPH0616507B2 (en) * 1984-08-06 1994-03-02 日本電気株式会社 Anodizing method and apparatus therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125735U (en) * 1989-03-20 1990-10-17

Also Published As

Publication number Publication date
JPS5387666A (en) 1978-08-02

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