Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS5914905B2 - Manufacturing method of semiconductor device - Google Patents
[go: Go Back, main page]

JPS5914905B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5914905B2
JPS5914905B2 JP54032747A JP3274779A JPS5914905B2 JP S5914905 B2 JPS5914905 B2 JP S5914905B2 JP 54032747 A JP54032747 A JP 54032747A JP 3274779 A JP3274779 A JP 3274779A JP S5914905 B2 JPS5914905 B2 JP S5914905B2
Authority
JP
Japan
Prior art keywords
voltage
layer
gallium arsenide
thickness
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54032747A
Other languages
Japanese (ja)
Other versions
JPS55124267A (en
Inventor
彰夫 嶋野
弘光 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54032747A priority Critical patent/JPS5914905B2/en
Priority to US06/047,931 priority patent/US4247373A/en
Priority to GB7921141A priority patent/GB2028370B/en
Priority to DE2924702A priority patent/DE2924702C2/en
Priority to CA330,051A priority patent/CA1129120A/en
Priority to FR7915720A priority patent/FR2429492A1/en
Publication of JPS55124267A publication Critical patent/JPS55124267A/en
Publication of JPS5914905B2 publication Critical patent/JPS5914905B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/061Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/80FETs having rectifying junction gate electrodes

Landscapes

  • Formation Of Insulating Films (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、とりわけショッ
トキーゲート電界効果トランジスタ(以下MESFET
と称す)のピンチ・オフ電圧値を半導体基板の初期厚み
と不純物濃度を知ることなく自動的に決定することを目
的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a Schottky gate field effect transistor (hereinafter referred to as MESFET).
The purpose of this invention is to automatically determine the pinch-off voltage value of the semiconductor substrate without knowing the initial thickness and impurity concentration of the semiconductor substrate.

従来、砒化ガリウム等からなる化合物半導体装置にあつ
ては、半導体基板としての半絶縁性砒化ガリウム基板土
に半導体層としてのn形活性層をエピタキシャル成長さ
せる場合にはその厚さ制御が非常に重要であり、例えば
砒化ガリウム基板を用いるMESFETにおいては、所
定のピンチ・; オフ電圧を得るためにn形活性層の厚
みは、0.25μmの厚さに対して±0.02μm程度
の精度内に抑える必要がある。
Conventionally, in the case of compound semiconductor devices made of gallium arsenide or the like, thickness control is extremely important when epitaxially growing an n-type active layer as a semiconductor layer on a semi-insulating gallium arsenide substrate as a semiconductor substrate. For example, in a MESFET using a gallium arsenide substrate, in order to obtain a predetermined pinch off voltage, the thickness of the n-type active layer is kept within an accuracy of about ±0.02 μm for a thickness of 0.25 μm. There is a need.

このような精密な厚みの制御は、従来良く用いられてい
るエピタキシャル成長技術はもとより、化学エッチング
技術を駆使して−0も不可能に近い。これを解決する一
つの方法として、電解液中における陽極酸化法が開発さ
れている。
Such precise thickness control is nearly impossible, even by making full use of chemical etching techniques, as well as epitaxial growth techniques that are commonly used in the past. As one method to solve this problem, an anodic oxidation method in an electrolyte has been developed.

これは電流あるいは電圧の制御によつて比比較的厚さ精
度の良い酸化膜を成長し、その後この酸化膜を除去し1
5て活性層厚みを制御しようとする方法である。し力化
ながら、この方法でも最初に形成する活性層の厚みをす
べての領域にわたつて均一に精度よく形成しておかねば
ならず、またこのようなすへての領域にわたつて均一な
膜厚を形成するのは■0 容易ではない。本発明はこの
ような問題を解決するものであつて、本出願人が特願昭
53−75104号で概に提案している光照射陽極酸化
の原理を用いて、活性層の初期厚みと濃度に関係なく残
存活性層上にク5 形成されるMESFETのピンチ・
オフ電圧を所定の値に制御しようとするものである。
This involves growing an oxide film with relatively high thickness accuracy by controlling current or voltage, and then removing this oxide film.
This method attempts to control the thickness of the active layer. However, even with this method, the thickness of the active layer that is initially formed must be formed uniformly and precisely over all regions, and it is necessary to form the active layer with uniform thickness over all such regions. It is not easy to form ■0. The present invention solves these problems, and uses the principle of light irradiation anodic oxidation that the present applicant generally proposed in Japanese Patent Application No. 75104/1983 to determine the initial thickness and concentration of the active layer. Pinch of the MESFET formed on the remaining active layer regardless of the
The purpose is to control the off-voltage to a predetermined value.

以下に本発明の詳細について実施例をもとに図面を用い
て述べる。
The details of the present invention will be described below based on embodiments and with reference to the drawings.

半絶縁性砒化ガリウム基板上に形成されたn形30砒化
ガリウム層を陽極酸化すれば、酸化膜とn形砒化ガリウ
ムとの接合により空乏層がn形砒化ガリウム層に形成さ
れる。
When an n-type 30 gallium arsenide layer formed on a semi-insulating gallium arsenide substrate is anodized, a depletion layer is formed in the n-type gallium arsenide layer by the junction between the oxide film and the n-type gallium arsenide.

この空乏層の両端に生ずる電圧VDは照射光量と酸化電
流に依存する。今一定電流、一定光量の光照射の下で陽
極酸化すれ35ば上記空乏層の端が半絶縁性砒化ガリウ
ム基板に達するまで酸化が進行し、その後電流が流れな
くなつて自動的に酸化が停止する。すなわち、残存11
クーする砒化ガリウム層の厚さは空乏層の厚さに等しく
なる。
The voltage VD generated across this depletion layer depends on the amount of irradiation light and the oxidation current. Now, if anodic oxidation is performed under light irradiation with a constant current and a constant amount of light, the oxidation will proceed until the edge of the depletion layer reaches the semi-insulating gallium arsenide substrate, and then the current will stop flowing and the oxidation will automatically stop. do. That is, remaining 11
The thickness of the gallium arsenide layer to be cooled is equal to the thickness of the depletion layer.

従つて、この時残存n形砒化ガリウム層の厚さはVDに
対応した厚さとなる。その後、この酸化膜を除去してシ
ヨツトキ一接合を形成すると、この場合のピツチオフ電
圧V,は次式で与えられる。p=VD−Vbi 但し、Vbiは形成したシヨツトキ一接合の接触電位に
より定まる定数である。
Therefore, at this time, the thickness of the remaining n-type gallium arsenide layer corresponds to VD. Thereafter, when this oxide film is removed to form a shot-off junction, the pitch-off voltage V in this case is given by the following equation. p=VD-Vbi However, Vbi is a constant determined by the contact potential of the formed shot key junction.

従つて、VDを制御することによつて、MESFETの
ピンチ・オフ電圧V,を制御することができる。
Therefore, by controlling VD, the pinch-off voltage V, of the MESFET can be controlled.

ところで、このVDは酸化電流密度と照射光量によつて
任意に変化させることができる。今、―定電流密度(j
=1mA/Cd)における照射光量φとVDの関係を第
1図に示す。
By the way, this VD can be arbitrarily changed depending on the oxidation current density and the amount of irradiation light. Now, - constant current density (j
FIG. 1 shows the relationship between the irradiation light amount φ and VD at 1 mA/Cd).

同図よりφ。以上の光量の光る照射すればVD=0とな
ることがわかる。しかしながら、空乏層の厚さはn形砒
化ガリウム層のキヤリア濃度によつて影響されるので、
これによつてVDも影響を受けることになる。ところで
、陽極酸化電圧Vcは任意の時間tにおいて、Vc(t
)::VD+d−T dは酸化電流密度により定まる定数 なる関係を有するので、照射光量をφ。
From the same figure, φ. It can be seen that if the above amount of light is irradiated, VD=0. However, since the thickness of the depletion layer is influenced by the carrier concentration of the n-type gallium arsenide layer,
This will also affect VD. By the way, the anodic oxidation voltage Vc is Vc(t
)::VD+d-T Since d has a constant relationship determined by the oxidation current density, the amount of irradiation light is φ.

以上にした時の酸化電圧と、照射光量をそれ以下にした
時の酸化電圧との差から、n形砒化ガリウム層の濃度に
関係なくVDを容易に知ることができる。この状態を第
2図に示す。この様に、陽極酸化中にVDが所定の値、
VDl、すなわちVpが所定の値になるような光量φ1
の光を照射して陽極酸化を行℃・、酸化が停止した後に
酸化膜を除去して、このn形活性層を用いてMESFE
Tを製作すると、初期の活性層厚さ及び濃度に関係なく
、一定のピンチ・オフ電圧を有するMESFETを得る
ことができる。
From the difference between the oxidation voltage when the irradiation voltage is set above and the oxidation voltage when the irradiation light amount is lower than that, VD can be easily determined regardless of the concentration of the n-type gallium arsenide layer. This state is shown in FIG. In this way, when VD is at a predetermined value during anodization,
Light amount φ1 such that VDl, that is, Vp becomes a predetermined value
After the oxidation has stopped, the oxide film is removed, and this n-type active layer is used to form a MESFE.
By fabricating T, a MESFET with a constant pinch-off voltage can be obtained regardless of the initial active layer thickness and concentration.

以下に本発明の具体的な実施例について述べる。Specific examples of the present invention will be described below.

第3図に示されるようにn形エピタキシヤル層を有する
砒化ガリウム基板31の〒端にオーミツク電極32を形
成し定電流電源35の正極に接続する。ただしオーミツ
ク電極32は電解液34と電気的に絶縁しておく。一方
陰極として白金板33を用い両者の間に電流密度にして
1mA/dの電流を通じて陽極酸化を行なう。本実施例
で用いた電解液の組成は、酒石酸3f、水100d、プ
ロピレングリコール200r1及び水素イオン濃度制御
(PH6.O)用アンモニア水の混合溶液である。まず
砒化ガリウム基板31に10000tX以上の強力な光
37を照射して陽極酸化を行なう。
As shown in FIG. 3, an ohmic electrode 32 is formed at the end of a gallium arsenide substrate 31 having an n-type epitaxial layer and connected to the positive electrode of a constant current power source 35. As shown in FIG. However, the ohmic electrode 32 is electrically insulated from the electrolyte 34. On the other hand, a platinum plate 33 is used as a cathode, and a current with a current density of 1 mA/d is passed between the two to perform anodic oxidation. The composition of the electrolytic solution used in this example was a mixed solution of 3 f tartaric acid, 100 d water, 200 r1 propylene glycol, and aqueous ammonia for hydrogen ion concentration control (PH 6.0). First, the gallium arsenide substrate 31 is irradiated with strong light 37 of 10,000 tX or more to perform anodic oxidation.

この時チヤートレコーダ36に記録される陽極酸化電圧
Vcは第4図のAに示すように時間に対して直線的に増
加する。次に混射光37の光量を減少させ、陽極酸化電
圧Vcが第4図のAに示す直線から所望のピンチオフ電
圧分だけ増加した直線Bとなるように光量を調節しそこ
で固定して陽極酸化を行なう。
At this time, the anodic oxidation voltage Vc recorded on the chart recorder 36 increases linearly with time as shown at A in FIG. Next, the light intensity of the mixed light 37 is reduced, and the light intensity is adjusted so that the anodic oxidation voltage Vc becomes a straight line B, which is increased by the desired pinch-off voltage from the straight line A shown in FIG. Let's do it.

チヤートレコーダ36上で陽極酸化電圧Vcの急激な土
昇を検出して酸化を停止し酸化膜を希塩酸で除去すれば
、所望のピンチオフ電圧を有するMESFETを製造可
能な、砒化ガリウムエピタキシヤル層を得ることができ
る。
By detecting a sudden rise in the anodic oxidation voltage Vc on the chart recorder 36, stopping the oxidation, and removing the oxide film with dilute hydrochloric acid, a gallium arsenide epitaxial layer capable of manufacturing a MESFET having a desired pinch-off voltage is obtained. be able to.

第5図は陽極酸化時の設定値VDとCr/Pt/Auを
ゲートとして製作したMESFETのピンチオフ電圧の
関係を示すものであつて、この関係に基いて、第4図の
直線AからBへの陽極酸化電圧Vcの変化Dを制御すえ
ば、所望のピンチオフ電圧Vpが得られる。以上に述べ
たように、本発明は半導体基板上に形成された半導体層
を一定の直流電流と光照射によつて陽極酸化する際に、
酸化電圧の変化から、後に形成する電界効果トランジス
タのピンチ・オフ電圧を知ることができ、且つ極めてそ
の値が均一な電界効果トランジスタを得ることができる
Figure 5 shows the relationship between the set value VD during anodic oxidation and the pinch-off voltage of a MESFET manufactured using Cr/Pt/Au as a gate. Based on this relationship, the line A to B in Figure 4 is By controlling the change D in the anodic oxidation voltage Vc, a desired pinch-off voltage Vp can be obtained. As described above, the present invention is capable of anodizing a semiconductor layer formed on a semiconductor substrate using a constant DC current and light irradiation.
The pinch-off voltage of a field effect transistor to be formed later can be determined from the change in oxidation voltage, and a field effect transistor whose value is extremely uniform can be obtained.

したがつて本発明は、性能の均一化、歩留の向上など工
業的価値は極めて大きい。
Therefore, the present invention has extremely great industrial value, such as uniformity of performance and improvement of yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は照射光量と空乏層電圧の関係を示す図、第2図
は陽極酸化電圧の酸化時間変化を示す図、第3図は本発
明の一実施例を説明するための図、第4図はチヤートレ
コーダ上に記録される陽極酸化電圧の変化を示す図、第
5図は本発明による空乏層電圧の設定値と製造された砒
化ガリウムシヨツトキゲート電界効果トランジスタのピ
ンチオフ電圧の測定値との相関を示す図である。 31・・・・・・エピタキシヤル層を有する砒化ガリウ
ム基板、32・・・・・・オーミツクコンタクト、33
・・・・・伯金陰極、34・・・・・・電解液、35・
・・・・・定電流電源、36・・・・チャートレコーダ
、37・・・タングステンランプによる白色光。
FIG. 1 is a diagram showing the relationship between irradiation light amount and depletion layer voltage, FIG. 2 is a diagram showing changes in anodic oxidation voltage over oxidation time, FIG. 3 is a diagram for explaining one embodiment of the present invention, and FIG. The figure shows the change in anodization voltage recorded on the chart recorder, and Figure 5 shows the set value of the depletion layer voltage according to the present invention and the measured value of the pinch-off voltage of the manufactured gallium arsenide shot gate field effect transistor. FIG. 31... Gallium arsenide substrate having an epitaxial layer, 32... Ohmic contact, 33
...Bakukin cathode, 34... Electrolyte, 35.
... Constant current power supply, 36 ... Chart recorder, 37 ... White light from tungsten lamp.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板上に形成された半導体層に、電解液中で
所定の電流を通ずるとともに光照射を行なうことにより
前記半導体層を酸化し、所望の厚さの前記半導体層を残
存させる半導体装置の製造方法であつて、前記光照射の
光量を前記半導体層に空乏層が形成されない量から、前
記半導体層に所定の空乏層が形成される量に変化させた
ときの陽極酸化電圧の増加分からピンチオフ電圧を決定
することを特徴とする半導体装置の製造方法。
1 Manufacturing a semiconductor device in which the semiconductor layer formed on a semiconductor substrate is oxidized by passing a predetermined current in an electrolytic solution and irradiating the semiconductor layer with light to leave the semiconductor layer with a desired thickness. In the method, the pinch-off voltage is determined by an increase in anodizing voltage when the amount of light irradiation is changed from an amount that does not form a depletion layer in the semiconductor layer to an amount that forms a predetermined depletion layer in the semiconductor layer. 1. A method for manufacturing a semiconductor device, the method comprising: determining .
JP54032747A 1978-06-20 1979-03-20 Manufacturing method of semiconductor device Expired JPS5914905B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP54032747A JPS5914905B2 (en) 1979-03-20 1979-03-20 Manufacturing method of semiconductor device
US06/047,931 US4247373A (en) 1978-06-20 1979-06-12 Method of making semiconductor device
GB7921141A GB2028370B (en) 1978-06-20 1979-06-18 Method of making simeconductor device and apparatus therefor
DE2924702A DE2924702C2 (en) 1978-06-20 1979-06-19 Method and apparatus for manufacturing semiconductor devices
CA330,051A CA1129120A (en) 1978-06-20 1979-06-19 Method of making semiconductor device and apparatus therefor
FR7915720A FR2429492A1 (en) 1978-06-20 1979-06-19 METHOD AND DEVICE FOR MANUFACTURING SEMICONDUCTORS BY ANODIC OXIDATION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54032747A JPS5914905B2 (en) 1979-03-20 1979-03-20 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS55124267A JPS55124267A (en) 1980-09-25
JPS5914905B2 true JPS5914905B2 (en) 1984-04-06

Family

ID=12367434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54032747A Expired JPS5914905B2 (en) 1978-06-20 1979-03-20 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5914905B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5789261A (en) * 1980-11-25 1982-06-03 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS55124267A (en) 1980-09-25

Similar Documents

Publication Publication Date Title
US4092445A (en) Process for forming porous semiconductor region using electrolyte without electrical source
US3798139A (en) Electrolytic oxidation of gallium containing compound semiconductors
JPS6348196B2 (en)
US4503600A (en) Process for manufacturing a buried gate field effect transistor
US3959098A (en) Electrolytic etching of III - V compound semiconductors
JPS5914905B2 (en) Manufacturing method of semiconductor device
Hoffmann et al. Voltage‐controlled photoetching of GaAs
GB2028370A (en) Method of making simeconductor device and apparatus therefor
US4157610A (en) Method of manufacturing a field effect transistor
JPH09306889A (en) Method for manufacturing semiconductor device
US3518511A (en) Semiconductor device having at least one contact applied to a semiconductor material of the type ii-b-vi-a and method of manufacturing such device
JPS57193069A (en) Semiconductor device
US4241167A (en) Electrolytic blocking contact to InP
JPS5949689B2 (en) Anodizing method
JPS5949690B2 (en) Anodizing method
JPH06140433A (en) Manufacture of semiconductor device
JPH06120256A (en) Method for manufacturing semiconductor device
JPH04219936A (en) Manufacture of semiconductor device
JPH0414227A (en) Manufacture of semiconductor device
JPS6113630A (en) Manufacture of semiconductor device
Takagi et al. A new technique for growth of thermal oxide films on GaAs
JPS59227129A (en) Manufacture of semiconductor device
JPH03147336A (en) Manufacture of semiconductor device
JP2869112B2 (en) Method for manufacturing semiconductor device
JPS58105545A (en) Manufacture of semiconductor device