JPS5951749B2 - Substrate bias generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate bias generation circuit for applying a bias voltage to a silicon substrate in a MOS type IC.

In a MOS type IC, a substrate bias voltage is applied between a silicon substrate and a ground potential.

Conventionally, such a substrate bias voltage has often been applied externally.

However, providing a bias generation circuit for this purpose is complicated and undesirable from a cost standpoint, so I
A bias generation circuit is provided in the C chip to internally supply a substrate bias voltage. FIG. 1 is a circuit diagram showing the configuration of a conventional substrate bias generation circuit. In the figure, 1 is an oscillator, Q,,Q. ,Q. , Q is a transistor, D is a diode, Cl is a coupling capacitor, Co is a bypass capacitor, and Ni, No.
represents a node. In FIG. 1, the signal of oscillator 1 is transmitted through transistors Q,,Q.

An output is generated at the node N2, and is applied to the node No via the coupling capacitor Cl. n-channel MO
In the case of S, the substrate is p-type silicon, and it is necessary to apply a negative substrate bias voltage to it. Now, when the potential of the node No rises, the transistor Q becomes conductive and sets the node N2 to the ground potential. Next, when the potential of the node N2 drops, No becomes a negative potential and the transistor Q3 is not conductive, so that a negative voltage is generated at the output terminal T through the diode D or the transistor Q. In this way, a positive supply voltage V. . A negative substrate bias voltage VBB can be generated by the output of node N2 that swings between the ground potential and the ground potential. In the circuit shown in FIG. 1, the node No becomes functional only when the potential becomes more negative than that of the substrate and the diode D or transistor Q4 is turned on.

Therefore, due to the forward characteristics of the diode D, the diffusion layer n
Electrons are injected from the p-layer into the substrate p-layer, which adversely affects information in peripheral circuits, memory cells, and the like. Therefore, a transistor Q4 is provided in parallel with the diode D1 to connect the node N
The potential difference between the potential No. 2 and BB is made small. However, the substrate bias generation circuit as shown in FIG. 1 uses the power supply voltage V.

The substrate bias voltage VBB changes depending on the increase or decrease in O and the substrate bias current 1BB. The level at node N2 is power supply voltage V. This is because the internal resistance of the substrate bias generation circuit is not zero. The present invention is intended to eliminate these drawbacks of the prior art, and its purpose is to provide a substrate bias system in which the substrate bias voltage changes little even when the power supply voltage fluctuates or the substrate bias current fluctuates. The purpose of this invention is to provide a generating circuit.

However, in order to prevent the substrate bias voltage from changing, the first
In the figure, the negative voltage value generated when the node N2 is driven by the oscillator 1 via the coupling capacitor C1 should not change even if the power supply voltage or substrate bias current changes. Therefore, in the substrate bias generation circuit of the present invention, a circuit is driven by an oscillator signal and supplies an output to a node via a capacitor, and one end is connected to the node and conducts when the output of the circuit is at a low level. and a first transistor connected in parallel to this to generate a negative voltage. The first transistor is connected between the node and ground and is driven by an external signal that is in phase with the output of the circuit, so that the signal goes high level. a second transistor consisting of one or more transistors, which conducts when the transistor is turned on and clamps the node to ground potential; one end of the transistor is connected to the node; the second transistor is driven by an external signal having a phase opposite to the signal of the circuit; A third transistor is connected between the power supply and the other end of the third transistor and conducts when the signal is at a high level and shuts off when the signal is at a low level. and a fourth transistor comprising one or more transistors that clamps the node to a negative voltage equal to its threshold voltage through the third transistor when in the cut-off state. . Examples will be described in detail below.

FIG. 2 is a circuit diagram showing the configuration of an embodiment of the substrate bias generation circuit of the present invention.

In the same figure, the symbols 1, Q1, Q2, Q3, Q4, D1,
The locations of C1, C2, N1, and N2 are the same as in the case of FIG. Qll9Ql2raQl39Ql49Q
l5 is a transistor, and N3gN4 and N5 are nodes. Further, FIG. 3 is a time chart showing operating waveforms of each part in the circuit of FIG. 2.

In the figure, (a) shows timing signals VA and V. , (b) shows the timing signal VB, (c) shows the potential of the node N1, and (d) shows the potential of the node N2. In FIG. 2, timing signals VA, VB
, VO have a timing relationship as shown in FIG. 3, and are applied to the gates of transistors Qll, Ql3, and Ql5, respectively. Initially, when the signals VA and VO are at high level and the signal VB is at low level, transistor Ql3
is in a cut-off state and transistors Ql4 and Ql5 are in a conductive state, so that node N2 is at ground potential. At this time, since the signal of the oscillator 1 generated at the node N1 is at a high level, the high level of the signal generated at N2 via the coupling capacitor C1 is clamped to the ground potential. Next, when the external signal is inverted, transistors Qll, Ql. is cut off, and transistor Ql3 becomes conductive.

This state is shown at timing T1 in FIG. Node N2 is driven to a negative potential by the signal at node N1 via coupling capacitor C1, but when this negative voltage value becomes lower than substrate bias voltage VBB, transistor Q4 and diode D1 become conductive and charge flows from the substrate. . At this time, the potential of the node N2 becomes equal to the potential of the node N4 due to conduction of the transistor Ql3. Now, when the negative potential of node N4 is VN4, VN4<-(VthQ
ll+VthQl2) (1), transistors Qll and Ql2 become conductive.

However, here Vth,l,,Vth. l2 is the threshold voltage of transistors Qll and Ql2, respectively. Therefore, charges flow in from the power supply VcO, and the negative potential V of the node N2
N2 is stabilized at the following value. VN2:1 (VthQll+
VthQl2) (2) In this way, node N2
The negative potential of can be kept constant at a value determined by the threshold voltages of transistors Qll and Ql2, thus achieving the purpose of stabilizing the substrate bias voltage.

Furthermore, from the relationship in equation (2), VBB-VN2 - (VthQll+ThQl2)
(3), so the transistors Q,,,Q,.

etc. in 1.1. (ion implantation) and its threshold voltage VthQ,,,VthQ,. It is also possible to determine the value of substrate bias voltage VBB by controlling . As explained above, according to the substrate bias circuit of the present invention, even if there are fluctuations in the power supply voltage or substrate bias current, the negative voltage value of the node to which the oscillator voltage is supplied via the coupling capacitor can be maintained at a constant value. Therefore, it is possible to stabilize the substrate bias voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a conventional substrate bias generation circuit, FIG. 2 is a circuit diagram showing the configuration of an embodiment of the substrate bias generation circuit of the present invention, and FIG. 3 is a timing diagram showing the operating waveforms of each part. It's a chat. 1...Oscillator, Q,,Q.

Claims (1)

[Claims] 1. A circuit driven by an oscillator signal and supplying an output to a node via a capacitor, and a diode connected in parallel to this, one end of which is connected to the node and conducts when the output of the circuit is at a low level to generate a negative voltage. a first transistor connected between the node and ground, driven by an external signal in phase with the output of the circuit, and conductive when the signal is at a high level to clamp the node to ground potential; a second transistor consisting of one or more transistors, one end of which is connected to the node and is driven by an external signal having a phase opposite to the signal of the circuit, and is conductive when the signal is at a high level and is at a low level; A third transistor to cut off is connected between the power supply and the other end of the third transistor, and is in the cutoff state when an external signal in phase with the output of the circuit is at a low level, and connects the node through the third transistor. a fourth transistor comprising one or more transistors clamping to a negative voltage equal to the threshold voltage of the substrate bias generating circuit.