JPH0326477B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a dynamic MOS RAM, for example.
The present invention relates to a semiconductor integrated circuit suitable for maintaining the level of peripheral circuits of the present invention, and particularly to a semiconductor integrated circuit that can maintain the level of an output signal boosted to a power supply voltage or higher for a long period of time.

The present invention also provides N-channel dynamics.
Since it is most applicable to MOS RAM, the following:
This will be explained using an example.

[Prior art]

An example of a conventional semiconductor integrated circuit that boosts an output signal above the power supply voltage V _CC is shown in FIG. 1. In the figure, 1 and 2 are MOS transistors;
The gate of the MOS transistor 1 receives the drive signal Φ ₁
The drain is connected to the input terminal to which the voltage V _CC is applied, the drain is connected to the power supply terminal to which the power supply voltage V CC is applied, and the source is connected to the output terminal from which the output signal Φ _B is obtained. Further, the gate of the MOS transistor 2 is connected to the input terminal to which the drive signal Φ ₂ is applied,
The drain is connected to the output terminal from which the output signal Φ _B is obtained, and the source is connected to ground (O _v ).
3 is a boosting capacitor, one end of which is connected to the output terminal from which the output signal Φ _B is obtained, and the other end is configured such that the boosting signal Φ ₃ is applied.

The operation of the circuit configured in this way will be explained with reference to the time chart shown in FIG.

First, at time t ₁ , the drive signal Φ ₁ shown in (a) is
At the same time that the drive signal Φ ₂ shown in (b) falls from the "H" level to O _v at the same time as it rises from O v to "H _" level, the output signal Φ _B shown in (d) goes from O _v to "H" level. begins to stand up.

Next, at time t ₂ , the drive signal Φ ₁ shown in (a)
rises above the power supply voltage V _CC , and the output signal Φ _B shown in (d) reaches the level of the power supply voltage V _CC .

Next, at time t ₃ , the drive signal Φ ₁ shown in (a)
falls from the power supply voltage V _CC or above to O _v , and the MOS
At the same time as the transistor 1 turns off, the boosted signal Φ ₃ shown in (c) rises from _Ov to the "H" level.

Next, at time t ₄ , the boosting capacitor 3 boosts the output signal Φ _B to the power supply voltage V _CC or higher. Note that _t5 indicates time.

However, in a circuit configured in this way, when trying to hold the output signal Φ _B at a level boosted above the power supply voltage V _CC for a long time,
Since the MOS transistor 1 is off and there is no current supply source from anywhere, it has the disadvantage that after a long period of time it will not be able to maintain the level boosted above the power supply voltage V _CC due to leakage current. This embodiment is illustrated at time _t5 in FIG.

[Summary of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The purpose of the present invention is to provide an output boosted to a voltage higher than the power supply voltage V _CC for a long time using a simple circuit configuration. An object of the present invention is to provide a semiconductor integrated circuit that can maintain signal levels.

In order to achieve such an object, the present invention provides a charge pump circuit in an output circuit from which an output signal is obtained.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

In FIG. 3, the same reference numerals as in FIG. 1 indicate corresponding parts, and numeral 4 represents an oscillator provided on the same chip, which is configured to output a clock signal Φ _C.

5, 6, 7, and 8 are MOS transistors, and 9 is a charge pump capacitor, which constitute a charge pump circuit 12. The gate of the MOS transistor 5 is connected to an output terminal from which an output signal Φ _B is obtained, and the drain is connected to a terminal to which a clock signal Φ _C is applied. Also, M.O.S.
The gate of transistor 6 is connected to the output terminal from which the output signal Φ _B is obtained, and the drain is connected to the power supply voltage V _CC
is connected to a power supply terminal to which is supplied, and its source is connected to node 10. Further, the gate of the MOS transistor 7 is connected to a power supply terminal to which a power supply voltage V _CC is supplied, the drain is connected to a node 10 , and the source is connected to a node 11 . Further, the gate and drain of the MOS transistor 8 are connected to a node 11, and the source is connected to an output terminal from which an output signal Φ _B is obtained. Reference numeral 9 denotes a charge pump capacitor, one end of which is connected to the source of the MOS transistor 5, and the other end connected to the node 11.

Here, the MOS transistor 7 is connected to the node 11
It operates as a diode functional element that prevents the charge at node 11 from flowing into the power supply voltage circuit even if the voltage at node 11 is higher than the power supply voltage V _CC . Furthermore, the MOS transistor 8 operates as a diode functional element that prevents the charge of the output signal circuit from flowing to the node 11 even if the voltage of the node 11 is lower than the voltage of the output signal circuit.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to the time chart in FIG. 4.

First, since the boosting operation of the output signal Φ _B (see FIG. 4d) from time t ₁ to time t ₄ in FIG. 4 is exactly the same as that in FIG. 2, the explanation here will be omitted.

Then, at time t4 shown in FIG. ₄ , the output signal Φ _B shown at d is boosted above the power supply voltage V _CC , so the MOS transistor 6 is turned on and the node 10 is turned on.
becomes the level of the power supply voltage V _CC . Further, the MOS transistor 5 is turned on, and the clock signal Φ _C from the oscillator 4 is applied to one end of the charge pump capacitor 9.

Now, after the output signal Φ _B rises and is boosted,
Assume that after a long period of time, the "H" level of the output signal Φ _B drops due to leakage current. This embodiment is illustrated at time _t6 in FIG. At this time t ₆ ,
The level of the node 11 is V _CC −V _TH (V _TH : threshold voltage of the MOS transistor).

That is, as described above, the MOS transistor 6
When the voltage level of node 10 is set to V _CC due to turning on of MOS transistor 7, the voltage level of node 11 is lowered because the source of MOS transistor 7 is at V _CC and the gate connected to the power supply voltage circuit is also at V _CC . turns on when is lower than V _CC −V _th . As a result, MOS transistor 7 becomes forward conductive in the direction from node 10 to node 11, and the voltage level V _CC at node 10 is lowered by MOS transistor 7.
The voltage decreases by V _th and the voltage of V _CC -V _th is supplied to node 11. This state is then maintained as is. At this time, the level of the output signal circuit where the output signal Φ _B is generated is higher than the level of node 11, but the current flow from the output signal circuit to node 11 is
This is blocked by MOS transistor 8.

Next, at time _t7 , when the clock signal Φ _C from the oscillator 4 rises from the "L" level to the "H" level as shown in FIG. The level of is boosted to V _CC +V _TH . When the level of node 11 is boosted, MOS transistor 8 is turned on, and the charge stored in charge pump capacitor 9 is supplied to output signal Φ _B. Therefore, the "H" level of the output signal Φ _B , which had slightly decreased at time t ₆ , recovers at time t ₇ .

In other words, when the level of node 11 rises and becomes higher than the level of the output signal circuit, the MOS transistor, which has been off and in a blocking state, turns on and the high voltage level of node 11 is applied to the output signal circuit. Supplied. At this time, node 1
The level of 1 becomes higher than the level of node 10, but in this state, MOS transistor 7 is in an off state, so that current flow from node 11 to node 10 is blocked. For this reason, the charge in the charge pump capacitor 9 does not escape to the power supply circuit side. Thus, MOS transistor 7 acts as a forward diode function element from node 10 to node 11, and MOS transistor 8 acts as a forward diode function element from node 11 to the output signal circuit.

By such an operation, the "H" level of the output signal Φ _B , which has been boosted above the power supply voltage V _CC , is maintained by the charge pump circuit 12 .

On the other hand, when the output signal Φ _B is at "L" level,
Since MOS transistor 5 and MOS transistor 6 are off and charge pump circuit 12 does not operate, charge pump circuit 12 has no effect on output signal Φ _B.

FIG. 5 is a circuit diagram showing another embodiment of the present invention,
Components that are the same as those in FIG. 3 are designated by the same reference numerals and their explanation will be omitted.

In this Figure 5, 13 has a gate that is at the power supply voltage.
connected to the power supply terminal to which V _CC is supplied, the drain connected to the output terminal from which the output signal Φ _B is obtained,
This is a MOS transistor whose source is connected to the gate of MOS transistor 5. And this
MOS transistor 13 as charge pump circuit 1
2 has the advantage that the MOS transistor 5 can be turned on more strongly, but the basic operation is the same as the embodiment shown in FIG. 3 (see FIG. 4).

FIG. 6 is a circuit diagram showing still another embodiment of the present invention.

In FIG. 6, the same reference numerals as in FIG. 5 indicate corresponding parts. The difference between FIG. 6 and FIG. 5 is that the gate of the MOS transistor 7 is connected to a terminal to which an external clock signal Φ _D is applied;
Further, the drain of the MOS transistor 13 is also connected to the terminal to which the clock signal Φ _D is applied. Here, this clock signal Φ _D is in phase with the output signal Φ _B , and the "H" level is the power supply voltage V _CC
This is the signal.

The basic operation of the embodiment shown in FIG. 6 constructed in this way is the same as that of the embodiment shown in FIG.
(see figure) is easily understood, so the explanation here will be omitted.

Although the present invention has been described above using an N-channel MOS transistor as an example, the present invention is not limited thereto, and can also be applied to P-channel MOS transistors and other field effect transistors. Needless to say.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a simple circuit configuration in which a charge pump circuit is provided in an output circuit that can obtain an output signal boosted to a voltage higher than the power supply voltage is achieved without using any complicated means. Since the increased pressure level can be maintained for a long time, the practical effect is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional semiconductor integrated circuit, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram showing an example of a semiconductor integrated circuit according to the present invention. FIG. 4 is a time chart for explaining the operation of FIG. 3, FIG. 5 is a circuit diagram showing another embodiment of the invention, and FIG. 6 is a circuit diagram showing still another embodiment of the invention. 5-8...MOS transistor, 9...capacitor for charge pump, 10, 11...node, 12...
...Charge pump circuit, 13...MOS transistor.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit that boosts an output signal to a power supply voltage or higher, an output signal circuit that is selectively controlled to a power supply voltage potential or a ground potential and is supplied with a boosted signal via a first capacitor. A charge pump circuit is connected to the first node, and the charge pump circuit is connected between the first node and the second node to which the clock signal is supplied via the second capacitor, and the charge pump circuit is connected to the first node. a first diode functional element that blocks the charge at the first node from flowing to the second node even if the voltage at the second node is higher than the voltage at the second node; and between the second node and the power supply voltage circuit. a switching element connected to the output signal circuit whose on/off state is controlled by the voltage of the output signal circuit; 1. A semiconductor integrated circuit comprising: a second diode functional element that prevents current from flowing to a node.