JPS5951750B2 - Substrate bias generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate bias generation circuit for applying a bias voltage to a silicon semiconductor substrate in a MOS type IC.

In a MOS type IC, a substrate bias voltage is applied between a silicon semiconductor substrate and a ground potential.

Conventionally, such a substrate bias voltage has often been applied externally.

However, providing a bias generation circuit for this purpose is complicated and undesirable from a cost standpoint, so I
A bias generation circuit is provided in the C chip to internally supply a substrate bias voltage. FIG. 1 is a circuit diagram showing the configuration of a conventional substrate bias generation circuit. In the figure, 1 is an oscillator, Q,,Q. , Q, ,Q are transistors, D is a diode, Cl is a coupling capacitor, and N2 and No are connected to nodes.
In FIG. 1, the signal of oscillator 1 is transmitted by transistor Q,
,Q.

An output is generated at the node N2, and is applied to the node No via the coupling capacitor Cl. n-channel MO
In the case of S, the substrate is p-type silicon, and it is necessary to apply a negative substrate bias voltage to it. Now, when the potential of node N2 rises, transistor Q becomes conductive and node No.
to ground potential. Next, when the potential of the node No falls, No becomes a negative potential and the transistor Q3 is not conductive, so that a negative voltage is generated at the output terminal T through the diode D or the transistor Q. In this way, the negative substrate bias voltage VBB can be generated by the output of the node N2 that oscillates between the positive power supply voltage Vcc and the ground potential. In the circuit shown in FIG. 1, the node No becomes functional only when the potential becomes more negative than that of the substrate and the diode D or transistor Q is turned on.

For this reason, electrons are injected from the n-diffusion layer to the p-layer of the substrate due to the forward characteristics of the diode D, which adversely affects information in dynamically operating peripheral circuits, memory cells, and the like. For this reason, a transistor Q4 is provided in parallel with the diode D1 to minimize the potential difference between the potential of the node N2 and BB. However, since the same potential is applied to the gate and drain of the transistor Q4, it is not possible to sufficiently increase the mutual conductance Gm, and therefore it is not possible to effectively suppress the electron injection as described above. The present invention seeks to eliminate these drawbacks of the prior art, and its purpose is to minimize the voltage drop by controlling transistor Q4 in the circuit of FIG. An object of the present invention is to provide a substrate bias generation circuit that can prevent injection.

To achieve this objective, the substrate bias generation circuit of the present invention includes a first circuit driven by an oscillator signal and supplying an output to a first node via a capacitor;
a second circuit driven by an external signal and supplying an output in phase opposite to the output of the first circuit to a second node via a capacitor; a second circuit connected between the first node and ground; a first transistor that is conductive when the output of the first circuit is at a high level and clamps the potential of the first node to the ground potential; a first transistor whose cathode is connected to the first node; the output of the first circuit is at a low level; a diode that conducts and outputs a negative voltage when
a second transistor that conducts when the potential of the node is high level and shuts off when the potential of the node is low level; the second transistor is connected between the second node and the output terminal of the diode and is connected when the potential of the first node is high level; It is characterized by comprising a third transistor which is turned off when conductive and at a low level. Examples will be described in detail below.

FIG. 2 is a circuit diagram showing the configuration of an embodiment of the substrate bias generation circuit of the present invention.

In the same figure, the symbols 1, Q1, Q2, Q3, Q4, D
1, C1, N1, and N2 are the same as in FIG. Q5, Q6, and Q7 are transistors, q is a coupling capacitor, and N3, N4, and N5 are nodes. Further, FIG. 3 is a time chart showing four operational waveforms of each part in the circuit of FIG. 2.

In the same figure, (a) is node N1, and (b) is node N2.
, (c) show the signals at the node N4, and (d) show the signals at the node N3, respectively. In FIG. 2, node N4 is connected to the gate of transistors Q6 and Q7.
Signals VA and VB are applied so that they are in opposite phase to 1.

As a result, when the node N2 becomes negative or equal to the substrate bias voltage VBB, for example as shown at timing T1 in FIG. 3, the transistor Q5 enters the cut-off state. At this time, if signals A and 3 are controlled so that node N4 goes from low level to high level, the signal at node N4 is applied to node N3 via coupling capacitor C2, and node N3 rises from the substrate bias voltage VBB. (
VOO-VBB) voltage (or (VOO-VthQ6
-VBB) voltage; however, VthQ6 is the transistor Q6
threshold voltage). This results in transistor Q
4 is conductive, so the substrate bias voltage VBB is at node N
2, and no electron injection occurs. next,
When the signal from the oscillator 1 changes the node N1 from low level to high level, and therefore the node N2 changes from low level to high level via the coupling capacitor C1,
Transistor Q4 must be turned off.

This is because the substrate bias voltage VBB also becomes high level. Therefore, before sort N2 changes from low level to high level, signals VA and VB are controlled to change node N4 from high level to low level.
As a result, the voltage at the node N3 becomes approximately the same as the substrate bias voltage VBB. In this state, when the node N2 changes from low level to high level, transistor Q5 becomes conductive. The conduction of transistor Q5 causes the voltage at node N3 to become equal to substrate bias voltage VB3, thereby blocking transistor Q4. As explained above, according to the substrate bias generation circuit of the present invention, the voltage drop in the diode D1 can be kept to a minimum, and therefore electron injection from the n-layer diffusion layer to the p-layer of the substrate as described above can be prevented. It can be prevented.

As a result, it is possible to prevent adverse effects on information stored in peripheral circuits and memory cells, and to ensure stable operation of the IC, resulting in excellent effects.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a conventional substrate bias generation circuit, FIG. 2 is a circuit diagram showing the configuration of an embodiment of the substrate bias generation circuit of the present invention, and FIG. 3 is a timing diagram showing the operating waveforms of each part. It's a chat. 1...Oscillator, Q,,Q.

Claims (1)

[Claims] 1. A first circuit driven by an oscillator signal and supplying an output to a first node via a capacitor, and a first circuit driven by an external signal to supply an output in opposite phase to the output of the first circuit through a capacitor. a second circuit that supplies power to the second node via the first node, and is connected between the first node and the ground, and conducts when the output of the first circuit is at a high level, bringing the potential of the first node to the ground potential; a first transistor to be clamped; a diode whose cathode is connected to the first node and which conducts when the output of the first circuit is at a low level to output a negative voltage; a second transistor which is connected in parallel with the diode; a second transistor that is conductive when the potential of the node is high level and cut off when the potential is low level; the second transistor is connected between the second node and the output terminal of the diode and is conductive when the potential of the first node is high level; The third switch that shuts off when the level is low.
A substrate bias generation circuit characterized by comprising a transistor.