JPS5952867B2 - Imaging device - Google Patents

Description

[Detailed Description of the Invention] In a color imaging device using a solid-state imaging body such as a BBD or a CCD, a part of the image obtained from the image PA includes characters and numbers, for example, as shown in FIG. In order to insert a desired pattern image PB such as PB, it is necessary to prepare a pattern generator, but if this is built into a color imaging device, it may be configured as shown in FIG. 2, for example.

In the figure, 1 indicates the imaging system, and the subject 2 is the solid-state imaging body 3.
The output, that is, the imaging output SA, is supplied to the color encoder 5 via the process circuit 4.

This color encoder 5 outputs a desired blank video signal S.
B. When the solid-state image sensor 3 is composed of a CCD, the solid-state image sensor 3 is usually constructed as shown in FIG. The figure shows the case of a solid-state imaging body that uses a frame transfer method, and includes an imaging section 3A having a plurality of light receiving sections serving as picture elements arranged vertically and horizontally;
It is composed of an accumulation section 3B for transferring and accumulating the carriers accumulated in the imaging section 3A, and a horizontal shift register 3C for further transferring the carriers in the horizontal direction.

6 indicates an output terminal.

When such a solid-state image sensor 3 is used, its drive system is configured as follows.

That is, a synchronization board 7 is provided, from which pulses PH and PV corresponding to the horizontal and vertical scanning frequencies are formed, and then supplied to the drive signal forming circuit 8 to transmit pulses in the vertical direction as shown in FIG. The clock pulses φc are respectively supplied to the horizontal shift register 3C. These pulses φClφV are supplied to the desired terminals of the solid-state image sensor 3 via the drivers 9, respectively. On the other hand, a pattern generator 10 built in this color imaging device is a pattern generator 1 called a character generator.
1, and a clock generator 12 is provided to drive the pattern generator 11.

That is, the address counter 13 is driven by a signal synchronized with the horizontal and vertical pulses obtained by the clock generator 12, and the pattern generator 11 is driven by its output. Note that 14 indicates a pattern designation circuit, and for convenience, in this example, a case will be described in which the date is displayed on a part of the image PA.

Therefore, the date designated by this designation circuit 14 is obtained as the output Sc of the pattern generator 11, which is supplied to the color encoder 15 in the same way as the imaging system, and then this color signal SO is output to the imaging system. Combiner 1 along with color signal SB
6. In this example, a part of the image PA is extracted and the date PB is displayed on the extracted part, so a cutting circuit is shown as the synthesis circuit 16. The control signal SE for cropping is a color signal S as shown in the figure.

The cutout control circuit 17 operates based on the following. Color signal S. The clipping circuit operates only when the color signal S is obtained. is output only. 18 indicates an output terminal.

By the way, the pattern generator 10 configured in this way
Since it is necessary to synchronize the two in a color imaging device with a built-in
and clock generator 12 must be locked.

Further, as is clear from FIG. 2, if the pattern generating device 10 itself is built into the color imaging device, there is a drawback that the configuration becomes complicated. In view of these points, the present invention is intended to facilitate synchronization and simplify the configuration.

The apparatus of the present invention will be explained in detail with reference to FIG. In the present invention, as shown in FIG. 4, a commonly used synchronous board 7 is provided, and horizontal and vertical pulses PH and PV obtained from this synchronous board 7 are supplied to a drive signal forming circuit 8. A signal necessary to drive the solid-state image sensor 3, that is, a transfer pulse φ.

, φ, and drives the pattern generator 10 based on pulses obtained from the synchronous disk 7 and the drive signal forming circuit 8. Here, since the pattern to be displayed in a part of the image PA is the date as described above, the pattern generating device 10 may be configured to be able to display a total of 10 numbers from 0 to 9.

That's why. In this example, a character generator 20 is provided for generating numeric patterns from 0 to 9. When and how the character generator 20 is driven is controlled by the output of the character designation circuit 14. The configuration of the character designation circuit 14 is not directly related to the gist of the present invention, and will therefore be omitted. To explain such a drive system step by step, as described above, the horizontal and vertical pulses PH and PV obtained from the synchronization board 7 and the horizontal transfer pulse φ obtained from the drive signal forming circuit 8 are used.

are supplied to the address counter 13, for example, the first
These pulses PH, PV and φ are set so that the image PB is displayed at the shaded position as shown in the figure. Its position on the screen is counted based on. In order to display the date image PB in a part of the image PA, it is sufficient to consider a total of six areas (addresses) from T1 to T6 as shown in FIG. In other words, it is sufficient to display the year, month, and day as the date. In order to display designated numbers at each address from T1 to T6, first, the output obtained by the counter 13 is supplied to the address signal forming circuit 21, and the position currently being scanned is determined. , the address signal forming circuit 21 generates outputs corresponding to T1 to T6 according to the respective scanning positions.

The signals corresponding to each address obtained by the address signal forming circuit 21 are supplied to the drive control circuit 22 of the character generator 20 together with the output of the character specifying circuit 14. Therefore, the drive control circuit 22 controls which numbers are displayed at which addresses. The output character signal corresponding to the desired number selected from among the numbers 0 to 9 by the character generator 20 is supplied to the above-mentioned clipping circuit 16 via the synthesis circuit 23. Here, the cutout circuit 1 is supplied with a control signal SE for the cutout, and in this example, the output obtained from the address signal forming circuit 21 is used as the control signal SE.

That is, as shown in FIG. 5, when the signals corresponding to the addresses T1 to T6 are formed, the image P is formed in a part of the image PA.
Since this indicates that B should be displayed, if the OR output of each address signal obtained by the address signal forming circuit 21 is used as the control signal SE, the same control operation as described above can be achieved. . Note that this cutout circuit 16 is different from that shown in FIG. 2 and is interposed in the transmission system immediately after the imaging output SA of the solid-state imaging body 3 is obtained.

Therefore, as the output of the pattern generator 10, the output which has not yet been encoded is also supplied to the clipping circuit 16. Output SO obtained from the cutout circuit 16
is supplied through the process circuit 4 to a color encoder 24 having a shared configuration. Here, after being converted into color signals, the signals are led to the output terminal 18 via a synthesizer 25 to which a synchronizing signal is supplied. Now, the character signal is the horizontal transfer pulse φ as described above. It is formed by address data formed based on the horizontal transfer lock φ in the solid-state image sensor 3. Since the image signal SA is formed by sequentially reading out the pixel information for each pixel based on the image data, the bit data that makes up the character signal and the pixel information that makes up the image signal SA are completely synchronized. is removed. In this way, if the pixel information and the bit data of the character are synchronized, it will become the character signal. The image PB can be inserted into the image PA based on the imaging signal SA at a predetermined screen position without causing distortion.

That is, the image signal SA and the character signal S. This means that not only the line phase but also the phase of picture element information and bit data must match. In the above configuration, the horizontal transfer lock φ.

At the same time, the image signal SA is outputted and this horizontal transfer lock φ is output. The address signal and readout clock based on the character signal S. Since both are output in a completely synchronized state, it is possible to insert a distortion-free character image PB. As explained above, in the present invention, the pattern generator 10
In a color imaging device with a built-in image sensor, in particular, by sharing the synchronization system required for each of the imaging system 1 and the pattern generator 10, it is possible to completely synchronize the two without using a genlock configuration. Therefore, the configuration can be simplified and an image PB without distortion can be inserted.

Further, according to the present invention, in addition to being able to simplify the configuration, it also has the effect of eliminating synchronization disturbances. In this example, the imaging output S obtained by the imaging system 1
Since the pattern output SO obtained from A and the pattern generator 10 are encoded after being synthesized, this configuration allows not only the common use of the synchronization system but also the common use of the color processing system. Therefore, the structure can be further simplified. Furthermore, as shown in FIG. 4, if an address signal forming circuit 21 is provided as the pattern generating device 10, the control signal SE for the clipping circuit 16 can be easily formed based on the address signal obtained from the address signal forming circuit 21. Since there is no need to newly provide a control circuit for forming the cutout control signal SE, in combination with the above-described configuration, further simplification can be achieved.

In the above description, the synthesis circuit 16 has a cutout configuration, but it is of course possible to adopt a configuration in which the outputs SA and SO are superimposed on each other.

[Brief explanation of the drawing]

FIG. 1 is a diagram used to explain the present invention, FIG. 2 is a system diagram showing an example of a color imaging device used to explain the invention, FIG. 3 is a configuration diagram showing an example of a solid-state image sensor, and FIG. FIG. 5 is a system diagram showing an example of the color imaging device of the present invention, and is a diagram showing an area of the image PB to be inserted into a part of the image PA. 1 is an imaging system, 10 is a pattern generator, 3 is an imaging body, 2
is the subject, 7 is the synchronization board, 12 is the clock generator,
8 is a drive signal forming circuit, 11 is a character generator, 1
3 is an address counter, and 14 is a designation circuit.

Claims (1)

[Claims] 1 It has a solid-state image sensor having a plurality of picture elements arranged in the horizontal and vertical directions, and this solid-state image sensor sequentially transmits pixel information for each pixel based on a clock pulse generated by a drive signal forming circuit. At the same time, a character generator is driven by an address signal synchronized with the clock pulse outputted from the drive signal forming circuit to form a character signal synchronized with the clock pulse, and this character An imaging device in which a signal and the imaging signal are combined by a combiner.