JPS5953591B2 - electronic translator - Google Patents

Description

[Detailed description of the invention] The present invention relates to an electronic translator.

In recent years, electronic translators have been developed that, when a Japanese word is input, the translated word is translated into English and displayed.

However, because this type of translator needs to store as many words as possible in its memory, which has limited capacity, it is necessary to store as many words as possible in its memory, which has limited capacity. is not stored in memory.
Therefore, the above-mentioned words can only be translated in their original form, and the user has to convert the word he or she wishes to translate into its original form before inputting it into the translation machine. This invention was made in view of the above-mentioned circumstances, and for words that have regular inflections, instead of storing the inflected forms in memory, by storing the original form in a special form, The purpose is to provide an electronic translator that can translate inflectional forms.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a plan view of an electronic translator employing the present invention.

Various key groups 2 are arranged on the top surface of the body 1 of the translator, 3 is a power on and all clear key, 4 is a power off key, 5 is a key for instructing Japanese input mode, and 6 is for instructing English input mode. 7 is a key for instructing translation of an input word or sentence, 8 is a single character correction key, 9 is a lowercase letter designation key, and 10 is a space key. On the other hand, the remaining keys are keys for inputting English or Japanese. After operating the above Japanese key 5, the kana written on each key is input, and after operating the English key 6, each key is input. The alphabet written in is input. Further, 11 is a display section, which is composed of, for example, a 20-digit 5.times.7 dot matrix liquid crystal display device. l Next, FIG. 2 shows the overall configuration of an electronic translator adopting this invention. 20 decodes the key operation signals of each group 1 and sends the key codes of alphabet keys, kana keys, etc. to the key buffer 21, and also sends the key codes of the Japanese key 5, English key 6, translation key 7, etc. This is a decoder that sends the key code to the control circuit 22 when a key is operated.

This control circuit 22 controls the entire system and includes microinstruction, timing control circuits, and the like. The control circuit 22 also includes a memory 22M.
is connected. This memory 22M includes arithmetic registers,
A flag register is configured. The key buffer 21 sequentially shifts and holds the input characters, and when a readout signal is given from the control circuit 22 via the signal line a, the stored word information is transferred to the bus line. It is sent to the comparator circuit 23 via b. This comparison circuit 23 is supplied with the data output from the first ROM pattern 24 via the bus line C, and according to the comparison command applied from the control circuit 22 via the bus line a, The data of the key buffer 2] and the data of the first ROM pattern 24 are compared, and the comparison result is applied to the bus line a.
At the same time, the character portions that match as a result of the comparison are sent to the control circuit 22 via the bus line d. The first ROM pattern 24 is the third
It has a storage structure as shown in the figure, and stores the ending part of a word's inflection and the situation flag when the ending is used. Note that the ending part of the word is memorized in reverse order. On the other hand, 25 is a second ROM pattern, which consists of an English area and, as shown in FIG. 4, stores words, their part-of-speech information, and addresses where words to be translated are stored. Thus, for example, the past tense of the word "STOP" becomes "STOPPED", the same letter P is superimposed on the ending P of the original word, and "ED" is added after that. In this way, words that overlap the ending of the original form when inflected are marked with a special mark ``△'' at the end of the original form. Characters that should be overlapped are added. This second ROM pattern 2
5 is stored in the discrimination circuit 26 and the bus line e.
is supplied to the comparison circuit 23 via the control circuit 22 and compared with data sent out via the bus lines D and b
be done.

Addressing of the first ROM pattern 24 and the second ROM pattern 25 is performed using address information obtained by decoding an addressing signal outputted from the control circuit 22 via the bus line f by the ROM address decoder 27. Each of them will be affected. The discrimination circuit 26 is a second RO
It is determined whether or not there is a special mark in the word read from the M pattern 25, and the characters until the special mark is detected are sent to the comparison circuit via the bus line e, and the special mark detection signal is sent to the signal line. Control circuit 2 via g
This is a circuit for sending data to 2, the details of which will be described later.

Further, 28 is an address buffer for storing a bilingual address stored together with the word in the second ROM pattern 25 that matches the input word as a result of the comparison process, and the data stored in this address buffer 28 is The ROM address decoder 27 decodes the second ROM pattern 2.
Specify address 5. 29 is a display control circuit, and 30 is a display device, which displays input words and translated words.

Next, the configuration of the discrimination circuit 26 will be explained with reference to FIG. The word data output from the second ROM pattern 25 is written into the buffer 52 via the AND gate 51, and sent to the comparison circuit 23 via the bus line e. Further, the data from the second ROM pattern 25 is sent to the decoder 5.
3 is input and decoded, and when a special mark "△" is detected, it outputs a "1" signal to the NAND gate 54. On the other hand, 55 is an S-R type flip-flop, and the first R
A set signal S is applied from the control circuit 22 when matching data is obtained in the comparison process for the data of the OM pattern 24, and a set signal R is applied when no matching data is obtained.
The output signal of the flip-flop 55 when set is supplied to the NAND gate 54. Therefore, this NAND gate 54 has the first R when the translation mode is English→Japanese mode.
When a matching output is obtained during the comparison process with respect to the OM pattern 24, only when a special mark is detected in the word read from the second ROM pattern 25, the output is "
0''.The output signal from this NAND gate 54 is supplied as a gate signal to the above gate 51, and is also output as a comparison processing stop request signal to the control circuit 22 via the signal line g.Next Next, the operation of this embodiment configured as described above will be explained.

First, taking the case of translating the word "SPEAKS" as an example, first operate the English key 6 to set the English input mode.

At this time, the operation signal of the English key 6 is decoded by the key decoder 20, and the key code is sent to the control circuit 22, whereby the control circuit 22 is set to the English input mode. Next, “SPEAKS” by Alphabet Tokiichi
When inputted, a code for each alphanumeric character is created by the key decoder 20 and inputted to the key buffer 21. Next, when the translation key 7 is operated, the operation signal is sent to the control circuit 2.
2, the control circuit 22 gives a read command to the key buffer 21 via the bus line a, and the comparison circuit 2
The comparison process is started by outputting a comparison command to the first ROM pattern 24 and specifying the start address of the first ROM pattern 24 via the bus line f. At this time, the first ROM from the end of the word stored in the key buffer 21
The contents of pattern 24 will be compared. That is, "SPEAKS" will be compared in the order of "SKAEPS".

First, "D" is read from the first ROM pattern 24 and input to the comparison circuit 23 together with the contents of the key buffer 21, and a comparison process is performed. Control circuit 2 through
Send to 2. As a result, the address of the first ROM pattern 24 is incremented and then compared with "DE". Similarly, when "S" is read from the first ROM pattern 24, a match of the last "S" in [SPEAKS] is detected, and the comparison circuit 23 is connected to the control circuit 22 via the bus line a. Outputs a match signal.

The control circuit 22 receives this coincidence signal and applies a set signal S to the flip-flop 55 in the discrimination circuit 26 via the bus line a. In addition, the first ROM pattern 2
The flag information indicating the status stored together with the data "S" read from 4 is sent to the control circuit 22 via the comparison circuit 23 and the bus line d, and written into the flag register configured in the memory 22M. It will be done. Further, the control circuit 22 deletes the matching characters from the words stored in the key buffer 21 and writes the remaining characters into the memory 22M. As a result, "SPEAK" is stored in the memory 22M. Next, the data stored in this memory 22M and the data stored in the second ROM pattern 25 are compared. First, control circuit 2
2 specifies the start address of the second ROM pattern 25 via the bus line f. The word at the designated address is read from the second ROM pattern 25 and supplied to the AND gate 51 and decoder 53 of the discrimination circuit 26 . At this time, the translation mode is English → Japanese mode,
In addition, a flip-flop 55 is set. Therefore, "SPEAK" in the second ROM pattern 25
When the address is specified, the read data is sent to the AND gate 51 and decoder 53 as "S" and "P".
, "E", etc., but since the special mark is not detected by the decoder 53, the output of the NAND gate 54 is n", so the data output from the second ROM pattern 25 is It is sequentially written into the buffer 52 via the AND gate 51 as it is.Then, the comparison circuit 23
is sent to the memory 22M and compared with the data written in the memory 22M, and if a match is detected, the data is sent to the second ROM 22M.
The part-of-speech information and bilingual address stored together with the pattern 25 "SPEAK" are determined by a discrimination circuit 26, a comparison circuit 23,
It is read into the control circuit 22 via bus line d, and it is determined that the part of speech is a verb.

Therefore, as the status flag of "S" read out in the first ROM pattern 24, the information of "plural form" and "third person singular present tense" is held in the flag register in the memory 22M. , "SPEAK" is a verb, so it can be seen that it is in the "third person singular present tense", and the "plural" flag is cleared. Further, after the bilingual address is written to the ROM address buffer 28, the second R
The OM pattern 25 is designated and the word "Hanas", which is a translation of "SPEAK", is read into the memory 22M. The translated word "Hanas" obtained by the above operation is sent to the display device 30 via the display control circuit 29 together with the flag information,
The information is displayed on the display unit 11 in the form shown in FIG. 6a, for example. Furthermore, when "CATCHES" is input, the same operation as above is performed, and [E
S] is "CATCH" from the second ROM pattern 25
is searched and the translated word ``Tsukamael'' is obtained.

Next, a case will be explained in which a word such as "STOPPED" in which the ending of the original word is changed is input.

Regarding the search for the first ROM pattern 24, the same operation as described above is performed, and a match of "ED" is obtained. At this time, "STOPP" is stored in the memory 22M.

In the comparison process for the first and second ROM patterns 25, the second ROM pattern 25 contains "STOP△".
Words are memorized in the form of "P". And "S""T"
” “O” and “P” in the same manner as above.
or when the special mark "△" is read out, the decoder 53 outputs a ``1'' signal, the output of the NAND gate 54 becomes 0'', and the special mark "△" is read out by the AND gate 51. inhibited. At the same time, the "0" signal output from the NAND gate 54 is given to the control circuit 22 as a comparison operation stop request signal via the signal line g. Therefore, the control circuit 22 stops the comparison operation by one character. When the next character "P" is read out from the ROM pattern 25 following the special mark "△", the output of the decoder 53 becomes 4' again, the output of the NAND gate 54 becomes 417, and the AND gate 5 opens. It will be done. Therefore, the character "P" read from the second ROM pattern 25 is written into the buffer 52 via the AND gate 5. Also, since the output of the NAND gate 54 becomes "," , control circuit 22
gives a comparison command to the comparison circuit 23. As a result, the comparison operation is restarted, and the data stored in the memory 22M "
A match between "STOPP" and "STOPP" read from the second ROM pattern 25 is detected.

By this match detection 2, the second ROM pattern 25 "
The translation address for “STOP△P” is address buffer 28
By specifying the address where the corresponding translated word is stored in the second ROM pattern 25,
The translated word "Tomal" is read out and displayed on the display section 11 as shown in FIG. 6, 5b. Although the above explanation did not explain the search operation when the word is input in its original form, the input word is first searched in the second ROM pattern 25 in its original form, and 3 matches are found. If no word is found, it is sufficient to perform the above-mentioned word ending search process.

When searching for the second ROM pattern 2, the "0" signal of the NAND gate 54 generated when the decoder 53 in the discrimination circuit 26 detects a special mark acts as a temporary stop request instead of a comparison process termination request. By doing so, comparisons can be made with the special marks removed. In addition, in the above embodiment, flags indicating situations such as third person singular present tense, plural tense, past tense, etc. are read out,
Although the corresponding situation is displayed when displaying the translated word, the translated word itself may be transformed into a form suitable for the situation based on this flag information.

Furthermore, in the above embodiment, the processing when English is input is explained as an example, but when Japanese is input, the processing can be performed using the same principle.

As detailed above, according to the present invention, for words that have a regular inflection and overlap characters at the end of the original form, a special mark and the character to be overlapped are added to the end of the original form of the word. When a word with such inflection is input, the input word is changed into a form with the regularly changing endings deleted, and the special mark in the dictionary memory is stored in the dictionary memory. Since the search is performed by sequentially comparing with the excluded memorized words, it is possible to translate the inflectional forms of such words without separately storing them in the dictionary memory, and this reduces the number of words stored in the dictionary memory. This has the effect of increasing the number of words that can be translated without increasing the number of words.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; Fig. 1 is a plan view of the main body of the translator, Fig. 2 is a block diagram showing the overall system configuration, and Fig. 3 is the first ROM pattern in Fig. 2. 4 is a storage state diagram of the second ROM pattern, and FIG. 5 is a diagram showing the configuration of the discrimination circuit.
FIGS. 6A and 6B are diagrams showing an example of a display state. 22... Control circuit, 23... Comparison circuit, 24...
First ROM pattern, 25... Second ROM pattern, 26... Discrimination circuit.

Claims (1)

[Claims] 1. In an electronic translator that stores a first word and a word in a second language in a dictionary memory and searches the dictionary memory for the input word to read out a word that is a parallel translation of the input word, Among words that undergo inflection, words that overlap characters at the end of the original form when inflected are stored in a dictionary memory in which special marks and characters to be overlapped are added to the end of the original form, and words that undergo regular inflection are stored. A dictionary memory for endings that stores inflectional endings, a means for sequentially comparing the endings of the input word with the memory contents of the dictionary memory for endings, and a matching ending of the input word being deleted by the comparison means detecting a match. and means for sequentially comparing the input word whose matching ending has been deleted by the deletion means with the stored contents of the dictionary memory excluding the special mark.