JPS6028033B2 - electronic translator - Google Patents

Description

[Detailed description of the invention] The present invention relates to an electronic translator.

In recent years, electronic translators have been developed that, when a Japanese word is input, the translated word is translated into English and displayed.

However, because this type of translator needs to store as many words as possible in its memory, which has limited capacity, it is necessary to store as many words as possible in its memory, which has limited capacity. I don't remember the memo about this.
Therefore, the above-mentioned words can only be translated in their original form, and there is a problem in that the user must first convert the word he or she wishes to translate into its original form before inputting it into the translation machine. This invention was made in view of the above circumstances, and for words that have regular inflections, by storing the original form in a special form without storing the inflected form in memory, The purpose of this invention is to provide an electronic translator capable of translating inflectional forms.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a plan view of an electronic translator employing this invention. Various key groups 2 are arranged on the top surface of the main body 1 of the translator, and 3
is a power-on and all-clear key, 4 is a power-off key, 5 is a key for instructing Japanese input mode, 6 is a key for instructing English input mode, 7 is a key for instructing translation of an input word or sentence, 8 is a single character correction key, 9 is a lowercase letter designation key, and 10 is a space key. On the other hand, the remaining keys are keys for inputting English or Japanese. After operating the above Japanese key 5, the kana written on each key is input, and after operating the English key 6, each key is input. The alphabet written in is input. Further, reference numeral 11 denotes a display section, which is comprised of, for example, a 2q-row 5×7 dot matrix liquid crystal display device. Next, FIG. 2 shows the entire electronic translation machine adopting this invention. 20 decodes the key operation signals of each of the above key groups and sends key codes for alphabet keys, kana keys, etc. to the key buffer 21, and also for key operations of control keys such as Japanese key 5, English key 6, translation key 7, etc. is a decoder that sends the key code to the control circuit 22.

Since the control circuit 22 controls the entire system, it includes microinstructions, a timing control circuit, registers for calculation, and the like. The key buffer 1 sequentially shifts and holds the input characters, and when a read signal is given from the control circuit 22 via the signal line a, the stored word information is transferred to the bus line b. The signal is sent to the comparison circuit 23 via. This comparison circuit 2
3 is connected to the first ROM pattern 24 via the bus line c.
The data output from the key buffer 21 and the first ROM pattern 24 are supplied with data outputted from the key buffer 21 in accordance with a comparison command applied from the control circuit 22 via the bus line a.
The comparison results are output to the control circuit 22 via the bus line a, and the character portions that match as a result of the comparison are sent to the control circuit 22 via the bus line d. The first ROM pattern 24 has a storage structure as shown in FIG. 3, and stores the ending part of the inflection of a word and the situation flag when the ending is used. Note that the ending part of the word is memorized in reverse order. On the other hand, 25 is a second ROM pattern, which consists of an English area and a Japanese area, and as shown in FIG. 4, stores words, their part-of-speech information, and addresses where words to be translated are stored. Thus, for example, the number form of the word "CRY" becomes "CRIES", and the ending "Y" of the original form is transformed to become "ESJ".

In words in which the ending of the original form of the inflection is changed in this way, a special character "o" is interposed between the part of the character in the original form that does not change and the part that changes. The words detected in the second ROM pattern 25 are supplied to the discrimination circuit 26 and the comparison circuit 23 via the bus line e, and are compared with the data sent from the control circuit 22 via the bus lines d and b. be done.

The addressing of the first ROM pattern 24 and the second ROM/program pattern 25 is obtained by decoding an addressing signal outputted from the control circuit 22 via the bus line f by the ROM addressing decoder 27. Each address is determined by the address information provided. The above discrimination circuit 2'6 is R of 2
It is determined whether or not there is a special character in the word read from the OM pattern 25, and the characters until the special character is detected are sent to the isolation circuit via the bus controller e, and the special character detection signal is sent to the signal line. This circuit sends the signal to the control circuit 22 via g, the details of which will be described later.

Further, 28 is an address buffer for storing the bilingual address written together with the word in the second ROM pattern 25 that matches the input word as a result of the comparison process, and the data stored in this address buffer 28 is stored in the ROM. The second ROM pattern 2 is decoded by the address decoder 27.
Specify address 5. 29 is a display control circuit, and 30 is a display device, which displays input words and translated words.

Next, the configuration of the discrimination circuit 26 will be explained with reference to FIG.

The word data output from the second ROM pattern 25 is written into the buffer 52 via the AND gate 51, and sent to the comparison circuit 23 via the bus line e. Also,
The data from the second ROM pattern 25 is input to the decoder 53 and decoded, and the special character "o"
When detected, a “1” signal is output to the NAND gate 54. On the other hand, reference numeral 55 denotes an S-R type flip-flop, which, when comparing the data of the first ROM pattern 24, sends a set signal S to the control circuit 24 when a match is obtained, and a reset signal R when no match is obtained. Applied from The reset output signal of this flip-flop 55 is supplied to the NAND gate 54 via an OR gate 56. Further, from the control circuit 22 to the OR gate 56,
A "1" signal is supplied in the Japanese to English translation mode (Japanese input mode). Therefore, when the translation mode is Japanese→English→or English→Japanese mode and no matching output is obtained during the comparison process for the first ROM pattern 24, the NAND gate 54 outputs the second R
Only when a special character is detected in the read word from the OM pattern 25, its output becomes "0". However,
The output signal from this NAND gate 54 is supplied to the AND gate 51 as a gate signal, and the signal line g
It is output to the control circuit 22 as a comparison processing stop request signal. Next, the operation of this embodiment configured as described above will be explained.

First, taking the case of translating the word "SPEAKS" as an example, first operate the English key 6 to set the English input mode.

At this time, the operation signal of the English key 6 is decoded by the key decoder 2, and the key code is sent to the control circuit 22, whereby the control circuit 22 is set to the English input mode. Next, use the alphabet keys to select “SPEAKS”.
”, a code for each alphabet is created by the key decoder 20 and input to the key buffer 21.
Next, when the translation key 7 is operated, the operation signal is given to the control circuit 22, and the control circuit 22 gives a read command to the key buffer 21 via the bus line a, and also outputs a copy command to the comparison circuit 23. , the comparison process is started by specifying the start address of the first ROM pattern 24 via the bus line f. At this time, the first RO from the end of the word stored in the key buffer 21
A comparison will be made with the contents of M pattern 24. That is, "SPEMKS" will be compared in the order of "SKAEPS". First, "D" is read from the first ROM pattern 24 and inputted to the comparison circuit 23 together with the contents of the key buffer 21, and a comparison process is performed, but since there is no match, the comparison circuit 23 sends a mismatch signal via the bus line a. and sends it to the control circuit 22. As a result, the first
The address of the ROM pattern 24 is incremented and then compared with "DE". Similarly, the first
When "S" is read from the ROM pattern 24 of
A match of the last "S" of "SPEAKS" is detected, and the comparison circuit 23 outputs a match signal to the control circuit 22 via the bus line a. The control circuit 22 receives the match signal and applies a set signal S to the flip-flop 56 in the discrimination circuit 26 via the bus line a. In addition, the first
Flag information indicating the status stored together with the data "S" read from the ROM pattern 24 is written to a flag register (not shown) in the control circuit 22 via the comparison circuit 23 and the bus line d. . The control circuit 22 then reads the remaining characters from the words stored in the key buffer 21 after deleting the matched characters into an internal register (not shown) via the bus line d. That is, "SPEAK" is stored in a register within the control circuit 22. Next, a comparison process is performed between the data stored in this internal register and the data stored in the second ROM pattern 25. First, the control circuit 22 specifies the starting address of the second ROM pattern 25 via the bus line f. The word at the specified address is read from the second ROM pattern 25 and supplied to the AND gate 51 and decoder 53 of the discrimination circuit 26.

At this time, the translation mode is English→Japanese mode and the flip-flop 55 is set, so the output of the OR gate 56 is "0". However, the second RO
The above-mentioned AND gate 5
1 and the decoder 53 in the order of "S", "P", "E", etc. However, since the special character is not detected by the decoder 53, the output of the NAND gate 54 becomes "1". The data output from the ROM pattern 25 of No. 2 is sequentially sent to the buffer 5 via the AND gate 51.
2. The data is then sent to the comparison circuit 23 and compared with the data written in the register in the control circuit 22 described above. If a match is detected, the data is stored together with "SPEAK" of the second ROM pattern 25. The part-of-speech information and bilingual address are read into the control circuit 22 via the discrimination circuit 26, comparison circuit 23, and bus line d, and it is determined that the part-of-speech is a verb. However, R of 1 above
As the status flag of "S" read out by the OM pattern 24, information of "plural form" and "third person singular present tense" is held in the flag register in the control circuit 22, but "S"
Since "PEAK" is a verb, it can be determined that it is "third person singular present tense", and the "plural" flag is cleared. Also, the translation address is in the ROM address buffer 2.
8, the second ROM pattern 25 is specified and the word "Hanasu", which is a translation of "SEAK", is read into a register in the control circuit 22. The translated word "Hanasu" obtained by the above operation is sent to the display layer 30 via the display control circuit 29 together with the flag information, and is displayed on the display section 11 in the format shown in FIG. 6, for example.

Further, when "CATCHES" is input, the same operation as described above is performed to retrieve "ES" from the first ROM pattern 24 and "CATCH" from the first love OM pattern 25, and obtain the translated word "Tsukamaeru".

Next, a case will be explained in which a word such as "CRIES" in which the ending of the original word is changed is input.

Regarding the search for the first ROM pattern 24, the same operation as above is performed, and a match of "IES" is obtained. At this time, "CR" is stored outside the register in the control circuit 22. In the comparison process for the second ROM pattern 25, the second ROM pattern 25 contains "CRoY".
” words are memorized. And C”, “R”
Up to this point, the buffer 52 is written in the same manner as above, but when the special character "o" is read, the decoder 53
A "1" signal is output from the NAND gate 54, the output of the NAND gate 54 becomes 0, and the special character "o" is inhibited by the AND gate 51. At the same time, the "0" signal output from the NAND gate 54 is applied to the control circuit 22 as a comparison operation stop request signal via the signal line g. Therefore, the control circuit 22 stops the comparison operation, and when the data "CR" stored outside the internal register matches the "CR" read out from the second ROM pattern 25 and has already been compared, it is determined that the words match. to decide. In other words, the second ROM pattern 25 “
The translation address of "CRoY" is written in the address buffer 28, and by specifying the address where the corresponding translated word in the second ROM pattern 25 is stored, the translated word "
"Naku" is read out. In addition, in the above explanation, before the above "IES" match is obtained, the first RO
In the "S" section of M pattern 24, the ending of "CRIES" is "
However, as a result of the subsequent discrimination operation of the discrimination circuit 26, a match with the word in the second ROM pattern 25 is not obtained. A comparison will be made between the section ``CRIES'' and ``CRIES''.

Although a match is obtained for the ending of the word in this section, a match with the word in the second ROM pattern 25 is not obtained, and a complete match is obtained for the first time in the next ``SEL.'' In this way,
The first ROM pattern 24 is searched until a match is found, and if no match is found in the last term of the first ROM pattern 24, it is treated as untranslatable.
In addition, in the above explanation, we did not explain the search operation when the word is input in its original form, but since the input word is initially unchanged, the search process for the ROM pattern 25' in 2 is performed, and the matching word is found. If it is not found, it is sufficient to proceed to the above-mentioned word ending search process.

Then, when searching for the ROM pattern 25 in No. 2, the "0" signal of the NAND gate 54, which is generated when the decoder 53 in the discrimination circuit 26 detects a special character, is not a request to end the comparison process but a request to stop the comparison process. As a result, the comparison is performed with special characters removed. In addition, in the above example, flags indicating situations such as third person singular present tense, number form, past tense, etc. are read out, and the corresponding situation is displayed when displaying the translated word.
Based on this flag information, the translated word itself may be transformed into a form suitable for the situation. Furthermore, in the above embodiment, the processing when English is input is explained as an example, but when Japanese is input, the processing can be performed based on the same principle.

As described in detail above, according to the present invention, for words that have regular poetic inflections and in which the ending of the original form changes when the inflection changes, a character is interposed between the unchanged part and the changed part of the word. By storing inflections in memory, we have made it possible to translate such inflections of words without having to store them in memory, so it is possible to translate without increasing the number of words stored in memory. This has the effect of increasing the number of words.

[Brief explanation of drawings]

The drawings illustrate embodiments of the invention. Figure 1 is a plan view of the translator, Figure 2 is a block diagram of the system configuration, and Figure 3 is the first RO in Figure 2.
Memory state diagram of M pattern, Figure 4 is also the second ROM
FIG. 5 is a diagram illustrating the configuration of a pattern, and FIG. 6 is a diagram illustrating an example of a display state. 2
2...control circuit, 23...comparison circuit,
24...First OM pattern, 25...
- Second ROM pattern, 26...Discrimination circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. An electronic translation in which words in a first language and words in a second language are stored in a dictionary memory, and the dictionary memory is searched for the input word to read out the word to be translated. In the machine, among words that have regular inflections, words whose original endings change when the inflection changes are stored in a dictionary memory with special marks interposed between the part that does not change and the part that changes, and regular inflections. a dictionary memory for endings that stores the inflectional endings of words to be used; means for sequentially comparing the endings of the input word with the contents of the dictionary memory for endings; and a means for sequentially comparing the endings of input words with the contents of the dictionary memory for endings; and means for sequentially comparing the input word from which the matching ending has been deleted by the deletion means with the memory contents of the dictionary memory excluding the special mark. Electronic translator. 2. In an electronic translator that stores words in a first language and words in a second language in a dictionary memory and searches the dictionary memory for the input word to read out the words to be translated, the basic word is a first dictionary memory for storing inflectional endings of basic words that undergo regular inflection; An electronic translator comprising means for searching both a second dictionary memory and a second dictionary memory.