JPS599996B2 - Driving method for semiconductor devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a charge transfer device, and its purpose is to simplify peripheral circuitry for driving the device.

In recent years, based on the rapid development of semiconductor integrated circuit technology,
A charge transfer device that allows carriers in a thermally non-equilibrium state to freely move within a semiconductor substrate using an external signal has been proposed, and research has been conducted to put it into practical use. These devices are broadly classified into charge-coupled devices (CCDs) and bucket brigade devices (BBDs), and are expected to be used as shift registers and imaging devices. However, in order to drive the device, various pulses are required, including a group of clock pulses, an input sampling pulse for charge injection, and a reset pulse for the hold circuit in the charge detection section, making the peripheral circuit complicated. Become. The present invention provides a new driving method for reducing the complexity of such peripheral circuits.

The present invention is achieved by making the input sampling pulse and the reset pulse the same in phase and pulse width, and has the advantage that the circuits for phase setting and pulse width setting can be simplified. Next, the present invention will be explained in detail with reference to the drawings. Although the description uses a two-phase drive type charge-coupled device, the present invention can be applied to single-phase to four-phase drive type devices or bucket brigade type devices without any modification. is clear from the description in this specification. FIG. 1 is a diagram illustrating the operation of a conventional two-phase drive type charge coupled device.

In the figure, 1 is the device, 2 is a diffusion layer having a different conductivity type from the semiconductor substrate that acts as a charge injection source, and 3 is 2
4 is an input gate electrode that controls the amount of charge injection; 5 is a wiring connected to 4; 6 and 7 are a group of transfer electrodes connected to a set of wirings 8 and 9; 10 is a group of transfer electrodes connected to 9; The connected final transfer electrode, 11 is an output gate electrode, 12 is a wiring connected to 11, 13 is a floating diffusion layer for charge detection that has a conductivity type different from that of the semiconductor substrate, and 14 periodically resets 13. 15 is a wiring connected to 14, and 16 is a diffusion layer similar to 13, which is connected to wiring 17. Furthermore, the floating diffusion layer 13 has a means for connecting the gates of source follower FETs 1 and B provided on the same substrate, and the output signal from the element 1 is detected as a potential across the source resistor 19. be done. The details of the operation of such a structured charge-coupled device are well known to those skilled in the art, so a brief explanation will be provided as an analog shift register.

FIG. 2 is a diagram showing waveforms of various parts for driving the element shown in FIG. 1, and is illustrated for an N-channel type element. In the figure, 28, 29, 23, and 25 are pulse waveforms applied to 8, 9, 3, and 15, respectively;
9 is an output signal waveform appearing at both ends of 19. Time T shown in FIG. In this case, since the pulse 28 becomes a positive voltage, a deep potential well is formed on the substrate surface below the electrode 6 connected to the wiring 8. On the other hand, since the input electric signal to the analog shift register, that is, the delayed signal, is applied to the input gate electrode 4 via the wiring 5, the substrate surface potential under the electrode 4 is determined according to the signal. . Furthermore, since a positive reverse bias voltage is applied to the charge injection source diffusion layer 2, no charge is injected into the well at the potential. Next, at time t[, the reverse bias electric field becomes shallow, so the charge injection is performed. Such injection is determined by the signal voltage to 23, 28 and input gate electrode 4 at time T,. That is, it is known that the amount of charge injected is limited by the channel conductance under the input gate electrode. After time t1, 2 is again strongly reverse biased, so the conductance becomes 0 and charge injection is no longer performed. That is, the delayed signal will be sampled by pulse 23. Next, at time T2, the voltages applied to the wirings 8 and 9 are reversed, so the charge injected at time T and localized under electrode 6 is transferred to under electrode 7.

Of course, in order to realize two-phase drive,
It is necessary that the potential under the electrodes 6 and 7 be directional. Such orientation is not shown, as it is known to be achieved in various ways and is not essentially relevant to the present invention. As is well known, the injected charge is sequentially transferred to the right inside the device shown in FIG. 1 by supplying a two-phase pulse. Next, the charge detection mechanism will be explained. At time T, the transferred charges are localized in the potential well below the final transfer electrode 10 connected to the wiring 9. Phase relationship of such clock pulses At time T, 4 o'clock, the reset pulse shown at 25 is connected to wiring 1.
5 to the reset electrode 14. The electrode 1
4 is provided with a diffusion layer 16 whose ends overlap with each other via an insulating film, and the diffusion layer 16 is connected to an external reverse bias DC power source via a wiring 17. Therefore, the floating diffusion layer 13 constitutes a part of a MOSFET in which 16 is a drain, 14 is a gate, and 13 is a source.
is charged until its potential is equal to the supply voltage to 16. Immediately after time T, the pulse 25 returns to 0 volts, so the channel under the reset electrode 14 disappears, and the source 13 is electrically isolated from the external circuit at time T4.
Then, the pulse 29 becomes O volts, the potential well under the electrode 10 becomes shallow, and charges flow into the electrode 13 through the DC biased output gate electrode 11. Part 13
If the voltage dependence of the capacitance associated with is sufficiently small, the potential change of the source 13 is proportional to the amount of inflowing charge and has a hold function. Under appropriate operating conditions, MOSFET 18 has an output voltage waveform similar to the potential change of source 13 because the gate voltage of the FET, that is, the potential of 13, and the source voltage, that is, the terminal voltage of 19, are directly proportional. 29 will be obtained.

In the operation of such an analog shift register immediate delay circuit, two sets of transfer pulses, an input sampling pulse, and a reset pulse are essential as drive pulse groups. In particular, the conventional single drive method, in which the phase and pulse width of the input sampling pulse and set pulse were individually varied, required a total of four time constant generation circuits, and furthermore, the period of the clock pulse was varied to increase the delay time. In the case of application to a variable delay line that changes the time constant, it becomes necessary to control such a time constant generating circuit according to the period, and the peripheral circuit becomes complicated. On the other hand, according to the present invention, it is possible to reduce the number of such time constant circuits by half, and it is possible to simplify peripheral circuits. FIG. 3 is a diagram showing an embodiment of the present invention, and shows pulse waveforms of various parts for driving the element shown in FIG. 1. In the figure, the same numbers as in FIG. 2 indicate the same parts. In the same figure, 25' shows the reset pulse applied to the reset electrode 15, which is characterized by having the same phase and the same pulse width as the sampling pulse 23, but only the polarity is reversed. The resetting pulse and the sampling pulse are at a time T within a period of 28 positive voltages. If this occurs, it is clear that the aforementioned set function and sampling function can be achieved without any problem.
The output signal waveform during this operation is indicated by 29'. That is, the output signal changes from time t1 when pulse 29 becomes O volts to T. It will be held for a period of time.
However, when the hold period is smaller than the reset pulse period, although the response of the output signal to the delayed signal of high frequency is less degraded, the energy of the delayed signal contained in the output signal becomes small, and the S/ N
The disadvantage is that it deteriorates. FIG. 4 shows another preferred embodiment of the present invention, which aims to eliminate such drawbacks. In this figure, the same numbers as in FIG. 1 indicate the same components. In the figure, the final transfer electrode 10' adjacent to the output gate electrode 11 is connected to the wiring 8. FIG. 5 is a diagram showing pulse waveforms for each part driving the element in FIG. 4. The same numbers as in FIG. , is the sampling pulse, and 39
is the output signal waveform obtained at both ends of 19. In the element structure example shown in FIG. 4, unlike the conventional structure shown in FIG. 1, the phases of the transfer electrodes are the same at the input and output ends. In such an example structure, as shown in the output signal waveform at 39, the pulse 28
fall time, that is, the time t1 when the charge flows into the floating diffusion layer 13, and the reset pulse application time T. Since the period in between can be set to more than half a period of the clock pulse, the energy of the delayed signal included in the output signal increases, and the S/N
It has the advantage that it does not deteriorate. In the element driving examples whose waveforms are shown in FIGS. 3 and 5, cases are shown in which a delayed signal is applied to the input gate electrode 4 and a sampling pulse is applied to the diffusion layer 2. However, a driving method in which a sampling pulse is applied to the input gate electrode 4 and a delayed signal is applied to the diffusion layer 2 is also possible. In this driving method, unlike the cases shown in FIGS. 3 and 5, the sampling pulse has the same polarity as the reset pulse, so that a clock driver for pulse amplification can be shared. In this driving method, the number of clock drivers can be reduced as well as the number of time constant generating circuits compared to the conventional method, so that the advantages of the present invention can be fully realized. Next, an embodiment will be described in which the present invention is applied to a driving method having better injection characteristics than the charge injection method shown in FIGS. 1 to 5. Such a charge injection method is called a potential equilibration method (POtential equilibration method).
The implantation amount is not controlled by the magnitude of the channel conductance directly under the input gate, but is controlled by the height of the barrier directly under the input gate. 6 to 8 are diagrams for explaining one embodiment of the present invention, and the same numbers as in FIGS. 1 to 5 indicate the same components. In FIG. 6, 40 is an electrode placed between the input gate electrode 4 and the first transfer electrode 6, and is connected to an external DC bias power source via a wiring 41.

FIG. 7 is a diagram showing various pulse waveforms for driving the element 1 shown in FIG. 6. FIG. 8 is a detailed operational diagram of the injection section for explaining the mechanism of charge injection, and the same numbers as in FIG. 6 indicate the same components. Figures a to d are T shown in FIG. - The potential relationship near the input gate electrode and the behavior of the injected charge at each time of T3 are shown. A brief explanation of the charge injection method will be given. Time T. Then, 2 is strongly reverse biased by 33, so 40
No charge is injected into the potential well formed directly below.
At time t1, 2 is biased almost in the forward direction by 33, so charge is sufficiently injected into the potential well immediately below 40, regardless of the magnitude of the delayed signal voltage applied to the input gate electrode. . At time T2, the diffusion layer 2 is strongly reverse biased by the pulse waveform 33, so that part of the charge excessively injected at time t1 is returned to the diffusion layer region 2 again. This charge movement continues until the substrate surface potentials immediately below the electrodes 4 and 40 become equal. That is, the amount of charge accumulated in the potential well directly below the electrode 40 is controlled by the delayed signal applied to the electrode 4. Next, at time T3, a deep potential well is formed under the electrode 6, so the injected charge is transferred directly below the electrode 6. Furthermore, as shown in FIG. 6 and FIG. 7, at time t1, the floating diffusion layer 13 is reset by the pulse 35 at the same time as excessive charge is injected below the layer 40. The resetting and charge detecting mechanisms are the same as those in the embodiment shown in FIG. 4, so their explanation will be omitted. As described above, it is clear that the present invention can be easily applied to a charge injection method called a potential equilibration method. FIGS. 9 and 10 are diagrams for explaining other embodiments of the present invention, which are embodiments for charge-coupled devices having a plurality of transfer channels.

FIG. 9 is a plan view of an element having such a configuration, and FIG. 10 is a pulse waveform of each part for driving the element. In FIG. 9, the same numbers as in FIGS. 1 to 8 indicate the same components. In the figure, reference numeral 50 denotes a control electrode for sequentially injecting charges into a plurality of transfer channels, to which the pulse train shown in FIG. 10 51 is applied. 7' and 6' are transfer electrodes constituting the second transfer channel, and are connected to wirings 9' and 6', respectively.
Further, 9' and 87 have means for connecting to other wirings 9 and 8, respectively, and the two-phase pulses 29 and 28 shown in FIG. 10 are supplied. .

In the configuration example shown in FIG. 9, a sampling pulse 52 is applied to the injection source diffusion layer 2, a delayed signal is applied to the input gate electrode 4, and an appropriate DC bias voltage is applied to the electrode 40. , the amount of injected charge is sampled by the potential equirepresion method explained in FIGS. 6 to 8. Such sampling is performed at twice the frequency of the pulse groups 28 and 29 for charge transfer, and the amount of injected charge passes directly under the restraining electrode 50,
Control pulses 51 cause it to be moved alternately under electrodes 6 and 7'. These charges are transferred in separate transfer channels consisting of 6, 7...53 and 7', 6'...54, respectively, and are alternately introduced into the floating diffusion layer 13 through the bottom of the output gate electrode 11. be done. Such alternating inflows are such that the final transfer electrodes of each transfer channel are 53, 54;
This can be easily understood from the fact that pulses 28 and 29 having different phases are supplied. The floating diffusion layer 13 is
The reset pulse 64 has the same phase and pulse width as the input sampling pulse 52, and is reset every time the charge is introduced. Through this operation, an output signal voltage 55 is obtained via the resistor 19. From the above explanation, it has become clear that the present invention can be applied to an element having a so-called multi-flex structure, which has a plurality of transfer channels. Although a duplex structure having two transfer channels has been used in the description, it is clear from the description that the present invention can also be applied to a general multi-flex structure. The present invention has been described above in detail by giving examples.

As described in this specification, the present invention enables the simplification of the driving peripheral circuit of the charge transfer element, and the effect thereof is significant. Although an analog shift register was used in the explanation,
The present invention is not limited to this field, but can be widely applied to applications using electrical charge injection, ie, bias charge injection into a photoelectric conversion image sensor.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the operation of a charge-coupled device, where 1 is a charge-coupled device, MOSFETs 12, 13, and 16 are diffusion layers, 4, 6, 7, 10, 11, 14 are electrodes, ,8
, 9, 12, 15, and 17 are wirings, and 19 is a resistor. FIG. 2 shows the pulse waveforms of each part for driving the element in FIG. 1, and 28, 29, 23, and 25 are 8 and 9 in FIG.
, 3, and 15, and 29 is an output signal waveform.

Claims (1)

[Claims] 1. In order to inject an electrically controlled amount of charge into the charge transfer element, a means for supplying a first pulse to the charge injection section and a floating diffusion layer having a hold function provided in the charge detection section are periodically inserted. In a method for driving a charge transfer device, the method includes a means for supplying a second pulse for charging a cell to a constant potential, and a means for supplying a plurality of pulse trains to achieve charge transfer within the device. , wherein the first pulse and the second pulse have the same repetition frequency, the same pulse generation start time, and the same pulse width, or the same repetition frequency and the same pulse generation start time. Driving method of charge transfer device.