JPS599997B2 - shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shift register, and more particularly to a shift register using a charge-coupled device capable of moving signal charges in a thermal nonequilibrium state within a semiconductor substrate by external control means. It is.

An object of the present invention is to provide a shift register that facilitates the design of a shift register having multiple charge transfer paths and a single charge detection means, reduces the chip area, and further reduces the number of pins of a package. It is in. recent years,
With the rapid development of semiconductor integrated circuit technology, charge-coupled devices have been developed and are expected to find application in various fields.

Such application fields include analog shift registers, solid-state imaging devices, and the like. It is known that when applied as a shift register, the shift register must be driven at a clock frequency that is at least twice the highest frequency of the signal passing through it. However, it is known that when a charge-coupled device is driven at a high frequency, the transfer efficiency deteriorates significantly due to signal charges being transferred within a finite time. Furthermore, since the element has a MOS capacitor structure, power consumption in the drive source increases as the drive frequency increases, which is not preferable. In order to eliminate such drawbacks, a plurality of rows of charge coupled devices are arranged in parallel,
A method has been proposed to increase the effective driving frequency by driving with different phases. This method is called the multiflex method, and it is well known that it is also applied to dynamic digital shift registers composed of MOSFETs. When applying the method to charge-coupled devices, the clock pulses to different charge-coupled devices can be swapped to drive them with different phases. However, in the conventionally proposed method, when arranging a number of such elements in parallel that is equal to or more than the number of clock pulse phases, it is impossible to configure the structure by simply replacing the clock pulses, and the phase of the clock pulse group cannot be arranged in parallel. must be phase shifted. This means that the clock drive source, wiring, and chip structure become complicated, which poses a significant problem in designing the shift register. The present invention eliminates such drawbacks and has the advantage that the shift register can be easily designed. The present invention provides a shift register that includes a plurality of charge transfer paths, means for transferring charges in the transfer paths, and a single charge detection means provided at one end of the transfer paths, in which the detection section adjacent to the output gate electrodes and biasing each output gate electrode constituting the transfer path with a different DC voltage, and further adjacent to the output gate electrode and common to the plurality of electrodes constituting the transfer path. By implementing said shift register including means to which pulses are supplied, [-- is easily achieved.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram conceptually showing a plan view of a conventional shift register. For convenience of explanation, the figure shows a case in which two rows of charge transfer elements 1, λ are included. 1t, 1v...
・12, 12'... and 13, 13'... 14,
14t... are charge transfer elements 1, 2, . . . , respectively. are a group of transfer electrodes that make up the terminals 3, 4,
5 and 6.

The transfer element V,2. In order to exchange the drive phases of , a common two-phase drive pulse is applied to 3 and 5 and 4 and 6, respectively. Reference numeral 7 denotes an output gate electrode having means for applying a DC bias, and is provided in common to the pixel elements 1, 1.

Generally, the absolute value of the DC bias voltage value is smaller than the peak value of the two-phase drive pulse. Reference numeral 8 denotes a floating diffusion layer for charge detection, which forms a Pn junction with the semiconductor substrate, and is further supplied with a reset pulse and is periodically activated by a set gate electrode 9 and a diffusion layer 10 reversely biased with DC. It has means for charging to a constant potential.

FIG. 2 is a time chart showing waveforms of various parts when driving the conventional shift register shown in FIG. In the same figure, 21, 22, and 23 are terminals 3 and 5, and terminal 4, respectively.
and 6 are the voltage waveforms applied to the reset gate electrode 9. Reference numeral 24 represents a potential change in the floating diffusion layer 8, which is generally impedance-converted and amplified by a MOSPET or electronic circuit provided within the same semiconductor substrate, and then detected outside the substrate.

At time TO, t2 shown in the figure, the reset pad 3
Since the pulse 23 is applied to the electrode 9, a channel is formed on the substrate surface below 9, and the potential of 8 becomes equal to the potential of 10. The relevant time T. In the charge transfer element T, 2. The regions where signal charges are localized are below 1V and 13', respectively, and at time T, they are 12' and 14', respectively.
Also, the time T. , t, the reset pulse 23
Since is 0 volts, the channel disappears and region 8 is electrically isolated from region 9. Next, at time t1, the pulse 21 becomes 0 volts, so the time T. The signal charges existing under 13' pass under the output gate electrode 7 and flow into the region 8, where part or all of the charged charges are discharged and the potential is reduced. Note that the signal charge of 1 at that time moves from 11 to below 12'. Next, at time T, the pulse 22 becomes 0 volts, so at time T2
The signal charges localized below 12' pass below 7 and flow into region 8. According to this operation, the signal charges from 1 and λ alternately flow into the single floating diffusion layer 8, so that the potential change in the region becomes as shown in the waveform 24. 1st
In the conventional shift register shown in Fig. 2 and Fig. 2, multiflex operation is achieved without any problems, but the chip surface area becomes large because the wiring for charge-coupled devices 1 and 2 is placed on both sides of the devices. Additionally, there is a drawback that the number of pins on the package increases. Furthermore, in the conventional method, the number of charge-coupled devices arranged in parallel needs to be equal to the number of drive phases. In other words, in the structure shown in Figure 1, if you want to double the number of charge-coupled devices, use a waveform whose phase is shifted by 90 elements from 21 and 22 to the pulse waveforms supplied to the third and fourth devices. Must be. It is clear that such a construction method would require the addition of two more clock drivers for pulse generation, which would complicate the device. It is clear that this drawback is caused by the fact that the only time the signal charge flows out from the charge-coupled device is the fall time of the clock pulses 21, 22. On the other hand, the principle of the present invention, which will be explained next, is to detect signal charges at both the rising and falling times of the clock pulse. Therefore, in the present invention, it is possible to arrange charge coupled devices in parallel in a number greater than the number of clock pulse phases, and it is also easy to reduce the chip area and the number of package pins. FIG. 3 is a diagram conceptually showing a plan view of a shift register which is an embodiment of the present invention.

In the same figure, 3'', 3-2 are charge transfer elements, 41, 4
V..., 42,42t... and 43,43t...,
44, 44', . . . are charge-coupled devices 1 unit, 1 unit, respectively.
2, and are connected to terminals 33, 34, 35, and 36, respectively, via wiring. Further, a common two-phase drive pulse is applied to 33 and 35, and 34 and 36, respectively. 8, 9, and 10 are the same components as in FIG.

37 and 37' are output gate electrodes of L.

FIG. 4 is a time chart of waveforms of various parts to explain the embodiment shown in FIG. In this figure, the same numbers as in FIG. 2 indicate the same components. In the same figure, 52 is the terminal 34
, 36, and 47, 47' indicate the magnitude of the DC bias value applied to 37, 37', respectively. Further, 54 is a voltage waveform in region 8 in FIG. FIG. 5 is a diagram for explaining the operation of FIGS. 3 and 4, and FIG. 5A and 5b are charge transfer elements 1, . . . , respectively. A cross-sectional view of 1u is conceptually shown. In the same figure, 41' to 4
In order to indicate that the device is of a two-phase drive type, the cross-sectional view of the electrode 4' is illustrated as if a difference is provided.
In addition, c-f in the same figure represent the times 1t0-T3 shown in Fig. 4.
FIG. 3 is a potential distribution diagram corresponding to FIG. g-j in the figure is time T shown in FIG. 3 is a potential distribution diagram corresponding to b in the same figure at each of T3. Time T shown in FIG. , t2, the reset pulse 23 causes
The floating diffusion layer 8 is charged to a reverse bias voltage value of 101 (see FIG. 5C, e, g, i). At other times, 8 is isolated from 10 because pulse 23 is 0 volts. At time TO, the pulse 52 has a high voltage value,
Furthermore, since the applied voltage 47 of 37 has a smaller absolute value than the voltage value, the signal charge of the charge coupled device 31 is transferred to the electrode 42.
' (Fig. 5c). On the other hand, the applied voltage of 3V 4
Since the absolute value of V is larger than the pulse voltage value of 52, the signal charge of the charge-coupled device 32 does not exist at 44', but passes under 37' and is guided to region 8 (Fig. 5). g). At time T, the pulse 52 becomes 0 volts, so at time T. The signal charge localized below 42' passes below 37 and is guided to region 8 (FIG. 5d). At this time, the signal charge of the charge-coupled device 32 exists below 43' (FIG. 5h). When the pulse 52 becomes a high voltage at time T3, the signal charge moves from below 43' to below 44', and further passes below 37' to be guided to region 8 (FIG. 5j). Following such operation, the voltage in region 8 becomes 54. That is, in this example, the same pulse is applied to the electrodes adjacent to the output gate electrode, and the charge transfer element transfers from one charge transfer element at the rise time of the pulse, and from the other charge transfer element at the fall time of the pulse. Signal charges will be detected from the element. In such a structure, since the same pulse is applied to the opposing electrodes of the two charge-coupled devices, it is possible to route wiring only on one side of the charge-coupled device array, reducing the chip area or increasing the size of the package. Significant advantages arise, such as a reduction in the number of pins, and chip design becomes easier.

Further, it can be easily inferred that the structure shown in FIG. 3, which is an embodiment of the present invention, is further increased by two columns and the same diffusion layer 8 is shared for the third and fourth charge transfer elements. In the case of such a four-row structure, the electrodes adjacent to the output gate electrodes of the third and fourth charge-coupled devices are applied with a waveform having a phase difference of 180 poles from the pulses applied to 42' and 44', that is, 4V. ，
It is clear that it is sufficient to apply the waveform applied to 43' and further set the duty of pulse 52 to 50% or more. In other words, even if a two-phase drive charge-coupled device is used, a shift register consisting of four columns of charge transfer paths can be realized with two clock drivers. . , This shows that, in general, a shift register consisting of (2n) charge transfer paths can be constructed using n-phase charge-coupled devices and n clock drivers. As explained above, it has been revealed that the present invention has great advantages when designing a shift register using a charge-coupled device, and the effects of the present invention are significant.

Although a two-phase drive charge-coupled device was used in the explanation, it is clear that single-phase to multi-phase devices may also be used, and furthermore, various application fields using the device, such as It is clear from the description of this specification that the present invention is widely applicable to imaging devices, digital memories, digital filters, and the like.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional shift register.
is a charge coupled device, 11,1V,...12,12'-...
・,13,13'...,14,14',...,7,
9 is an electrode, 8 and 10 are diffusion layers, and 3, 4, 5, and 6 are terminals. FIG. 2 is a time chart of waveforms of various parts to explain the operation of FIG. 1. FIG. 3 shows a shift register showing an embodiment of the present invention, in which 3 units and 1 units are charge coupled devices, 41 and 4 units are charge coupled devices, and 41 and 4 units are charge coupled devices.
1″...42,42t...,43,43/...,4
4, 44t..., 37, 37' are electrodes, 33, 34, 3
5 and 36 are terminals.

Claims (1)

[Claims] 1. In a shift register having a plurality of charge transfer paths, means for transferring charges in the transfer paths, and a single charge detection means provided at one end of the transfer paths, adjacent to the detection section, Each output gate electrode constituting the transfer path includes means for biasing with a different DC voltage, and a common pulse is supplied to a plurality of electrodes adjacent to the output gate electrode constituting the transfer path. A shift register characterized in that it includes means for