JPS6010338B2 - Multiple virtual memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a segment table origin stack (
In an information processing system using a multiple virtual memory system, which has an STO stack (hereinafter referred to as an STO stack) and performs logical/real address translation in different virtual spaces using a single address translation buffer (so-called TLB), TLB is used. (hereinafter referred to as TLB/DAT) and the case where address translation is performed using segment tables and page tables on the main storage device without using TLB (hereinafter referred to as table DAT). The switching is controlled by the value of the space ID in the STO stack.

Normally, in order to minimize the address conversion time, the TL is
Translation by B is attempted, and if the corresponding real address does not exist in TLB, table DAT is performed.

However, when the TLB breaks down or when you want to temporarily disconnect the TLB for maintenance, testing, etc., you can actively disconnect the TLB.
There are cases where you do not want to use . Conventional TLB like this
To disconnect, either set up a special mode or use T.
DA as usual while always invalidating the entry in LB (that is, always making it a TLB fault)
I was thinking of doing T. The former method requires an extra mode control bit, and the latter method has drawbacks such as requiring processing to keep the TLB invalid and requiring a TLB access time. The purpose of the present application is to eliminate such drawbacks, and to switch between TLB/DAT and table DAT based on the value of the space ID in the STO stack.

This will be explained in detail below with reference to the drawings. In the figure, 1 is a logical address register, 2 is an STO stack, 21 is a segment index storage section, 22 is a space ID storage section, 3 is a coincidence detector,
4 is register, 5 is spatial ID generator, 6 is TLB, 61
1 is an index storage section, 62 is a real address storage section, 7 is a coincidence detector, 8 is a register, 9 is an ID detector provided according to the present invention, and 10 is a table DAT control section.

The STO stack 2 is indexed using a part of the segment address part of the logical address, and if a matching index exists, the corresponding space ID is set in the register 4.

TLB6 is indexed by part of the page address part of the logical address (and part of the segment address may be hashed), but it also contains the space ID as part of the index, and it is linked to the space ID in register 4. TLB conditional on match
Determine hit no fault. When a TLB hit occurs, the corresponding real page address is set in register 8 from 62. , and table DA when there is a TLB fault.
The T control section is activated and table DAT is performed. Up to this point, the method is similar to the conventional method, and for more details, please refer to Japanese Patent Publication No. 25774. In the present invention, the spatial m output to the ladder register 4 is monitored by the detector 9, and if the value is, for example, all "0" (conventionally, it was an invalid value), the TLB access is not performed and the table DAT is immediately accessed. The control unit 10 is activated to perform table DAT.

As described above, in the present invention, by simply providing a simple all-0 detector, the TLB can be easily disconnected even if a special mode is provided or the TLB is subjected to special processing. In addition, to set the ID value to the STO stack 2, generally, a counter is provided in the m generator 5, and the value is set in the rust using a new space, and the count value is updated. .

When setting all "0"s as in the present invention, the counter output may be inhibited by a gate. Also TL
When B fails or during maintenance, all space IDs in the STO stack are set to "0" in order to perform table DAT for all virtual spaces, but in some cases for diagnostic purposes, table DAT is performed only for specific virtual spaces. For other virtual spaces, TLB/
It is also possible to have DAT performed.

[Brief explanation of the drawing]

The figure is a block diagram of an embodiment of the present invention, in which 1 is a logical address register, 2 is an STO stack, 6 is a TLB, 9 is a space m detector according to the present invention, and 10 is a table DAT control section.

Claims (1)

[Claims] 1. In a multiple virtual memory information processing system having a segment table origin stack that defines a virtual space ID, when the virtual space ID has a specific value, the segment table in main memory is immediately updated without using an address translation buffer. A multiple virtual memory control device characterized in that a real address is obtained by performing address conversion using a table and a page table.