JPS6017263B2 - timing extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing extraction circuit that extracts timing from the jitter distribution of an input signal, and particularly to a timing extraction circuit when the jitter distribution has two peaks.

There are two types of circuits that extract timing from the jitter distribution of an input signal: analog systems that use LC tank circuits or cavity resonators, and digital systems that use phase comparators, doji conversion circuits, etc. Both are fairly widely used. However, these methods have no problem when the jitter distribution of the input signal has a single peak, but when the jitter distribution of the output signal has two peaks, as will be explained later using the drawings, the jitter distribution of the output signal However, there are two peaks, and the timing cannot be extracted accurately. Therefore, an object of the present invention is to provide a timing extraction circuit that can perform accurate timing extraction even when the jitter distribution of an input signal has two peaks.

According to the present invention, there is provided a variable frequency oscillator that operates in response to a control signal for increasing and decreasing the oscillation frequency, and a phase difference between the output signal of the variable frequency oscillator and an input signal from the outside that is proportional to the phase difference. a phase comparator that outputs a phase difference output, a quantization unit that quantizes the phase difference output, and an integration unit that integrates the output signal of the doji conversion unit and outputs the control signal; In a circuit adapted to extract a timing signal from a signal, when the jitter distribution of the external input signal as the output signal of the quantization means has two peaks at positions o clocks apart. Express the magnitude of the phase difference output as N on the coordinates with the midpoint of the two peaks as 0, and determine whether N is in the range from -No to 0 or from 0 to No. The first signal g, the second signal h, the third signal j, or the fourth signal depends on whether it is less than No or more than No.
When the first signal exceeds the second signal, the integrating means generates a fifth signal k, and when the first signal becomes smaller than the second signal, the integrating means generates a sixth signal k. a seventh signal m when the sum of the third signal and the fifth signal is greater than the sum of the fourth signal and the sixth signal; and an eighth signal n when the sum of the third signal and the fifth signal is less than the control signal; There is obtained a timing extraction circuit characterized in that it is configured to have an integral function that generates .

Next, a detailed explanation will be given with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a conventional timing extraction circuit.

In the figure, 11 is a phase comparator, 12 is a quantization circuit, 1
3 represents an integrator, and 14 represents a variable frequency oscillator. The input signal a from the outside is compared with the output signal b from the variable frequency oscillator 14 in the phase comparator 11, and the output proportional to the phase difference between both signals is subjected to nonlinear processing in the doji conversion circuit 12, and the output is It is integrated in the integrating circuit 13, and its output controls the oscillation frequency of the variable frequency oscillator 14. This controlled oscillation frequency is the aforementioned output signal b, and is also the output of this timing extraction circuit. Note that signal c represents a clock signal. Next, when this circuit is used, what happens to the jitter distribution of the input signal in the output signal will be explained. Figures 2 and 3 show an example of the jitter distribution of an input signal assumed when there is one peak, and an example of the jitter distribution of an output signal obtained from this input signal using a subordinate timing extraction circuit, respectively. This is a diagram. The jitter distribution shown in Fig. 3 is a desirable form for a timing extraction wax, and the
The diagrams are omitted to indicate that they have sufficiently satisfactory characteristics. However, the situation is different when the jitter distribution of the input signal has two peaks, for example when using a signal obtained by slicing the eye pattern of the received pulse consisting of 1 (-1) and 0 at a certain height. It's coming. That is,
The eye pattern of the bibolar code that is often used in PCM transmission takes the shape shown in Figure 3A, for example, and the binary signal obtained by inputting this signal to a level comparator whose reference is the level indicated by the broken line is When operating a digital phase locked loop circuit (DPLL) using the rising point (black V point) whose position is shown in Figure 3A b as an input signal, the DPLL input signal obtained by this method can be seen from Figure 3A. As shown, there are two rising phases, and the input jitter distribution has two peaks.

Figures 4 and 5 show an example of the jitter distribution of the input signal assumed when there are two peaks, and an example of the jitter distribution of the output signal obtained from this input signal using the subordinate timing extraction circuit. Each is expressed as follows.

In the output signal jitter distribution with two peaks obtained in this way, the timing will be shifted to the one that appears more frequently among the two peaks, making it impossible to obtain accurate characteristics. o represents the interval between two peaks as a phase difference angle, and usually represents 20% of 3600, or 7. Fig. 6 is a block diagram showing the circuit configuration of an embodiment of the present invention. be.

The phase comparator 21 is substantially the same as the conventional circuit shown in FIG. 1, and counts the phase difference between the input signal d and the output e from the variable frequency oscillator 22 using the clock pulse signal c, and calculates the counted number N. Output as signal f. Quantization circuit 23
is a circuit in which one of the four output signals g, h, i, and i outputs "1" according to the sign and magnitude of the count number N represented by the signal f. FIGS. 7 and 8 are diagrams for explaining the division of the four output signals of the quantization circuit 23 according to the phase difference count number N, and the meaning of the predetermined count number No representing the boundary of this division, respectively. In FIG. 8, No represents the number of clocks that is half the interval between two peaks. /2. Assuming that the interval between two peaks of the fundamental frequency of the input signal is 48 clocks, 9.6 clocks, which is 20% of this number of clocks, corresponds to state o. That is, No is 4.8 clocks. Therefore, from Figures 7 and 8, the count number N is NS - 4.8 -4.8, N≦0,0, N≦4.8,4
．． As 8<N, signals 1, g, h and i become “1”
This means that the output will be . In addition, in Fig. 7, N
The equality sign shown to the right of N may be replaced below the inequality sign to the left of N. Next, the up/down counter 24, which is the first integration circuit, has an overflow value set to 8, and the number Ng of "1" pulses sent from the g signal circuit is "1" pulses sent from the h signal circuit. 1” number of pulses N
If the number is 8 more than h, the pulse signal “1” is indicated by k.
On the other hand, when Ng becomes 8 less than Nh, a pulse signal "1" is outputted.

The up/down counter 25, which is the second integrating circuit, has an overflow value set to 4, and the OR circuit 26
If the number of pulses from the OR circuit 27 is 4 more than the number of pulses from the OR circuit 27, it outputs a pulse signal "1" indicated by m,
Conversely, if the former is less than the latter by 4, a pulse signal "1" indicated by n is output. To simply state the above, when only signals g and h are considered, when the difference between them becomes 32, signal m or n outputs "1", and when only signals i and i are considered, both When the difference between is 4, the signal m or n becomes “
1". Therefore, if the number of pulses of signals m and n is Nm and Nn, respectively, then the count number of signal f is N
Nm that occurs when is smaller than -No or larger than No
(or Nn) to the phase difference count number N is N
Nm (or Nn
) is eight times the ratio of phase difference count number N. Therefore, if we name the part 28 surrounded by the broken line as the control signal generation circuit, the change that the control signals m and n output from this circuit give to the oscillation frequency of the variable frequency oscillator is determined by the number of clocks of the phase difference output f. When it is smaller than No, it is set to 1, and when it is larger than No, it is set to 8. Assuming that the phase of the oscillation frequency has advanced slightly, in the case of the peak on the left side of the figure, the number N of phase difference pulses is between -No and 0, and in the case of the peak on the right side, the number N of phase difference pulses is No. It's in a bigger place. Therefore, in such a case, if both peaks appear equally, the correction of the oscillation frequency shift will be as follows:
The frequency at which control is performed to further delay the phase is 8, and it approaches 0 at a speed of 7, which is the difference between the two, and even if the ratio of appearance of both peaks is not equal, it is 8:1. If it is smaller, the oscillation frequency will gradually decrease to 0.
will come close to. Therefore, according to this circuit, accurate timing extraction can be performed even if the jitter distribution of the input signal has two peaks. Although the overflow values of the two integrating circuits are set to 8 and 4 in the above, it goes without saying that the overflow values are not limited to this.

For example, if the pulses of the input signal tend to be biased toward either "1" or "0", the overflow value of the first up/down counter may be further increased. FIG. 9 shows the magnitude of the output of the integrator in such a case, and shows that the output changes stepwise with the earth No. as a boundary.

Note that in this case, a voltage controlled oscillator is used as the variable frequency oscillator. In the above embodiment, the quantization circuit 23 and the integration circuits 24 and 25 having four outputs were used as the control signal generation circuit, but instead of these, when the number of phase difference pulses N is smaller than No, fewer pulses are used. It is also possible to generate a positive or negative signal with a number of pulses, and when it is larger than No, generate a positive or negative signal with a large number of pulses, and use a single integrator.

In that case, the output of the single integrator changes stepwise as the soil number. The change is the same as the change in the first embodiment shown in FIG.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the configuration of a subordinate timing extraction circuit, Fig. 2 is a diagram showing an example of the jitter distribution of the input signal assumed when there is one peak, and Fig. 3 is a diagram showing an example of the jitter distribution of the input signal assumed when there is one peak. Figure 3A is a diagram showing an example of the jitter distribution of the output signal obtained from the input signal having the jitter distribution shown in the figure using the subordinate timing extraction circuit, and Figure 3A explains the case where the jitter of the input signal has two peaks. Figure 4 is a diagram showing an example of the jitter distribution of the input signal assumed when there are two peaks.
FIG. 5 is a diagram showing an example of the jitter distribution of an output signal obtained using a conventional timing extraction circuit from an input signal having the jitter distribution shown in FIG. 4, and FIG. 6 is a circuit configuration of an embodiment of the present invention. Figure 7 shows the 6th block diagram.
Figure 8 shows the meaning of the predetermined number No representing the boundary of the division shown in Figure 7. An explanatory diagram, FIG. 9, is a diagram showing the magnitude of the output of the integrator in the first and second embodiments of the present invention. Explanation of symbols: 21 is a phase comparator, 22 is a variable frequency oscillator, 23 is a doji conversion circuit, 24 is an up/down counter with an overflow value of 8, 25 is an up/down counter with an overflow value of 4, 26 and 27 are OR circuits, 28 is the control signal generation circuit, N' is the phase difference count number, and No is half the number of counts when the peak-to-peak of the jitter distribution of the input signal is expressed. Figure 1 Figure 2 Figure 3 Figure 3 A Figure Dance Figure 5 Figure 6 and Figure 7 Garden Figure 8 Figure 9

Claims (1)

[Claims] 1. A variable frequency oscillator that operates in response to a control signal for increasing or decreasing the oscillation frequency, and a phase difference output proportional to the phase difference by comparing the phase of the output signal of this variable frequency oscillator and the phase of an external input signal. a phase comparator that outputs a signal, a quantization means that quantizes the phase difference output, and an integration means that integrates the output signal of the quantization means and outputs the control signal, and extracts a timing signal from the input signal. In the circuit for extracting the jitter distribution of the external input signal, the quantization means outputs a jitter distribution of 2N.
When there are two peaks at positions separated by _0 clocks, the magnitude of the phase difference output is expressed as N on the coordinates where the midpoint of the two peaks is 0, and N is -N_0.
Is it in the range from 0 to 0, or is it in the range from 0 to N_0?
The first according to whether it is less than N_0 or more than N_0.
The integrating means is configured to have a function of emitting a signal g, a second signal h, a third signal i, or a fourth signal j, and the integrating means a function of emitting a fifth signal k when the number increases and a sixth signal l when the number decreases; and the sum of the third signal and the fifth signal is greater than the sum of the fourth signal and the sixth signal. A timing extraction circuit characterized in that it is configured to have an integration function of emitting a seventh signal m as the control signal when the number decreases, and an eighth signal n as the control signal when the number decreases.