JPS601799B2 - Reverberation adding device - Google Patents
Reverberation adding deviceInfo
- Publication number
- JPS601799B2 JPS601799B2 JP52128919A JP12891977A JPS601799B2 JP S601799 B2 JPS601799 B2 JP S601799B2 JP 52128919 A JP52128919 A JP 52128919A JP 12891977 A JP12891977 A JP 12891977A JP S601799 B2 JPS601799 B2 JP S601799B2
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- Prior art keywords
- signal
- circuit
- output
- voltage
- delay
- Prior art date
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- Expired
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- 230000010355 oscillation Effects 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000003786 synthesis reaction Methods 0.000 claims 1
- 230000002194 synthesizing effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 description 6
- 238000009499 grossing Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 230000001755 vocal effect Effects 0.000 description 1
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Description
【発明の詳細な説明】
本発明は残響付加装置に関し、特にステレオ及びモノラ
ル音声信号に残響音を付加することの可能な残響付加装
置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reverberation adding device, and more particularly to a reverberation adding device capable of adding reverberation to stereo and monaural audio signals.
ステレオセット等の音響再生機器において、ある種のプ
ログラムソース再生時に所定の残響を付加して聴感上好
ましい再生音を得ているが、か)る残響の付加としては
、得られた残響成分を可変抵抗器等を用いてもとの信号
と好みのレベルでミキシングする方法が一般的である。In sound reproduction equipment such as stereo sets, when playing certain program sources, a predetermined reverberation is added to obtain a reproduction sound that is pleasing to the ear. A common method is to mix the signal with the original signal at a desired level using a resistor or the like.
しかしながら、この様な方法では、もとの信号内容にか
)わらず一定レベルの残響音が付加されることになるた
め、例えば入力信がボーカル等の場合には、当該入力信
号自体にすでに残響音が付加されている関係上、更に残
響を付加することになり聡感上むしろ不自然な感じを与
えることになり好ましいものではない。また、AM放送
をはじめモノラルあるいはセパレーションの小さなプロ
グラムソースの場合は、残響成分付加により好感のもて
る再生音を得ることができるが、先述した如く残響成分
のミキシングはユーザが手動によりレベルを調整して聴
感上より良い再生条件を作り出す必要があり、ユーザ側
の当該調整のわずらわしさを伴う欠点がある。However, with this method, a constant level of reverberation is added regardless of the original signal content, so for example, if the input signal is a vocal, etc., the input signal itself may already have reverberation. Since sound is added, reverberation is added, which gives an unnatural feeling, which is not desirable. Furthermore, in the case of monaural or program sources with small separation, such as AM broadcasting, it is possible to obtain a pleasant playback sound by adding reverberation components, but as mentioned earlier, the mixing of reverberation components requires the user to manually adjust the level. Therefore, it is necessary to create playback conditions that are better for audibility, and there is a drawback that the adjustment is troublesome on the user's side.
本発明は上述の欠点に鑑みなされたものであり従って入
力信号の内容に応じて付加する残響音の遅延量を自動的
に制御することのできる残響付加装置を提供することを
目的としている。以下、本発明を添加図面を用いて詳細
に説明する。The present invention has been made in view of the above-mentioned drawbacks, and it is therefore an object of the present invention to provide a reverberation adding device that can automatically control the amount of delay of reverberant sound to be added depending on the content of an input signal. Hereinafter, the present invention will be explained in detail using additional drawings.
図は本発明の実施例を示すブロック図であり、図におい
てプログラムソースであるステレオ信号の左右チャンネ
ル信号(以下L,R信号と略す)がそれぞれ入力端子1
及び2に印加されて、共に加算回路3及び減算回路4へ
入力される。The figure is a block diagram showing an embodiment of the present invention. In the figure, left and right channel signals (hereinafter abbreviated as L and R signals) of a stereo signal, which is a program source, are input to input terminals 1 and 11, respectively.
and 2, and both are input to the addition circuit 3 and the subtraction circuit 4.
従って加算回路3の出力は(L+R)信号となり、減算
回路4の出力は(L−R)信号となる。当該両信号はそ
れぞれ整流回路5,6及び所定時定数を有する積分回路
7,8に印加されて、(L+R)及び(L−R)信号に
応じた直流レベルに変換される。これ等直流信号は共に
直流減算回路9に入力されて両者の差に相当する電圧が
当該減算回路9及び次段の平滑回路10を介して出力さ
れることになる。平滑回路10の出力である差信号は一
入力のゲート回路16へ入力されると共に、反転回路1
4により反転されて同じく一入力ゲート回路15へ入力
される。一方、(L−R)信号に応じた直流レベルを有
する電圧すなわち積分回路8の出力は電圧比較回路11
に入力されて所定基準電圧と比較される。Therefore, the output of the addition circuit 3 becomes a (L+R) signal, and the output of the subtraction circuit 4 becomes a (L-R) signal. These two signals are applied to rectifier circuits 5 and 6 and integration circuits 7 and 8 having predetermined time constants, respectively, and are converted into DC levels according to the (L+R) and (LR) signals. These DC signals are both input to the DC subtraction circuit 9, and a voltage corresponding to the difference between the two is outputted via the subtraction circuit 9 and the next stage smoothing circuit 10. The difference signal that is the output of the smoothing circuit 10 is input to the one-input gate circuit 16, and is also input to the inverting circuit 1.
4 and is similarly input to the one-input gate circuit 15. On the other hand, the voltage having a DC level corresponding to the (LR) signal, that is, the output of the integrating circuit 8 is output to the voltage comparator circuit 11.
and is compared with a predetermined reference voltage.
この比較回路11の比較出力信号は直接ゲート16の開
閉動作を制御する信号として用いられ、また比較回路1
1の出力は反転回路13により反転されてゲート15の
開閉動作を制御する。ゲート回路15,16の出力は共
に電圧制御発振回路17の電圧制御入力端子に接続され
て当該ゲート回路から出力される直流電圧レベルに応じ
てその発振周波数が制御される。発振回路17の出力信
号はアナログシフトレジスタで構成される例えばBBD
等の遅延回路18,19のシフトクロツク信号となり、
L,R入力信号はそれぞれ遅延回路18,19によりそ
のシフトクロツク信号周波数に応じて遅延される。そし
て出力増幅回路20,21によって所定レベルにそれぞ
れ増幅及び低インピーダンス化されて出力端子22及び
23に出力される。尚、遅延回路18,19の各出力は
それぞれ所定の減衰回路24,25を介してその各入力
に帰還され合成されて適当な残響が付加されたL,R信
号が得られる。上述した回路の動作原理及び効果を以下
に述べる。The comparison output signal of the comparison circuit 11 is directly used as a signal to control the opening/closing operation of the gate 16.
1 is inverted by an inverting circuit 13 to control the opening/closing operation of the gate 15. The outputs of the gate circuits 15 and 16 are both connected to a voltage control input terminal of a voltage controlled oscillation circuit 17, and the oscillation frequency thereof is controlled according to the DC voltage level output from the gate circuit. The output signal of the oscillation circuit 17 is composed of an analog shift register, for example, BBD.
It becomes a shift clock signal for delay circuits 18 and 19 such as
The L and R input signals are delayed by delay circuits 18 and 19, respectively, according to their shift clock signal frequencies. The output amplification circuits 20 and 21 amplify the signals to a predetermined level and lower the impedance, respectively, and output the signals to output terminals 22 and 23. The outputs of the delay circuits 18 and 19 are fed back to their respective inputs via predetermined attenuation circuits 24 and 25, respectively, and are combined to obtain L and R signals to which appropriate reverberation has been added. The operating principle and effects of the above-mentioned circuit will be described below.
入力信号をステレオ信号とするとL,R信号は下記の如
く表わすことができる。When the input signal is a stereo signal, the L and R signals can be expressed as follows.
こ)で1及びrはステレオ再生時においてそれぞれ左及
び右に定位する音像成分であり、cは虚像として左右中
央に定位する音像成分である。In this), 1 and r are sound image components localized to the left and right, respectively, during stereo reproduction, and c is a sound image component localized to the left and right center as a virtual image.
従って加算及び減算回路3及び4の出力S^及びS3は
次式で示される。よってS^及びSSは整流回路5,6
及び積分回路7,8により共に直流電圧S^。Therefore, the outputs S^ and S3 of the addition and subtraction circuits 3 and 4 are expressed by the following equations. Therefore, S^ and SS are rectifier circuits 5 and 6
and DC voltage S^ by integral circuits 7 and 8.
及びS肌となって次式で示される。こ)で−−一は直流
レベル変換後の平均値を示すものとする(以下同じ)。and S skin, which is expressed by the following equation. In this), -1 indicates the average value after DC level conversion (the same applies below).
一方、1及びrは全く別個のランダム信号であるから1
十rニーーrがなりたつと考えられる。On the other hand, since 1 and r are completely separate random signals, 1
It is thought that 10 r nee r becomes.
よってS^。及びSS。の差電圧すなわち平滑回路10
の出力は次式で表わすことができる。S^。Therefore, S^. and S.S. , that is, the smoothing circuit 10
The output of can be expressed as: S^.
−SS。ニc ”””…【4’上記{4}
式から分かるように平滑回路10の出力すなわちゲート
回路15及び16の入力には中央定位成分cに対応した
電圧レベルが得られる。換言すれば入力信号中のc成分
が大きい場合はcのレベルも上昇するからゲート回路1
6の入力は増加し、他方ゲート回路15の入力は減少す
ることになる。こ)で入力端子1及び2に印加されるプ
ログラムソースがモノラル信号の場合には、L=R=松
/2と表わすことができるから、前記したステレオ信号
の場合と同様にしてS^。,SS。及びS^。−SS。
は次式となる。S^D=SS。-SS. nik ”””…[4' Above {4}
As can be seen from the equation, a voltage level corresponding to the center localization component c is obtained at the output of the smoothing circuit 10, that is, at the input of the gate circuits 15 and 16. In other words, if the c component in the input signal is large, the level of c also increases, so gate circuit 1
The input of gate circuit 15 will increase, while the input of gate circuit 15 will decrease. In this case, if the program source applied to input terminals 1 and 2 is a monaural signal, it can be expressed as L=R=pine/2, so S^ can be expressed in the same manner as in the case of the stereo signal described above. , SS. and S^. -SS.
is the following formula. S^D=SS.
ニ次 (>0)SS。Secondary (>0) SS.
=L−R二0 ...・・・(5)S^。=L
+Rニ父 (>0)上記‘3}及び{5)式のSSDよ
り入力信号のモノラルステレオの別を直流レベルにて判
断することが可能であることは明白であるから、今電圧
比較器11の基準電圧発生器12の基準電圧をVRとし
て1一r>VR>0なる値に選定し、SS。=L-R20. .. .. ...(5)S^. =L
+R (>0) Since it is clear that it is possible to determine whether the input signal is monaural or stereo based on the SSD in equations '3} and {5) above, the voltage comparator 11 The reference voltage of the reference voltage generator 12 is set as VR, and a value of 1r>VR>0 is selected.
>VRの時に比較回転11の出力が“H”(高)レベル
、SS。<VRの時に“L”(低)レベルとなるように
設計し、ゲート回路15,16が制御入力“H”レベル
の場合に開すなわち導適状態になるようにすれ‘よ、電
圧制御発振回路17の制御電圧に関して次の2つの場合
が存在することになる。先ずSS。>When in VR, the output of comparison rotation 11 is “H” (high) level, SS. <The voltage controlled oscillation circuit should be designed so that it is at the "L" (low) level during VR, and the gate circuits 15 and 16 are open or in a conductive state when the control input is at the "H" level. The following two cases will exist regarding the 17 control voltages. First of all, SS.
<VRの場合すなわち入力信号がモノラルの場合には、
比較回路11の出力“L”レベルとなり、よって反転回
路13を介してゲート回路15が導通し、c成分に反比
例した電圧が電圧制御発振回路17の制御電圧となる。
次にSS。<In the case of VR, that is, if the input signal is monaural,
The output of the comparator circuit 11 becomes "L" level, the gate circuit 15 becomes conductive via the inversion circuit 13, and a voltage inversely proportional to the c component becomes the control voltage of the voltage controlled oscillation circuit 17.
Next is SS.
>VRすなわちステレオの場合には比較回路11の出力
が“H’’レベルとなり、ゲート回路16が導通してス
テレオ中のc成分に比例した直流電圧が電圧制御発振回
路17の制御電圧となる。こ)で、電圧制御発振回路1
7の電圧一周波数変換係数をKo,ゲート回路15,1
6からの制御電圧をVC発振周波数をfoとし、遅延回
路18,19のシフトレジスタ段をNとすれば、遅延回
路の遅延時間7dは次式で示される。>VR, that is, in the case of stereo, the output of the comparator circuit 11 becomes "H'' level, the gate circuit 16 becomes conductive, and a DC voltage proportional to the c component in stereo becomes the control voltage of the voltage controlled oscillation circuit 17. ), the voltage controlled oscillation circuit 1
The voltage-frequency conversion coefficient of 7 is Ko, gate circuit 15,1
If the VC oscillation frequency of the control voltage from 6 is fo, and the shift register stage of the delay circuits 18 and 19 is N, the delay time 7d of the delay circuit is expressed by the following equation.
\ ?d=希=赤C I‐‐‐‐・‐.側別ち制御電圧
V。\? d=Rare=Red CI----.-. Side-separated control voltage V.
に対し遅延時間7dは反比例することがわかる。以上の
関係から入力信号がモノラルソースの場合を考えると、
c成分が上昇則ちL,R信号が同一で当該同一信号レベ
ルが上昇することによりVCが減少し、従って遅延回路
18,19の遅延時間7dは増大することになる。It can be seen that the delay time 7d is inversely proportional to the delay time 7d. Considering the above relationship, if the input signal is a monaural source,
When the c component increases, that is, when the L and R signals are the same and the same signal level increases, VC decreases, and therefore the delay time 7d of the delay circuits 18 and 19 increases.
すなわちモノラルソースの場合は入力が大になる程信号
の遅延時間が増大する。他方、入力信号がステレオソー
スの場合を考えると、ステレオ信号のc成分が増大する
と制御電圧VCも増大しよって遅延回路18,19の遅
延時間7dが減少する。In other words, in the case of a monaural source, the signal delay time increases as the input becomes larger. On the other hand, considering the case where the input signal is a stereo source, when the c component of the stereo signal increases, the control voltage VC also increases, and the delay time 7d of the delay circuits 18 and 19 decreases.
即ちc成分レベルが大の場合には信号の遅延時間は少と
なる様動作する。即ちプログラムソース中すでに多くの
残響が付加されている場合には、c成分のレベルが大で
あるから本回路による遅延時間は短くなり好都合となっ
ている。以上詳述した如く本発明によれば、モノラルソ
ースのような拡がりの少ないプログラムソースに対して
は入力レベルに比例して長い遅延時間が得られ、よって
残響効果が自然なものが得られ、一方ステレオプログラ
ムソースでは、あらかじめ含まれる残響に対応するc成
分の大小に従って遅延時間を短長にそれぞれ制御して自
動的にかつ効果的に自然な残響付加が達成される。That is, when the c component level is high, the signal delay time is operated to be short. That is, when a large amount of reverberation has already been added to the program source, the level of the c component is high, so the delay time by this circuit is shortened, which is advantageous. As detailed above, according to the present invention, for a program source with little spread, such as a monaural source, a long delay time can be obtained in proportion to the input level, and therefore a natural reverberation effect can be obtained. In a stereo program source, natural reverberation can be automatically and effectively added by controlling the delay time to be short or long according to the magnitude of the c component corresponding to the pre-included reverberation.
このように本発明の装置ではプログラムソースの状態に
合致した残響付加が可能となり、特にモノラルソースの
場合にはその入力レベルに応じて自動的に残響が制御さ
れるので蟻感上好ましいものとなる。またマイクミキシ
ング等の付加入力の場合にもその昔量に応じて残響付加
による効果度を変化させることができ好都合であり、更
に遅延回路18,19を用いた遅延時間の制御に限らず
、他の音響効果の付加例えば位相変調等への応用へも発
展させることが可能である。尚上述の実施例においては
、L及びRチャンネルそれぞれに対し遅延回路を用いた
が、L,Rチャンネルを合成(例えば加算若しくは減算
)して当該合成信号に対して1個の遅延回路を設けても
よい。In this way, the device of the present invention makes it possible to add reverberation that matches the state of the program source, and in particular, in the case of a monaural source, the reverberation is automatically controlled according to the input level, which is preferable from a user's perspective. . Furthermore, in the case of additional inputs such as microphone mixing, it is convenient to be able to change the degree of effect of adding reverberation depending on the amount of input. It is also possible to develop applications such as adding acoustic effects such as phase modulation. In the above embodiment, a delay circuit was used for each of the L and R channels, but it is also possible to combine the L and R channels (for example, by addition or subtraction) and provide one delay circuit for the combined signal. Good too.
更には遅延回路18,19に周波数特性をもたせてもよ
くまたそれぞれ異なる周波数特性としてもよい。遅延回
路18,19の出力を減衰回路24,25を介して入力
に帰還して、L,Rチャンネル信号と遅延信号とをそれ
ぞれ合成し残響を含む出力信号を端子22,23に得て
いるが、出力端子22,23の信号を本来のL及びRチ
ャンネル用スピーカとは8Uのスピーカへそれぞれ直接
に導入して残響効果を得ることもできる。Furthermore, the delay circuits 18 and 19 may have frequency characteristics, or may have different frequency characteristics. The outputs of the delay circuits 18 and 19 are fed back to the input via the attenuation circuits 24 and 25, and the L and R channel signals and the delayed signals are synthesized, respectively, and output signals including reverberation are obtained at the terminals 22 and 23. It is also possible to obtain a reverberation effect by directly introducing the signals of the output terminals 22 and 23 to the original L and R channel speakers, respectively, to the 8U speakers.
また、端子22,23の後に加算回路をそれぞれ設けて
、L及びRチャンネル信号と出力端子22,23の出力
信号とを加算合成しても同様な効果が得られる。Furthermore, the same effect can be obtained by providing adder circuits after the terminals 22 and 23, respectively, and adding and combining the L and R channel signals and the output signals of the output terminals 22 and 23.
図は本発明の実施例を示すブロック図である。 The figure is a block diagram showing an embodiment of the present invention.
Claims (1)
有する直流信号を発生する第1の信号変換手段と、前記
第1及び第2チヤンネル信号の差に応じたレベルを有す
る直流信号を発生する第2の信号変換手段と、前記第1
及び第2の信号変換手段からの直流信号の差に応じた信
号を発生する差信号発生手段と、前記第2の信号変換手
段からの直流信号と所定基準電圧とを比較する比較手段
と、前記比較手段の出力により制御され前記差信号発生
手段の出力を入力とする第1のゲート回路と、前記比較
手段の反転出力により制御され前記差信号発生手段の反
転出力を入力とする第2のゲート回路と、前記第1及び
第2のゲート回路の出力により発振周波数が制御される
電圧制御発振回路と、前記電圧制御発振回路の出力信号
により遅延時間が制御されつつ前記第1及び第2チヤン
ネル信号を遅延させる遅延手段と、前記遅延手段の出力
と前記第1及び第2チヤンネル信号とを合成する合成手
段とを含むことを特徴とする残響付加装置。 2 前記第1の信号変換手段は前記第1及び第2チヤン
ネル信号の和を出力する加算回路と、前記加算回路の出
力を整流する第1整流回路と、前記第1整流回路の出力
を積分する第1積分回路とを含み、前記第2の信号変換
手段は前記第1及び第2チヤンネル信号の差を出力する
減算回路と、前記減算回路の出力を整流する第2整流回
路と、前記第2整流回路の出力を積分する第2積分回路
とを含むことを特徴とする特許請求の範囲第1項の残響
付加装置。 3 前記遅延手段は前記電圧制御発振回路の出力信号を
シフト用信号とするアナログシフトレジスタであること
を特徴とする特許請求の範囲第1項又は第2項の残響付
加装置。 4 前記遅延手段は、前記第1及び第2チヤンネル信号
をそれぞれ遅延する第1及び第2遅延回路を有すること
を特徴とする特許請求の範囲第1項、第2項又は第3項
の残響付加装置。[Scope of Claims] 1. A first signal conversion means for generating a DC signal having a level corresponding to the sum of first and second channel signals, and a first signal converting means for generating a DC signal having a level corresponding to the difference between the first and second channel signals. a second signal converting means for generating a DC signal having a
and a difference signal generating means for generating a signal corresponding to the difference between the DC signals from the second signal converting means, and a comparing means for comparing the DC signal from the second signal converting means and a predetermined reference voltage; a first gate circuit controlled by the output of the comparing means and receiving the output of the difference signal generating means; and a second gate circuit controlled by the inverted output of the comparing means and receiving the inverted output of the difference signal generating means. a voltage-controlled oscillation circuit whose oscillation frequency is controlled by the outputs of the first and second gate circuits; and a voltage-controlled oscillation circuit whose oscillation frequency is controlled by the output signals of the voltage-controlled oscillation circuit; and the first and second channel signals whose delay times are controlled by the output signals of the voltage-controlled oscillation circuit. 1. A reverberation adding apparatus comprising: a delay means for delaying the delay means; and a synthesis means for synthesizing the output of the delay means and the first and second channel signals. 2. The first signal conversion means includes an adder circuit that outputs the sum of the first and second channel signals, a first rectifier circuit that rectifies the output of the adder circuit, and integrates the output of the first rectifier circuit. a first integrating circuit, and the second signal converting means includes a subtracting circuit that outputs the difference between the first and second channel signals, a second rectifying circuit that rectifies the output of the subtracting circuit, and the second signal converting means 2. The reverberation adding device according to claim 1, further comprising a second integrating circuit that integrates the output of the rectifying circuit. 3. The reverberation adding device according to claim 1 or 2, wherein the delay means is an analog shift register that uses the output signal of the voltage controlled oscillation circuit as a shift signal. 4. Reverberation addition according to claim 1, 2, or 3, wherein the delay means includes first and second delay circuits that respectively delay the first and second channel signals. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52128919A JPS601799B2 (en) | 1977-10-27 | 1977-10-27 | Reverberation adding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52128919A JPS601799B2 (en) | 1977-10-27 | 1977-10-27 | Reverberation adding device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5461904A JPS5461904A (en) | 1979-05-18 |
| JPS601799B2 true JPS601799B2 (en) | 1985-01-17 |
Family
ID=14996607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52128919A Expired JPS601799B2 (en) | 1977-10-27 | 1977-10-27 | Reverberation adding device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601799B2 (en) |
-
1977
- 1977-10-27 JP JP52128919A patent/JPS601799B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5461904A (en) | 1979-05-18 |
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