JPS601800B2 - Reverberation adding device - Google Patents
Reverberation adding deviceInfo
- Publication number
- JPS601800B2 JPS601800B2 JP52128920A JP12892077A JPS601800B2 JP S601800 B2 JPS601800 B2 JP S601800B2 JP 52128920 A JP52128920 A JP 52128920A JP 12892077 A JP12892077 A JP 12892077A JP S601800 B2 JPS601800 B2 JP S601800B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- channel signals
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000002194 synthesizing effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000003786 synthesis reaction Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 6
- 238000009499 grossing Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 230000001755 vocal effect Effects 0.000 description 1
Landscapes
- Reverberation, Karaoke And Other Acoustics (AREA)
- Stereophonic System (AREA)
Description
【発明の詳細な説明】
本発明は残響付加装置に関し、特にステレオ及びモノラ
ル音声信号に残響音を付加することの可能な残響付加装
置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reverberation adding device, and more particularly to a reverberation adding device capable of adding reverberation to stereo and monaural audio signals.
ステレオセット等の音響再生機器において、ある種のプ
ログラムソース再生時に所定の残響を付加して蟻感上好
ましい再生費を得ているが、か)る残響の付加としては
、得られた残響成分を可変抵抗器等を用いて、もとの信
号と好みのレベルでミキシングする方法が一般的である
。In audio playback equipment such as stereo sets, when playing certain program sources, a predetermined reverberation is added to obtain a playback cost that is desirable from a human perspective. A common method is to mix the signal with the original signal at a desired level using a variable resistor or the like.
しかしながら、この様な方法では、もとの信号内容にか
)わらず一定レベルの残響音が付加されることになるた
めに、例えば入力信号がボーカル等の場合には当該入力
信号自体にすでに残響音が付加されている関係上、更に
残響を付加することになり聴感上むしろ不自然な感じを
与えることになり好ましいものではない。また、AM放
送をはじめモノラルあるいはセパレーションの小さなプ
ログラムソースの場合は、残響成分付加により好感のも
てる再生音を得ることができるが、先述した如く残響成
分のミキシングはユーザが手動によりレベルを調整して
聡感上より良い再生条件を作り出す必要があり、ユーザ
側の当該調整のわすらわしごを伴う欠点がある。However, with this method, a constant level of reverberation is added regardless of the original signal content, so for example, if the input signal is a vocal, etc., the input signal itself already has reverberation. Since the sound is added, reverberation is added, which gives an unnatural feeling to the auditory sense, which is not preferable. Furthermore, in the case of monaural or program sources with small separation, such as AM broadcasting, it is possible to obtain a pleasant playback sound by adding reverberation components, but as mentioned earlier, the mixing of reverberation components requires the user to manually adjust the level. Therefore, it is necessary to create better playback conditions in terms of intelligence, and there is a drawback that the user has to make the necessary adjustments.
本発明は上述の欠点に鑑みなされたものであり従って入
力信号の内容に応じて付加する残響音のレベルを自動的
に制御することのできる残響付加装置を提供することを
目的としている。以下、本発明を添付図面を用いて詳細
に説明する。The present invention has been made in view of the above-mentioned drawbacks, and therefore, it is an object of the present invention to provide a reverberation adding device that can automatically control the level of reverberant sound added depending on the content of an input signal. Hereinafter, the present invention will be explained in detail using the accompanying drawings.
図は本発明の実施例を示すブロック図であり「図におい
てプログラムソースであるステレオ信号の左右チャンネ
ル信号(以下L,R信号と略す)がそれぞれ入力端子1
及び2に印加されて、共に加算回路3及び減算回路4へ
入力される。The figure is a block diagram showing an embodiment of the present invention.
and 2, and both are input to the addition circuit 3 and the subtraction circuit 4.
従って加算回路3の出力は(L+R)信号となり、減算
回路4の出力は(L−R)信号となる。当該両信号はそ
れぞれ整流回路5,6及び所定時定数を有する積分回路
7,8に印加されて、(L+R)及び(L−R)信号に
応じた直流レベルに変換される。これ等直流信号は共に
直流減算回路9に入力されて両者の差に相当する電圧が
当該減算回路9及び次段の平滑回路10を介して出力さ
れることになる。平滑回路10の出力である差信号電圧
は一入力のゲート回路16へ入力されると共に、反転回
路14により反転されて同じく一入力ゲート回路15へ
入力される。一方、(L−R)信号に応じた直流レベル
を有する電圧すなわち積分回路8の出力は電圧比較回路
1 1に入力さ.・れて所定基準電圧と比較される。Therefore, the output of the addition circuit 3 becomes a (L+R) signal, and the output of the subtraction circuit 4 becomes a (L-R) signal. These two signals are applied to rectifier circuits 5 and 6 and integration circuits 7 and 8 having predetermined time constants, respectively, and are converted into DC levels according to the (L+R) and (LR) signals. These DC signals are both input to the DC subtraction circuit 9, and a voltage corresponding to the difference between the two is outputted via the subtraction circuit 9 and the next stage smoothing circuit 10. The difference signal voltage that is the output of the smoothing circuit 10 is input to a one-input gate circuit 16, and is also inverted by an inverting circuit 14 and input to a one-input gate circuit 15. On the other hand, the voltage having a DC level corresponding to the (LR) signal, that is, the output of the integrating circuit 8, is input to the voltage comparator circuit 11. - compared with a predetermined reference voltage.
言舞嵩雷電策を基山喬手管嵩亭雲量隼毒害;ズまた比較
回路11の出力は反転回路13により反転されてゲート
16の開閉動作を制御する。ゲート回路15,16の出
力は共に電圧制御減衰回路17の電圧制御入力端子に接
続されて当該ゲート回路から出力される直流電圧レベル
に応じてその減衰量が制御される。電圧制御減衰回路1
7,18の各入力はそれぞれ遅延回路19及び20‘こ
より所定量遅延されたL及びR信号であり、減衰回路1
7及び18の各出力はそれぞれ次段の加算回路21及び
22に印加され、入力端子1及び2に入力された原信号
であるL及びR信号とそれぞれ加え合わされて、出力端
子23及び24に出力される。尚、減衰回路17,18
の各出力はそれぞれ遅延回路19,20の各入力に帰還
されて適当な残響が付加されたL,R信号が得られる。
上述した回路の動作原理及び効果を以下に述べる。Furthermore, the output of the comparison circuit 11 is inverted by the inverting circuit 13 to control the opening/closing operation of the gate 16. The outputs of the gate circuits 15 and 16 are both connected to a voltage control input terminal of a voltage control attenuation circuit 17, and the amount of attenuation thereof is controlled in accordance with the DC voltage level output from the gate circuit. Voltage control attenuation circuit 1
The inputs 7 and 18 are L and R signals delayed by a predetermined amount from the delay circuits 19 and 20', respectively, and are input to the attenuation circuit 1.
The respective outputs of 7 and 18 are applied to adder circuits 21 and 22 at the next stage, respectively, and are added to the L and R signals, which are the original signals input to input terminals 1 and 2, respectively, and output to output terminals 23 and 24. be done. In addition, the attenuation circuits 17 and 18
The respective outputs are fed back to the respective inputs of delay circuits 19 and 20 to obtain L and R signals to which appropriate reverberation has been added.
The operating principle and effects of the above-mentioned circuit will be described below.
入力信号をステレオ信号とするとL,R信号は下記の如
く表わすことができる。When the input signal is a stereo signal, the L and R signals can be expressed as follows.
こ)で1及びrはステレオ再生時においてそれぞれ左及
び右に定位する音像成分であり、Cは虚像として左右中
央に定位する音像成分である。In this), 1 and r are sound image components localized to the left and right, respectively, during stereo reproduction, and C is a sound image component localized to the left and right center as a virtual image.
従って加算及び減算回路3及び4の出力S^及びSSは
次式で示される。よってS^及びSSは整流回路5,6
及び積分回路7,8により共に直流電圧S^。Therefore, the outputs S^ and SS of the addition and subtraction circuits 3 and 4 are expressed by the following equations. Therefore, S^ and SS are rectifier circuits 5 and 6
and DC voltage S^ by integral circuits 7 and 8.
及びSS。となって次式で示される。こ)で−−一は直
流レベル変換後の平均値を示すものとする。and S.S. This is shown by the following equation. In this), -1 indicates the average value after DC level conversion.
(以下同じ)一方、1及びrは全く別個のランダム信号
であるからb+r≠1一rがなりたつと考えられる。(The same applies hereinafter) On the other hand, since 1 and r are completely separate random signals, it is considered that b+r≠1−r.
よってSAD及びSS。の差電圧すなわち平滑回路10
の出力は次式で表わすことができる。SAD−SS。Therefore, SAD and SS. , that is, the smoothing circuit 10
The output of can be expressed as: SAD-SS.
〒C ・・・・・・・・・{4}上記(4)
式から分るように平滑回路10の出力すなわちゲート回
路15及び16の入力には中央定位成分Cに対応した電
圧レベルが得られる。換言すれば入力信号中のC成分が
大きい場合はCのレベルも上昇するからゲート回路16
の入力は増加し、他方ゲート回路15の入力は減少する
ことになる。こ)で、入力端子1及び2に印加されるプ
ログラムソースがモノラル信号の場合には、L=R=*
′2と表わすことができるから、前記したステレオ信号
の場合と同様にしてS^。〒C ・・・・・・・・・{4} Above (4)
As can be seen from the equation, a voltage level corresponding to the center localization component C is obtained at the output of the smoothing circuit 10, that is, at the input of the gate circuits 15 and 16. In other words, if the C component in the input signal is large, the level of C also increases, so the gate circuit 16
The input to the gate circuit 15 will increase, while the input to the gate circuit 15 will decrease. In this case, if the program source applied to input terminals 1 and 2 is a monaural signal, L=R=*
'2, so S^ can be expressed as in the case of the stereo signal described above.
,SSD及びSAD−SSDは次式となる。上記‘3}
及び{5}式のSS。, SSD and SAD-SSD are expressed as follows. Above '3}
and SS of formula {5}.
より入力信号のモノラルステレオの別を直流レベルにて
判断することが可能であることは明白であるから、今電
圧比較器11の基準電圧発生器12の基準電圧をVRと
して1一r>VR>0なる値に選定し、SS。>VRの
時に比較回路11の出力が“H”(高)レベル,S如く
VRの時に“L”(低)レベルとなるように設計し、ゲ
ート回路15,16が制御入力“H”レベルの場合に開
すなわち導適状態になるようにすれば、電圧制御減衰回
路17,18の制御電圧に関して次の2つの場合が存在
することになる。先ずSSD<VRの場合すなわち入力
信号がモノラムの場合には、比較回路11の出力は“L
”レベルとなり、よって反転回路13を介してゲート回
路16が導通し、C成分に比例した電圧が電圧制御減衰
回路17,18の制御電圧となる。次にSS。>VRす
なわちステレオの場合には比較回路11の出力が“H’
’レベルとなり、ゲート回路15が導通してステレオ中
のC成分に反比例した直流電圧が電圧制御減衰回路17
,18の制御電圧となる。こ)で電圧制御減衰回路17
,18の利得は制御電圧VCに比例しており最大利得を
1とすると、減衰回路入力及び出力電圧をそれぞれvi
及びvoとすれば次式が成立する。It is clear that it is possible to judge whether the input signal is monaural or stereo based on the DC level, so now, assuming that the reference voltage of the reference voltage generator 12 of the voltage comparator 11 is VR, 11r>VR> Select a value of 0 and set it to SS. > The output of the comparator circuit 11 is designed to be at "H" (high) level when it is VR, and to be at "L" (low) level when it is VR like S, and the gate circuits 15 and 16 are If the voltage-controlled attenuation circuits 17 and 18 are opened or conductive, the following two cases will exist regarding the control voltages of the voltage-controlled attenuation circuits 17 and 18. First, when SSD<VR, that is, when the input signal is a monoram, the output of the comparison circuit 11 is “L”.
Therefore, the gate circuit 16 becomes conductive via the inversion circuit 13, and a voltage proportional to the C component becomes the control voltage of the voltage control attenuation circuits 17 and 18. Next, SS.>VR, that is, in the case of stereo The output of the comparison circuit 11 is “H”
' level, the gate circuit 15 becomes conductive, and a DC voltage inversely proportional to the C component in the stereo is applied to the voltage control attenuation circuit 17.
, 18 control voltages. ) voltage control attenuation circuit 17
, 18 are proportional to the control voltage VC, and if the maximum gain is 1, the attenuation circuit input and output voltages are respectively vi
and vo, the following equation holds true.
V。V.
=守・Vi(VC/k≦1).・・.・■(6)ここに
k‘ま電圧一利得変換係数である。よって上式側より減
衰回路の出力電圧voは制御電圧VCに比例することが
わかる。= Mamoru Vi (VC/k≦1).・・・.・■(6) Here, k' is the voltage-gain conversion coefficient. Therefore, it can be seen from the above equation that the output voltage vo of the attenuation circuit is proportional to the control voltage VC.
以上の関係から入力信号がモノラルソースの場合を考え
ると、C成分が上昇良0ちL,R信号が同一で当該同一
信号レベルが上昇することによりVCが増加し、よって
減衰回路17,18の出力電圧voも増大することにな
る。Considering the case where the input signal is a monaural source from the above relationship, if the C component rises, the L and R signals are the same, and the same signal level rises, so VC increases, and therefore the attenuation circuits 17 and 18 The output voltage vo will also increase.
すなわちモノラルソースの場合は入力が大になる程遅延
信号のレベルは大となる。他方、入力信号がステレオソ
ースの場合を考えると、ステレオ信号中のC成分が増大
すると制御電圧VCが減少し、よって減衰回路17,1
8の出力電圧voも減少する。In other words, in the case of a monaural source, the higher the input, the higher the level of the delayed signal. On the other hand, considering the case where the input signal is a stereo source, when the C component in the stereo signal increases, the control voltage VC decreases, and therefore the attenuation circuit 17,1
8's output voltage vo also decreases.
即ちC成分レベルが大の場合には遅延信号のレベルは小
となる様動作する。即ちプログラムソース中にすでに多
くの残響が付加されている場合にはC成分のレベルが大
であるから、本回路による残響成分レベルは減少し好都
合となる。以上詳述した如く本発明によれば、モノラル
ソースのような拡がりの少ないプログラムソースに対し
ては入力レベルに比例して残響成分の大なるものが得ら
れ、よって残響効果が自然なものが得られる。That is, when the C component level is high, the delay signal is operated to have a low level. That is, if a large amount of reverberation has already been added to the program source, the level of the C component will be high, so this circuit advantageously reduces the reverberation component level. As detailed above, according to the present invention, for a program source with little spread, such as a monaural source, a large reverberation component can be obtained in proportion to the input level, and a natural reverberation effect can therefore be obtained. It will be done.
一方ステレオソースの場合にはあらかじめ含まれる残響
に対応するC成分の大小に従って遅延信号のレベルを小
大にそれぞれ制御して自動的にかつ効果的に自然な残響
付加が達成される。このように、本発明の装置ではプロ
グラムソースの状態に合致した残響付加が可能となり、
特にモノラルソースの場合にはその入力レベルに応じて
自動的に残響が制御され聴感上好ましいものとなる。ま
たマイクミキシング等の付加入力の場合にもその音量に
応じて残響付加による効果を変化させることができ好都
合であり、更に残響効果に用いるのみならず他の音響効
果の付加例えば位相変調等への応用へも発展させること
が可能である。満、上述の実施例においては、L及びR
チャンネル毎に遅延回路、減衰回路を用いたが、L,R
チャンネル信号を合成(例えば加算若しくは減算)して
、当該合成信号に対して遅延及び減衰を行うための遅延
回路、減衰回路を各一個設けてもよい。On the other hand, in the case of a stereo source, the level of the delayed signal is controlled to be small or large according to the magnitude of the C component corresponding to the reverberation included in advance, thereby automatically and effectively adding natural reverberation. In this way, the device of the present invention makes it possible to add reverberation that matches the state of the program source.
Particularly in the case of a monaural source, the reverberation is automatically controlled according to the input level, making it more pleasing to the ear. Furthermore, in the case of additional inputs such as microphone mixing, it is convenient to be able to change the effect of adding reverberation depending on the volume.Furthermore, it can be used not only for reverberation effects, but also for adding other acoustic effects such as phase modulation. It is also possible to develop it into applications. In the above embodiments, L and R
A delay circuit and an attenuation circuit were used for each channel, but L, R
One delay circuit and one attenuation circuit may be provided for synthesizing (for example, adding or subtracting) channel signals and delaying and attenuating the synthesized signal.
更には、遅延回路19,201こ対してそれぞれ異なる
遅延時間をもたせてもよいし、減衰回路17,18に対
して周波数特性をもたせてもよく、またそれぞれ異なる
周波数特性としてもよい。更にはまた、加算回路21,
22の代りに、減衰回路17,18の出力を本来のL及
びRチャンネル用スピーカとは別のスピーカへそれぞれ
直接に導入しても、残響効果は得られる。Furthermore, the delay circuits 19 and 201 may have different delay times, the attenuation circuits 17 and 18 may have frequency characteristics, or they may have different frequency characteristics. Furthermore, the addition circuit 21,
22, the reverberation effect can also be obtained by directly introducing the outputs of the attenuation circuits 17 and 18 into speakers other than the original L and R channel speakers.
図は本発明の実施例を示すブ。 The figure shows an embodiment of the present invention.
Claims (1)
有する直流信号を発生する第1の信号変換手段と、前記
第1及び第2チヤンネル信号の差に応じたレベルを有す
る直流信号を発生する第2の信号変換手段と、前記第1
及び第2の信号変換手段からの直流信号の差に応じた信
号を発生する差信号発生手段と、前記第2の信号変換手
段からの直流信号と所定基準電圧とを比較する比較手段
と、前記比較手段の出力により制御され前記差信号発生
手段の反転出力を入力とする第1のゲート回路と、前記
比較手段の反転出力により制御され前記差信号発生手段
の出力を入力とする第2のゲート回路と、前記第1及び
第2チヤンネル信号を遅延させる遅延手段と、前記第1
及び第2のゲート回路の出力により減衰量が制御されつ
つ前記遅延手段の出力信号を減衰する電圧制御減衰手段
と前記電圧制御減衰手段の出力と前記第1及び第2チヤ
ンネル信号とを合成する合成手段とを含むことを特徴と
する残響付加装置。 2 前記第1の信号変換手段は前記第1及び第2チヤン
ネル信号の和を出力する加算回路と、前記加算回路の出
力を整流する第1整流回路と、前記第1整流回路の出力
を積分する第1積分回路とを含み、前記第2の信号変換
手段は前記第1及び第2チヤンネル信号の差を出力する
減算回路と、前記減算回路の出力を整流する第2整流回
路と、前記第2整流回路の出力を積分する第2積分回路
とを含むことを特徴とする特許請求の範囲第1項の残響
付加装置。 3 前記遅延手段は前記第1及び第2チヤンネル信号を
それぞれ遅延する第1及び第2遅延回路を有し、前記電
圧制御減衰手段は前記第1及び第2遅延回路の各出力を
それぞれ減衰する第1及び第2電圧制御減衰回路を有す
ることを特徴とする特許請求の範囲第1項又は第2項の
残響付加装置。 4 前記合成手段は前記電圧制御減衰手段の出力と前記
第1及び第2チヤンネル信号との和を出力する加算回路
を有することを特徴とする特許請求の範囲第1項の残響
付加装置。[Scope of Claims] 1. A first signal conversion means for generating a DC signal having a level corresponding to the sum of first and second channel signals, and a first signal converting means for generating a DC signal having a level corresponding to the difference between the first and second channel signals. a second signal converting means for generating a DC signal having a
and a difference signal generating means for generating a signal corresponding to the difference between the DC signals from the second signal converting means, and a comparing means for comparing the DC signal from the second signal converting means and a predetermined reference voltage; a first gate circuit that is controlled by the output of the comparing means and receives the inverted output of the difference signal generating means; and a second gate circuit that is controlled by the inverted output of the comparing means and receives the output of the difference signal generating means. a circuit, a delay means for delaying the first and second channel signals, and a delay means for delaying the first and second channel signals;
and voltage control attenuation means for attenuating the output signal of the delay means while the amount of attenuation is controlled by the output of a second gate circuit, and synthesis for combining the output of the voltage control attenuation means and the first and second channel signals. A reverberation adding device characterized by comprising: means. 2. The first signal conversion means includes an adder circuit that outputs the sum of the first and second channel signals, a first rectifier circuit that rectifies the output of the adder circuit, and integrates the output of the first rectifier circuit. a first integrating circuit, and the second signal converting means includes a subtracting circuit that outputs the difference between the first and second channel signals, a second rectifying circuit that rectifies the output of the subtracting circuit, and the second signal converting means 2. The reverberation adding device according to claim 1, further comprising a second integrating circuit that integrates the output of the rectifying circuit. 3. The delay means has first and second delay circuits that respectively delay the first and second channel signals, and the voltage controlled attenuation means has a first and second delay circuit that attenuates each output of the first and second channel signals, respectively. 3. The reverberation adding device according to claim 1, further comprising a first voltage control attenuation circuit and a second voltage control attenuation circuit. 4. The reverberation adding device according to claim 1, wherein the synthesizing means includes an addition circuit that outputs the sum of the output of the voltage-controlled attenuation means and the first and second channel signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52128920A JPS601800B2 (en) | 1977-10-27 | 1977-10-27 | Reverberation adding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52128920A JPS601800B2 (en) | 1977-10-27 | 1977-10-27 | Reverberation adding device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5461905A JPS5461905A (en) | 1979-05-18 |
| JPS601800B2 true JPS601800B2 (en) | 1985-01-17 |
Family
ID=14996634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52128920A Expired JPS601800B2 (en) | 1977-10-27 | 1977-10-27 | Reverberation adding device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601800B2 (en) |
-
1977
- 1977-10-27 JP JP52128920A patent/JPS601800B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5461905A (en) | 1979-05-18 |
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