JPS6018948B2 - test pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test pattern generator that makes it possible to test a semiconductor memory circuit or a memory circuit portion in a semiconductor device and efficiently analyze the results.

Figures 1a to 1e show arbitrary areas of a memory cell matrix used to test malfunctions of address circuits, decoder circuits, etc. of the memory under test, effects of interference between memory cells in the memory cell matrix, etc. An example is shown in which a test pattern in which the written data pattern is intentionally inverted is written into the memory under test, and the shaded area in the figure indicates that the written data is inverted with respect to the others.

A test pattern for performing such data inversion in an arbitrary area has been generated by a pattern generator using a microprogram method having a configuration as shown in FIG. Such a conventional test pattern generator consists of an address pattern generation section 2 and a data pattern generation section 3, which are controlled by a program control section 1, and generates an address pattern and a data pattern to be generated at that time (for example, a write data pattern). Since both are generated by essentially independent pattern generating units, it has been difficult to establish a relationship between them.

Therefore, in order to invert a data pattern in an arbitrary area as shown in FIG. This is realized by combining a microprogram that describes a sequence with an instruction set for controlling the program control unit 1, which not only increases the number of steps in the microprogram and makes it more complicated, but also increases the computation time of the data pattern generation unit 3. Since it is generated by a combination of a function and an instruction set for controlling the program control unit 1, it has the disadvantage that the range in which data can be inverted is restricted by the combination limit. An object of the present invention is to make it possible to perform data pattern inversion in an arbitrary area with a simple configuration, whereas the microprogram is complicated and has restrictions in the pattern generator using the conventional microprogram method as described above. Embodiments will be described in detail below.

The present invention replaces the address pattern that is applied to the memory circuit under test and the data pattern at that time (for example, write data pattern) independently generated by an address pattern generation section and a data pattern generation section. By creating a relationship between the two, it is possible to easily realize data pattern inversion in an arbitrary area. FIG. 3 is a block diagram of an embodiment of the present invention.

The test pattern generator of the present invention stores a microprogram that describes test patterns to be generated, decodes the microprogram during execution, and sends instructions to each pattern generation section (address and data pattern generation section). At the same time, the status information from each pattern generation part is obtained,
A program control section 1 that controls the progress of a microprogram, and an address pattern generator 2 (X and Y address patterns ' program control section 1) and program control section 1.
a data pattern generator 3 that generates data patterns by receiving instructions from and performing corresponding arithmetic operations; and a data pattern generator 3 that receives the generated X and Y address pattern signals, decodes them, and executes them. By accessing each of the X and Y inversion memories in which inversion information of the position corresponding to the X address or Y address of the memory under test whose data is to be inverted is written in advance, the memory under test to be inverted can be X and Y inversion memories 4 and 5 obtain data inversion information corresponding to the X and Y addresses of The selected logic (e.g. “
0” fixed, “1” fixed, ×, Y, XoRY, XNoRY
, X^NoY, XN^NoY, XEx-oRY, Xox
-NORY, etc.) and sends the result to the inverting circuit.
The inverting circuit 7 obtains an inverted or non-inverted output based on the output from the inverting circuit 7, and uses the inverted or non-inverted output as a data pattern. FIG. 4 is an explanatory diagram of the operation, and the operation will be explained below with reference to FIGS. 3 and 4. Before starting the test, a microprogram in which the test pattern to be generated is written and X, Y inversion memories 4 and 5 are stored in the program control unit 1 in advance.
Inversion information is written in each of the memories 41 and 51 at bit positions corresponding to the area 12 of the memory under test 10 where data inversion is to be performed. Note that 11 indicates one of the write data patterns. During operation, an arbitrary test pattern is generated by the address pattern generating section 2 and the data pattern generating section 3 according to a command from the program control section 1. However, the pattern program is created for the data pattern generation section 3 without being aware of the data inversion area 12. For example, the fourth
In the illustrated example, the data pattern generator 3 creates a pattern program that always outputs "0". The memory under test 10 is accessed using the x and Y address patterns generated by the address pattern generating section 2, and at the same time, the memories 41 and 51 are accessed via the decoders 42 and 52, respectively.
access.

As a result, Douty is output as the inverted data U corresponding to the address accessed from the memories 41 and 51, respectively. These inverted data Doutx, Douty
is determined by the logic control circuit 6 (in the example shown in FIG. 4, it is assumed that the logic of Invert or non-invert the data pattern. That is, if the contents of the memories 41 and 51 are as shown in FIG.
1" can be written. FIGS. 6a and 6b are block diagrams of different embodiments of the X and Y inversion memories '1 and 5, respectively, and a decoder DE for decoding the address pattern.
It has C and memories MEM and MEM'.

Figure a shows one inverted data D for the address pattern.
A case is shown in which out is read out and applied to the logic control circuit 6, and FIG.
This shows a case in which n inverted data Dout can be output with the old M', and in the case shown in FIG. becomes. Further, by changing the contents of the memories M and MEM', an arbitrary data inversion area can be defined. As explained above, the present invention provides address pattern generation section 2.
Inversion memories 4 and 5 are provided between the
By making a predetermined association using the logic control circuit 6, inverting circuit 7, etc., data pattern inversion in any area can be easily realized, and the generation of various test patterns for the memory under test can be achieved with an extremely small number of program steps. And it can be done with a simple configuration.

[Brief explanation of the drawing]

1A to 1E are explanatory diagrams of the data inversion area for the memory under test, FIG. 2 is a block diagram of a subordinate test pattern generator, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. The figure is an operation explanatory diagram, and FIGS. 5a and 5b are block diagrams of different embodiments of the inversion memory. 1 is a program control section, 2 is an address pattern generation section,
3 is a data pattern generator, 4 is a Y inversion memory, and 5 is an X
6 is an inversion memory, 6 is a logic control circuit, and 7 is an inversion circuit. O1 Wing O2 Oka O3 Mother O48 O5 Crab

Claims (1)

[Claims] 1. A program control unit that stores a microprogram that describes a test pattern to be generated, decodes the microprogram during execution, and sends a command signal based on the decoding result, and a program control unit that receives and responds to commands from the program control unit. a data pattern generating section that generates a data pattern by performing an arithmetic operation, and an address pattern generating section that generates one or more types of address patterns by receiving instructions from the program control section and performing a corresponding arithmetic operation. accessed by a generating section and an address pattern generated from the address pattern generating section;
One or more inverting memories that output inversion information written in advance at a position corresponding to the position where data in the memory under test is to be inverted, and logic that performs a logical operation selected by a selection signal on the output of the inverting memory. A test pattern generator comprising: a control circuit; and an inverting circuit that performs an inverting or non-inverting operation on a data pattern generated from the data pattern generating section according to an output from the logic control circuit.