JPS6023530B2 - push-pull amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in push-pull amplifier circuits used in power amplifiers and the like of audio equipment.

The basis of such an amplifier circuit is a class A and class B combinatory push-pull amplifier circuit.

Here, class A transistors have the advantage that the pair of output transistors always operate in the active region and never shift to the cutoff region, so switching distortion is not correct, but on the other hand, it is necessary to flow a large bias current. , the disadvantage is that heat loss is large. Class B transistors have the advantage of reducing bias current and reducing heat loss, but have the disadvantage of generating switching distortion because the pair of output transistors are alternately switched between active and cutoff states. Therefore, by applying a variable bias between the bases of a pair of output transistors in a combinatory push-pull amplifier circuit, which changes according to the current flowing through the output transistors, the output transistors can be operated with a minimum operating current and always It is possible to operate in the active region, and has the effect of preventing the occurrence of switching distortion as seen in class B operating bush-pull amplifiers. On the other hand, switching distortion in a class B operating push-pull amplifier occurs more significantly as the signal frequency becomes higher. Accordingly, an object of the present invention is to provide a push-pull amplifier circuit with improved high voltage characteristics by enhancing the effect of preventing the generation of switching distortion in the push-pull amplifier circuit equipped with the variable bias generating means described above. An embodiment of the present invention will be specifically described below based on the drawings.

In Figure 1, an NPN output transistor Q, and a PNP
Both emitters of the output transistors Q2 are commonly connected at the output point OUT via resistors 戊, , R2, and a load RL such as a speaker is connected to the output point OUT, and the output amplified by the output transistors Q, , Q2 is connected to the output point OUT. It is designed to be driven by The emitters of driver transistors Q and Q4 are connected to the bases of transistors Q and Q2, respectively, and emitter resistors R3 and R4 are connected between the emitters and the output point OUT, respectively. A base bias voltage from a bias generation circuit is supplied between the bases of the driver transistors Q and Q4. In other words, the base bias generation circuit consists of an NPN transistor, a diode ○, D2 that generates a reference bias, and voltage adjustment resistors R5 and P.
It consists of a series circuit with an NP transistor Q6, to which a current is supplied from a constant current source 1, and an input signal is applied by an input transistor Q7 whose base is connected to the input terminal IN. ing. The transistors Q5 and Q6 operate as fixed bias generating transistors, and variable bias transistors Q and Q for detecting the currents of the output transistors Q and Q2 are connected to the transistors Q and Q6. That is, P
The NP transistor False has its emitter connected to the base of the transistor Q5 and is further connected to the collector of the transistor Q5 via a resistor R6, whose collector is connected to the emitter of the transistor Q5 and whose base is connected to the resistor R8.
, are connected to the output point OUT via a diode D3, and the emitter of the NPN transistor Q9 is connected to the base of the transistor Q6, which is also connected to the collector of the transistor Q via a resistor R7, and the collector is connected to the transistor Q9. It is connected to the Q emitter, and its base is further connected to the output point OUT via a resistor 9 and a diode D4. Resistor R8 and diode D3 and resistor R9
Current from the constant current source 13 is supplied to the diode 04, and the output point OUT is supplied to the transistor Q and the common base.
It is designed to supply a constant fly pressure to the air. Here, the variable bias transistors Q8 and Q9 are set so that the operating point during the bran signal is at point A shown in FIG. 2, that is, the minimum base bias is applied so that the collector current starts to flow. Therefore, when there is no signal, the collector currents of the transistors Q8 and Q are very small.

Therefore, the voltage drop across resistors R6 and R7 is also very small.
The voltage between the bases of the output transistors Q, Q2 is determined by the base-emitter voltage of the transistors Q5 and Q6, the forward drop voltage of the diodes D, D2, and the resistor R.
It is set based on the sum of the voltages generated in 5. In this way, a signal is applied from the input transistor Q7, and the output point OUT
When transitions to the positive side due to the input signal condition, current flows through the output transistor Q, and the voltage between the base of the transistor Q and the output point OUT increases, so the current is detected by the transistor Q8, and the The base-emitter voltage increases and collector current flows through transistor Q6.

If the current amplification factor of each transistor is large, most of the current flowing through resistor R6 will become the collector current of transistor Q8, and the current flowing through resistor R5 will be the same as when no signal is present, and will flow through both collectors of transistors Q8 and Q. The voltage between them is kept the same as when there is no signal. On the other hand, the operating point of the transistor shifts from point A to point B in Figure 2, but the change in the voltage between the base and emitter at this time is minute, and the voltage between the base and collector of transistor Q8 also changes when there is no signal. It is almost the same as Further, a current is supplied to the resistor R8 and the diode D3 by a constant current source 12, and the voltage drop thereof is always constant. Therefore, transistor Q2 for output point OUT
The base voltage of Q2 is maintained at approximately the same voltage as when there is no signal, and the output transistor Q2 does not enter the cutoff region. Next, even when the output point OUT shifts to the negative side due to the input signal condition and the output transistor Q2 performs an amplifying operation, the output transistor Q does not shift to the cutoff region due to the same effect as described above.

Note that a capacitor C is connected in parallel between both ends P and Q of the bias generating circuit including the transistors Q and Q.

Due to the action of the bias generating circuit, this capacitor C is charged when the voltage between points P and Q increases, and conversely discharged when it decreases. In the circuit configuration shown in Fig. 1, the discharging time of capacitor C is longer than the charging time, so when the Takagi signal continues, the voltage between P and Q increases compared to the case where capacitor C does not exist. As a result, the output transistor Q
,, the operating current of Q2 increases. Therefore, the effect of the bias circuit can be enhanced at the Takagi frequency where switching distortion occurs significantly in a class B amplifier circuit, and an amplifier circuit with better Takagi characteristics can be obtained. If the operating current of the output transistors Q, Q2 increases too much at ultra-high frequencies, the capacitor C
It is sufficient to insert a resistor R in series with . Since the present invention is configured as described above, the output transistor always operates in the active region and does not shift to a cut-off mirror state, thereby eliminating the switching distortion seen in class B push-pull amplifier circuits. Also, since the capacitor C is connected in parallel to both ends of the bias generation circuit, the effect of the bias circuit is enhanced at the Takagi frequency, and switching distortion does not occur even when reproducing the Takagi frequency.

A stable amplifier circuit can be provided.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a diagram showing operating characteristics of some transistors used in the embodiment shown in the figure, and a wiring diagram showing a modified example of a capacitor circuit connected in parallel to a variable bias generation circuit. Q,, Q2...output transistor, Q5, Q...bias generation transistor, Q6, Q9...current detection transistor,
C...Capacitor. Traditional Figure 2 Figure 3

Claims (1)

[Claims] 1. In an amplifier circuit that operates in a push-pull manner and has base bias means connected between the bases of first and second output transistors whose emitters are commonly connected at an output point via a resistor, the base bias means is first and second constant voltage generating means for generating a constant voltage with respect to the output point; an emitter is connected to the base of the first output transistor via a resistor; a first bias transistor whose base is connected; and a second bias transistor whose emitter is connected to the base of the second output transistor via a resistor, and whose base is connected to the second constant voltage generating means. and a third bias transistor having a collector connected to the base of the first output transistor, a base connected to the emitter of the first bias transistor, and an emitter connected to the collector of the first bias transistor. , a fourth bias transistor having a collector connected to the base of the second output transistor, a base connected to the emitter of the previous second bias transistor, and an emitter connected to the collector of the second bias transistor; a reference bias generating means connected between the emitters of the third and fourth bias transistors, and further comprising a capacitor connected between the collectors of the third and fourth bias transistors. .