JPS6027039B2 - key assigner - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key assigner used in an electronic musical instrument.

In electronic organs etc. with conventional key assigners,
As a method of detecting a pressed key, each key switch is scanned in a time-sharing manner, and the information on the pressed key is collected using DTM.
Generally, a time division multiplexing method was used in which a key code storage bag is directly sent as a time division multiplex (time division multiplex) signal or a PCM (pulse code modulation) signal.

However, in this method, information on keyswitches that are not pressed is also sent because the state of keyswitch presses and keys is checked in a time-sharing manner, and one scanning period is required to send the necessary information. In order to improve the quick response to the key and key, it is necessary to use a very high frequency, for example several hundred KH.
A Z clock was required. Also, when the key is pressed, the time of the next key and 1
The response time may deviate depending on the relationship with the scanning interval. For example, if a key switch that has been pressed is released immediately after scanning, the response time will deviate by about one scanning interval. SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks, and to provide a key assigner that improves immediate response to key presses and key presses and lowers the clock frequency required to output key code data.

In order to achieve the above object, the key assigner of the present invention includes a master clock generator that supplies a master clock to each key switch in parallel in order to simultaneously detect a change in the state of the key next to the pressed key of each key switch; a first memory circuit that stores the state of the switch; a second memory circuit that stores the output of the first memory circuit in the second half of the master clock;
a memory circuit for detecting changes in the state of keys pressed and pressed in each key switch by the outputs of the first and second memory circuits; means for generating a corresponding key code, means for outputting a latch pulse from the master clock and the key code, and a second memory circuit reset by the output of the master clock and the output circuit to generate an output. a key code generating circuit group comprising key code generating circuits each provided corresponding to a plurality of key switches, and according to a predetermined priority order with the output of the variable screen output circuit in the key code generating circuit group, The key code is generated sequentially from the high priority key code generation circuit using the master clock, and the output of the low priority variable output circuit is temporarily prohibited.
A means for waiting for the generation of a key code, and a first control circuit for prohibiting the generation of the key code by the pressed key and giving priority to the Iso key when the key next to the key switch and the key of another key switch are pressed at the same time. It is characterized by this. In other words, the present invention sends the key code at the time of the change in the state of the key switch being pressed and released, and only requires a clock to check the state of all the key switches at the same time and the time to send the key code data during that time. Yes, the answer is extremely quick. If a change in the state of a key is detected at the same time, priority is given to key code output due to key release, and the key code output is output in accordance with a predetermined priority order, for example, giving priority to treble tones. The present invention will be described in detail below with reference to examples. In FIG. 1, a master clock generator 1 is provided which supplies master clocks in parallel to each of the key switches Sw, Sw2, . . . , S, .

The frequency of the master clock is 1'200 seconds at the maximum when all key codes generated in the key code storage circuit are written when one key is pressed at the same time.
If so, it is sufficient if it is higher than the fox HZ. The key code generating circuit group includes key code generating circuits 2i, which are representatively shown surrounded by broken lines, and are provided in n stages of key switches.

All these outputs are wired-or (OR). Now, in the key code generation circuit 2i, when the key switch (SWi) 21 is closed, the flip-flop (
FFI) 22 is set by the output Q of the master clock generator 1 and outputs "1" from the Q terminal. The flip-flop (FFI) 22 uses a D type flip-flop. AND1 has flip-flop (FFI) 22
's Q output "1" and the Q of flip-flop (FF2) 23
Output "1" is input, and ANDI outputs "1".
At this time, in other key code generation circuits, if the key is not in the released state, another similar AND3 outputs "0", and the lines (1,) 24 connected to each other via the diode DI are "0".
” is output.AND2 is BNDI and line (1,)24
The inverted output "1" of is input and outputs "1". AND
The 2 outputs are input to OR1, and ORI outputs "1".
At this time, the same circuit 2 above the key code generation circuit 2j
If p(2, ≦2p<2i) is a key or is not pressed, "0" is input to the lines (12) 25 connected to each other through an inverter so as to input each to AND4. Therefore, "1" is input to AND4. AND
4 receives ORI and the output "1" of line (12) 25, and outputs "1" as a result. The AND4 output is input to OR2, and OR2 outputs "1". As a result, key code generation in the circuits 2i to 2n below the key code generating circuit 2i is prohibited and placed on standby. Furthermore, the output of AND4 is input to the diode matrix 30, and outputs key code data through diodes D2-05, for example. Next, the master clock Q is applied from the master clock generator 1 to the monostable multipipe layer (MMI) 11, and the delayed clock is applied to the monostable multipipe layer (MMI) 11.
MMI) 11. The output Q of the monostable multipipulator (MMI) 11 and the output "1" of AND4 are input to AND5, and AND5 outputs a latch pulse of key code data. Furthermore, the Q of master clock generator 1 is
The output is input to AND6 through AND7. AND
The output “1” of BND4 is input to 6, and the master clock Q output is input to T of flip-flop (FF2) 23.
input to the terminal. The flip-flop (FF2) 23 uses a JK flip-flop, and now the J terminal receives the output Q of the flip-flop (FFI) 22, which is "1", and the K terminal receives the output Q of the flip-flop (FFI) 22, which is "0". Flipflop (FF2) 23 is a mask. It is set at the rising edge of the TsukQ output. As a result, the Q output of the flip-flop (FF2) 23 becomes "0", and AND1, AND2, AND3, OR1, AND4, A
The outputs of ND5, OR2, and AND6 become "011", stopping key code generation and canceling the inhibition and standby for other key code generation circuits.Next, when the key switch (Swi) 21 is opened, the flip-flop (FFI) 22 is reset by the rising edge of the Q output of the master clock.

As a result, the Q output of the flip-flop (FFI) 22 becomes "1", and the flip-flop (FFI)
)22 Q output '11' and flip-flop (FF2)
23's Q output "1" is input, and as a result "1" is output. Based on this output, "1" is input to the similar line (12) 24 of another key code generation circuit, thereby prohibiting key code generation by key depression and putting it on standby. The AND3 output is input to ORI, and ORI outputs "1". At the same time, the same circuit 2p (2, ≦2p<2i) above the key code generation circuit 2i
If the key is not in the released state, "0" is input to line (12) 25, which is inverted and "1" is output. ORI for AND4
Each output "1" of the line (12) 25 is inputted and "1" is outputted, so that OR2 outputs "1". This prohibits key code generation in the circuits 2i+, .about.2n below the key code circuit 2i and puts them on standby. Further, the output of AND4 is inputted to a diode matrix 301, and data obtained by encoding, for example, 8 bits corresponding to the key code N through a line 26 with diodes D2 to D5 is output. Along with this, the monostable multipipulator (MMI) output Q and AN
The output "1" of D4 is inputted to AND5, and output from the key code data latch pulse line 27 through diode D6. Further, the output "1" of AND4 is inputted from the Q terminal of the master clock generator 1 to AND6 via AND7, which will be described later, and the Q output of the master clock is inputted from AND6 to the T terminal of flip-flop (FF2) 23.

The J terminal of this flip-flop (FF2) 23 receives the output Q of the flip-flop (FFI) 22 as "0", the K terminal receives the same output Q as "1", and the master clock Q output of the flip-flop (FF2) 23 is input. It is reset at the rising edge of , and the output Q of the flip-flop (FF2) 23 becomes "0" and the outputs of AND1, AND2, AND3, OR
The output of 1, AND4, AND5, OR2, AND6 is “
0'', the key code generation is completed and the prohibition standby for other key code generators is released.If two or more key switches are pressed next to each other at the same time, a key code generation circuit is installed in each key switch stage. Similar AND3, line (1,)
24, the main key always has priority over the pressed key, and the key code generation is OR2, line (12) 25, AND4 as above.
The configuration gives priority to treble.

When two or more keys are pressed and a key is pressed at the same time as a key, the highest key is always given priority in generating a key code, and even among the adjacent keys, the high key is given priority as described above.

Since key codes are generated sequentially based on such priority order, confusion does not occur. The key code data outputted from these key code generation circuit groups is also applied to the key code storage device group shown in FIG.

This key code memory device 3i includes a latch pulse circuit 31 and a coincidence circuit 32, each of which inputs data in parallel.
Other FF clocks are flip-flops (FF3) 3
3, and a latch pulse is applied to the latch circuit 31 via the latch inhibit circuit 4i. FIG. 3 shows the timing of each clock and data. FIG. 2 shows a key code storage device corresponding to one channel, and this embodiment has 10 channels of an equivalent device.

It has an lq circuit with key code memory 3i, the key code data and FF clock are input in the same way to each channel, and the latch pulse is ANDIO in the 1st channel.
from the next channel, the output of AND9 of the previous channel is input to AND8, A
Input to ND9.

The outputs of the matching circuits 32 of each channel are respectively input to the NORI of the latch control circuit 4i. The key code data sent by pressing the key is shown by the waveform of e in the same figure in response to the master clock in FIG.
Written to 1. Now the key switch (SWi) shown in Figure 1
) 21 is pressed, key code data is output from the key code generation circuit group 2i. Data is input to the latch circuit 31 and the match circuit 32 in parallel, and the respective parallel outputs are input to the OR gate (OR3) 34 to output "0", which is then input to the D type flip-flop (FF3) 33. It is input to the D terminal, and its Q output outputs "1". Next, "1" of the output Q of this flip-flop (FF3) 31 is input to AND8, and the latch pulse is
It is input via NDIO and its output is given to the latch circuit 31. This causes the key code data to be transferred to the latch circuit 31.
is latched to. When the key code is latched, OR3
)34 outputs “1” and flip-flop (FF3)
Given to 33. Flip-flop (FF3) 33 is set by master clock Q and outputs Q output "1". Further, the Q output becomes "0" and the input of the latch pulse to the latch circuit 31 is prohibited by AND8.
Furthermore, the Q output of flip-flop (FF3) 33 is “1”
is applied to AND9, which outputs the next latch pulse. The output of AND9 is input to a similar AND8 of the next channel. Furthermore, flip-flop (
The output Q of the FF3) 33 is input to a coincidence detection circuit 32 to detect a coincidence between the next sent key code data and the latched key code. In other words, Key Switch (SWi)2
When 1 is the key, the coincidence detection circuit 32 outputs a coincidence output from the key code data outputted from the key code generating circuit group 2i. As shown in the latch control circuit 4i that prohibits the same key code from being latched to other channels at this time, the coincidence output of the coincidence detection circuit 32 is
RI) 41, its output is input to ANDI0, and the latch pulse is sent to the key code storage device 3i via AND8.
input to the latch circuit 31 is prohibited. Furthermore, the latch circuit 31 is reset by the coincidence output of the coincidence detection circuit 32. When reset (OR3) 34 becomes ''0
” is output, the flip-flop (FF3) 33 is reset by the master clock Q, the Q output becomes “0”, the Q output becomes “1”, and the next latch pulse AND8 outputs it, and AND9 inhibits it and does not send it to the next channel. When the key code is latched in this way, the latch pulse is applied from AND9 to AND8 of the next channel, and the next channel operates in the same way.Now, if the key code storage device group has 10 or more channels, the latch pulse is applied from AND9 to AND8 of the next channel. If the switch 21 is pressed, that is, if further key code data is output when there is no empty channel,
This key code data overflows and must be continued to be output until an empty channel is available.

Therefore, in this embodiment, the arbor-flowed latch pulse is applied to the monostable multipipulator (MM2) 12 shown in FIG. By prohibiting input to the terminal and not changing the state of (FF2) 23, the overflow signal is output once until an empty channel is created, for example, as shown in Figure 3, and the overflow key code is An overflow signal is output every time an overflow occurs, and continues to be output until the overflow is eliminated. At this time, when generating a key code using the Shigeru key, as described above, an empty channel is first created using the Koji key in order to give priority to the pressed key, and then an overflowing key code is generated again.

In the above embodiment of the present invention, a case has been described in which the key code storage device group has 10 channels, but the key code storage device group is not limited to this, and an appropriate maximum number of simultaneous sounds may be provided. Note that the parallel PCM output from the key code generation circuit
It is also possible to easily reduce the number of output lines as data as serial PCM data, and this can be achieved by adding a simple serial-to-parallel conversion circuit between the key code generation circuit group and the key code storage device.

It is clear that the clock frequency in this case corresponds to the number of data bits of the clock frequency in the above embodiment. As explained above, according to the present invention, the key code is sent when the state of the key switch is pressed and the state of the baby key changes, and the key code data between the clock and the time when the state of all the key switches is simultaneously checked. It only takes time to send a message, and the response is extremely fast.

At the same time, if a change in the state of a key switch is detected, priority is given to the key code output due to key release, and furthermore, the key code output is output in accordance with the determined priority order, and the key switch that is not output is maintains the status change, waits, and outputs key codes in order of priority. For example, as shown in the embodiment, priority is given to high-pitched sounds in order to improve prompt response to high-pitched sounds. The key code data is, for example, an 8-bit parallel PCM signal, and one clock pulse is enough to output the key code, so even if one crab is pressed at the same time, if the clock frequency is set to NaHZ, the clock frequency will be 101/1/ The response time is much longer than that of the slave scanning method, and the clock frequency is also extremely low. In the case of the present invention, the problem of the time lag between key presses and key keys caused by scanning the slave key switch to perform key assignment is also solved, and a key assigner with a simple configuration and high responsiveness can be realized. It is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a key code generation device according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of a key code storage device connected to the key code generation circuit of FIG. 1, and FIG. 3
The figure is a time chart showing the operation of the above embodiment of the present invention, in which 1 is a master clock generator, 2i is a key code generation circuit, 3i is a key code storage device, 4i is a latch control circuit, 11, 12 is a monostable multipipulator,
21 is a key switch, 22, 23, and 33 are flip-flops, 30 is a diode matrix, 31 is a latch circuit, 32 is a coincidence detection circuit, 34 is an OR gate, and 41' is a gate. Figure 1 Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1. A master clock generator that supplies a master clock to each key switch in parallel to simultaneously detect changes in the state of key depression and release of each key switch, and a first memory that stores the state of the key switch in the first half of the master clock. a second memory circuit that stores the output of the first memory circuit in the second half of the master clock; a change that detects a change in the state of key press and release of each of the key switches based on the outputs of the first and second memory circuits; a detection circuit, means for generating a key code corresponding to the key switch based on the output of the change detection circuit, means for outputting a latch pulse from the master clock and the key code, and a second memory based on the output of the master clock and the change detection circuit. A key switch generating circuit group comprising means for resetting the circuit to complete output generation, respectively, corresponding to a plurality of key switches; The key code generation circuit sequentially generates a key code using a master clock starting with the high priority key code generation circuit according to the order of priority, temporarily prohibits the output of the low priority change detection circuit, and waits for key code generation, and also controls the release of the key switch and other functions. A key assigner comprising a first control circuit for prohibiting key code generation due to key depression and giving priority to key release in the case of simultaneous key depression operations of a key switch. 2. A mask clock generator that supplies a master clock to each key switch in parallel in order to simultaneously detect changes in the state of key depression and release of each key switch; a first memory circuit that stores the state of the key switch in the first half of the master clock;
a second memory circuit that stores the output of the memory circuit in the second half of the master clock; a change detection circuit that detects a change in the state of a key press/release of each of the key switches based on the outputs of the first and second memory circuits; means for generating a key code corresponding to the key switch by the output of the detection circuit; means for outputting a latch pulse from the master clock and the key code; and means for resetting a second memory circuit by the output of the master clock and the change detection circuit. A key code generating circuit group comprising key code generating circuits each comprising means for completing output generation corresponding to a plurality of key switches; A key code generating circuit is generated sequentially by a master clock from a key code generating circuit at the same time, and a means for temporarily inhibiting the output of a low priority change detection circuit and waiting for key code generation is provided. a first control circuit for prohibiting key code generation due to key presses and prioritizing key release in the case of simultaneous operations; and a third storage circuit for storing key codes output from the key code generation circuit group; a coincidence detection circuit that compares the stored key code and the key code output from the key code generation circuit group and outputs a match; a key code is stored in the third storage circuit by the output of the coincidence detection circuit; A key assigner comprising a key code storage device group comprising a circuit for detecting the latch pulse and a second control circuit that operates to prohibit the application of the latch pulse to the third storage circuit and apply it to the next channel. 3. A master clock generator that supplies a master clock to each key switch in parallel to simultaneously detect changes in the state of key presses and release of each key switch; a first memory circuit that stores the state of the key switch in the first half of the master clock; a second memory circuit that stores the output of the memory circuit in the second half of the master clock; a change detection circuit that detects a change in the state of the key press/release of each of the key switches based on the outputs of the first and second memory circuits; means for generating a key code corresponding to the key switch by the output of the detection circuit; means for outputting a latch pulse from the master clock and the key code; and means for resetting a second memory circuit by the output of the master clock and the change detection circuit. A key code generating circuit group comprising key code generating circuits each comprising means for completing output generation corresponding to a plurality of key switches; The master clock generates key codes sequentially from the key code generating circuit of the second level, and temporarily prohibits the output of the low priority change detection circuit.
Means for waiting for key code generation, and first method for prohibiting key code generation due to key depression and giving priority to key release in the case of simultaneous operation of key release of one key switch and key depression of another key switch.
a third storage circuit for storing the key code output from the key code generation circuit group; and a third storage circuit for storing the stored key code and the key code output from the key code generation circuit group. A coincidence detection circuit that compares and outputs a coincidence, a circuit that detects that a key code is stored in the third storage circuit by the output of the coincidence detection circuit, and a circuit that prohibits applying a latch pulse to the third storage circuit. A key code storage device group consisting of a second control circuit that operates to apply data to the channels of the key code storage device is provided, and furthermore, when key switches greater than or equal to the number of channels of the key code storage device are pressed, the key code data that is not stored is stored again. A key assigner characterized by being equipped with a circuit that controls continuous output.