JPS6027040B2 - key code generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key code generating device having means for time-divisionally sending and storing key switch data input to a group of key code generating circuits.

In a counterfeit machine having a large number of key switches such as an electronic organ, if each switch is directly connected to a circuit in order to supply switch opening/closing information to a desired circuit, the amount of wiring becomes enormous. Therefore, a time division multiplexing method has generally been used in which each key switch is scanned in a time division manner to send open/close information to a key code storage device as a TDM (time division multiplex) signal or a PCM (pulse code modulation) signal. However, in this method, since the state of the pressed key and the chick key of the key switch is checked in a time-sharing manner, information about the key switch that is not pressed is also sent, and one scanning period is required to send the necessary information. In order to improve the prompt response to the scale key and the iso key, a very high frequency clock, for example, several hundred kilohertz, was required. In addition, the response time may deviate depending on the relationship between the pressed key and one scanning period at the time of the chick key. For example, if a pressed key switch is released immediately after scanning, the response time will deviate by about one scanning period. In order to improve these problems, the applicant of the present invention has proposed a new key assigner in a separate application.

That is, as will be described in detail in the embodiments, a key code generator is used, and the key code is sent when the state of a key switch changes, not by scanning each key switch. In this case, only a clock to simultaneously check the status of all key switches and time to send the key code data are sufficient, and the system is characterized by a low clock frequency and high prompt response. However, the number of input lines input from the key switch is equal to the number of key switches. When integrating these circuits, the number of pins of the semiconductor device is limited, so it is necessary to reduce the number of lines input from the key switch as much as possible. An object of the present invention is to reduce the number of input/output lines without impairing the characteristics of the key code generator.

In order to achieve the above object, the key code generator of the present invention includes a first memory circuit that stores the state of each key switch in the first half of the first clock, and an output of the first memory circuit that is stored in the first half of the first clock. A second memory circuit that stores data in the second half, the first
, a change detection circuit for detecting a change in state of a pressed key of a key switch based on the output of a second memory circuit; means for generating a key code corresponding to the key switch based on the output of the change detection circuit; and the first clock. and means for outputting a latch pulse based on the key code, and means for resetting the second storage circuit using the first clock and the output of the change detection circuit to complete output generation. A key code generation circuit group provided corresponding to a plurality of key switches, and an output of the change detection circuit in the key code generation circuit group according to a predetermined priority order,
Means for sequentially generating key codes from the high-priority key code generation circuit using the first clock, temporarily prohibiting output of the low-priority change detection circuit to wait for key code generation, and a key switch. In a key code generator equipped with a control circuit for prohibiting key code generation due to key presses and giving priority to the Iso key in the case of simultaneous operation of key release and key press of another key switch, input to the key code generation circuit group. An m×n key switch matrix circuit composed of a plurality of key switches, a core key switch matrix circuit, transmits key switch information for each octave to a first clock using a low-speed synchronous or asynchronous second clock. m time-division transfer means, and n pieces of the key code generation circuit group are set as one block.
It is characterized by comprising a time division device consisting of a control circuit that sequentially stores data in blocks at a low speed.

That is, since the above-mentioned key code generation device is equipped with a storage device that stores the open/closed state of the key switch, it is suitable for time-sharing use, and time-sharing does not interfere with key code generation.

Roughly speaking, considering the tolerance of the clock frequency of this key code generation loop, the time required to generate a key code for each pressed key does not pose any problem at all in terms of time delay during time division. In this way, the number of input/output lines can be effectively reduced without looking at any characteristics of the key code generator. The present invention will be described in detail below with reference to examples.

FIG. 1 is a schematic explanatory diagram showing the configuration of an embodiment of the present invention.

In the figure, the key switch matrix 2 is (m, n
) matrix, and the key data is sequentially output n bits at a time in m minutes by the time division clock 1 and given to the key code generation circuit group 3. Similarly to the key switch matrix 1, the key code circuit group 3 is composed of m blocks, where n key code generating circuits are one block. The time division clock circuit 1 is composed of a ring counter or a shift register to which a clock a is applied from a clock source. This ku. Let the clock frequency be a. Furthermore, the clock b of frequency Nb applied to the memory circuit of the key code generation circuit 3 is ANDed with the clock a of frequency A by the gate 11 from the clock source and distributed to each block. In this case, clock B is synchronized with clock a. Alternatively, in order to satisfy the sampling theorem, the clock may be an asynchronous clock such as mebZ2naa.In the case of the embodiment, clock a and clock b may be the same clock from the viewpoint of lowering the clock frequency. It is assumed that the frequencies are synchronized.This time-divided key data is used to sequentially write the open/closed state of the key switch for each block of the key code generation circuit group 3 into its memory circuit.By this key data detection, The key code generation circuit 3 sequentially outputs key code data according to a preset priority order, regardless of the time division clock.Figure 2 shows the configuration of the key switch matrix 2, which is composed of m and n matrices. configured.

That is, it is scanned from n to nn by the time division clock a, and the output n bits are output in a time division of m minutes. If the switch SWi-j is pressed now, "1" is output to the output nj at the time of time slot i, that is, at the time of mi scanning. This is simultaneously input to the key code generating circuit Ki-j of block i of the key code generating circuit group consisting of n blocks. FIG. 3 shows a typical key code generation circuit (encircled by a broken line) for the key code generation circuit of the embodiment shown in FIG.
KH)3 is shown.

If the switch matrix SWi-j is now pressed, "1" is input to the ○ terminal of the D-type flip-flop (FFI) 21 at time slot i. At the same time, gate 11 is connected, clock b is input to the T terminal, and Q output of (FFI) 21 outputs ``1''. Output Q of JK type flip-flop (FF2) 22.
is "1", and since the Q output "1" of 〇FI) 21 and the Q output "1" of (FF2) 22 are input to ANDI, it outputs "1". At this time, if no key code is generated by the koji key in other key code generation circuits, other similar AND3 outputs "0", and the diode D is mutually output.
The connected line (1,) 24 outputs "0". AND2 receives the output of ANDI and the inverted output "1" of line (1,) 24, and outputs "1". The AND2 output is input to ORI, and ORI outputs "1". At this time, at the same time, the same circuit Kp- above the key code generation circuit Ki-j
If q (KM≦Kp-q<KH) is released and the key is not pressed, the wires (12) and 25 connected to each other through an inverter are set to "0".
is input, and therefore "1" is input to AND4. AN
D4 receives ORI and the output "1" of line (ra) 25, and outputs "1" as a result. The AND4 output is input to OR2, and OR2 outputs "1". As a result, generation of key codes at the key switches below the key code generating circuit Ki-j is prohibited and placed on standby. Next, JK type flip-flop (FF2) 22 is AN with J being “1” and K being “0”.
It is set by the clock input to D6, and (F
The Q output of F2) 22 becomes “0” and AND1, AN
D2, AND3, OR1, AND4, AND5, OR2
, AND6 becomes "0" and stops key code generation, canceling the inhibition and standby for other key code generation circuits. Next, when the key switch matrix SWi-i leaves, the flip-flop (FF
``0'' is input to the D terminal of I) 21, and at the same time, the gate 11 is opened and clock b is input to the T terminal of the i block, and the Q output of the flip-flop (FFI) 21 becomes ``1''.

The Q output of the flip-flop (FF2) 22 is outputting ``1'', so these two outputs are connected to the input AND3.
outputs “1”. AND3 output is input to ORI and O
RI outputs "1". The output of AND3 is connected to the similar line (1,) of the other key code generating circuits so that all key code generating circuits K, -j are prohibited from generating key codes by pressing keys.
Enter "1" in 24. Furthermore, key code generation circuit K
The same circuit Kp-q (K, -, SKp-q<
If no key code is generated in line (Ki-j), line (1
2) "0" is input to 25, which is inverted and outputs "1". ORI and each output "1" of the line (12) 25 are input to AND4, and "1" is output. Similar to when a key is pressed, the output "1" of the AND4 causes the key switch code of the i-i stage to be inputted to the diode matrix 30, and the line 26 corresponds to the key code. For example, data obtained by encoding 8 bits with diodes D2 to D5 is output. At the same time, the output Q of the monostable multipipulator (MMI) and the AND4 output "1" are input to AND5, and output from the key code data latch pulse line 27 through the diode D4. Further, the AND4 output inputs "1" to the key switch line (12) 25 below the input Ki-j to OR2, and therefore the output is inverted and becomes "0", thereby inhibiting key code generation. Next, the flip-flop (FF2) 22 is reset by the clock input to ANG6 with J being "0" and K being "1", and the output Q of (FF2) 22 is "0".
becomes. This completes key code generation. Furthermore, when key codes are generated by pressing keys and machine keys at the same time, the AND3 output is input to the line (12) 24 of all key code generation circuits, and priority is given to key code generation by key codes. Furthermore, OR2 is generated by AND4 output.
is inputted to the line (12) 25 of the lower key code generation circuit through the key code to give priority to higher notes, for example, high notes, and key codes are output in accordance with this priority order.

FIG. 4 shows a time chart of an embodiment of the present invention.

In other words, the key switch matrix is (m, n) = (6
, 12), and the key code generation circuit is provided corresponding to a 6-block key switch in which 12 circuits constitute one block. Further, the clock b is a negative logic output of the clock a, and the state of the key switch is stored in synchronization with the clock b.

The clock input to the T terminal of flip-flop (FF2) 22 is the same as clock a. These clocks a are shown by waveform CIa in figure a, and clock b is shown by waveform CIb in figure c. Figure b shows time-division time slots when m=6. Now, the three key switches SW2-, SW2- shown in FIG.
2. Assume that SW3-2 is pressed and the adjacent key is pressed as shown. In this case, both SW2- and SW2-2 belong to time slot 2, and are pressed at the same time.
-2 belongs to time slot 3 and is pressed with a slight delay. The timing of these key releases is different. These key codes correspond to the respective time slots m2 and m3 in Figure b.
It is controlled by gate output pulses G2 and G3 shown in FIG. 2D, which are generated by clock b in FIG. Furthermore, in the case of simultaneous key presses, high notes are given priority. Therefore, as shown in the figure, the key code output is S first when a key is pressed.
W2-, is outputted by the pulse of ○2 immediately after that, then SW2-2 is outputted with a delay of one time slot depending on the priority order, and finally SW3-2 is outputted with a further delay of one time slot. In the case of key release, SW2-, first outputs in response to the G2 pulse immediately after the Koji key, and then SW2-, outputs in response to the G2 pulse immediately after the Koji key.
2-2 and SW3-2 are output in accordance with the order of G2 and G2 immediately after the machine keys, respectively.

By configuring key code output in this way, there is no difference in the timing of key press and release, and there is no large difference as with the conventional scanning method, making it possible to generate key codes with excellent prompt response. be. As explained above, according to the present invention, compared to the conventional scanning method, the clock frequency is low, the quick response is high, and the deviation in response time is small. By connecting it to a group of code generation circuits and using it in a time-sharing manner, the number of input/output lines can be reduced.

In other words, the number of input/output lines is m×n when the points of the matrix configuration mxn are directly connected, but it can be reduced to m+n when time-division is performed. Also, the maximum time it takes to output a key code is (X + 1) x 100 microseconds if the clock is 100 microseconds when there are x key switch state changes at the same time without time sharing. On the other hand, in this example, the maximum (m
+×+1)×100 microseconds, and the response time is slightly extended depending on the number of time divisions m.

However, m reduces the number of input and output lines. For example, the number of input and output lines for a 25-needle key switch is m = 8, n = 3.
2 is 8x323256, so 832 = 4 stops will be sufficient. In this case, m=8, and it is clear that the responsiveness will not deteriorate so much by time division. Also, in order to achieve the same response speed, m+X
+ IX longevity ÷ 11 times 1 koku. This is also accomplished by X+1.

One of the characteristics of the key code generation method applied to the present invention is that it uses a low clock frequency, so even if this frequency is slightly increased, there is hardly any problem.

[Brief explanation of the drawing]

FIG. 1 is a schematic explanatory diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the key switch matrix of the embodiment of FIG. 1, FIG. 3 is a detailed diagram of the key code generation circuit of the embodiment of FIG. 1, and FIG. 4 is a time chart of the embodiment of the present invention. ,
In the figure, 1 is a time division clock, 2 is a key switch matrix, 3 is a key code generation circuit, 11 is a gate, 21, 2
2 is a flip-flop, and 30 is a diode matrix. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 a first memory circuit that stores the state of each key switch in the first half of the first clock; a second memory circuit that stores the output of the first memory circuit in the second half of the first clock; a change detection circuit for detecting a change in the key press/release status of a key switch based on the output of a second memory circuit; means for generating a key code corresponding to the key switch based on the output of the change detection circuit; A key code generation circuit comprising means for outputting a latch pulse based on a key code, and means for resetting the second memory circuit using the first clock and the output of the change detection circuit to complete output generation, is connected to a plurality of key switches. According to a predetermined priority order of the outputs of the change detection circuits in the key code generation circuit groups provided corresponding to the key code generation circuit groups, the key code generation circuits are sequentially set by the first clock, starting from the key code generation circuit with the highest priority. Means for generating a key code, temporarily inhibiting the output of the change detection circuit of low priority, and waiting for the generation of the key code, and in case of simultaneous operation of releasing a key switch and pressing a key of another key switch. In a key code generation device equipped with a control circuit for prohibiting key code generation and giving priority to key release, m×
n key switch matrix circuits; means for transmitting key switch information for each octave from the key switch matrix circuits in m time-division manner using low-speed synchronous or asynchronous independent first clocks with respect to the first clock; 1. A key code generation device comprising a time division device comprising a control circuit that sequentially stores data at low speed in m blocks each consisting of n key code generation circuits.