JPS6021440B2 - amplifier circuit - Google Patents

Description

Detailed Description of the Invention The present invention relates to an insulated gate field effect transistor, mainly a MOS crab field effect transistor (hereinafter referred to as MOST).
The present invention relates to a circuit configured by the above, and particularly to a circuit that amplifies a minute difference signal and obtains a binary output.

Although the following explanation will be made for an N-channel MOST, it is essentially the same for a P-channel MOST or other insulated gate field effect transistors.

Dynamic memory using MOST is required to be faster, and MOS memory circuit input signals other than clock signals are required to have a TTL level (0.4 to 2.4V), which is smaller than the MOS level (12V). Therefore, it is necessary to convert it to MOS level.

On the other hand, as memories have become larger in capacity, single-transistor memory cells with the smallest memory cell area have been used, but when a single-transistor memory cell is depleted, the binary signal stored in that cell is , that is, "1",
“0” information is 0.1 to 0. A different level of 4
・Only small potential changes occur, and therefore an amplifier circuit is required to amplify this minute signal. Conventionally, a circuit shown in FIG. 1 has been used as a circuit for amplifying such a small signal.

That is, the amplifier circuit 1 includes switching transistors Q,
and Q3, and load transistors Q2 and Q. The flip-flop outputs 2 and 3 are connected to the digit lines 4 and 4' of the memory circuit, respectively, and their load capacitances are made equal. When cell 5, which is one of the memory cells connected to digit line 4, is read out, memory cell 5' connected to digit line 4' is not read out, and instead, the memory cell 5' connected to digit line 4' is A reference potential intermediate between cell information "1" and "0" is generated on digit line 4'. Conversely, when the cell 5' connected to the digit line 4' is read out, a reference potential is generated on the digit line 4 by the reference voltage generating circuit 6. In Figure 2, both digit lines 4,
4' waveform is shown. The operation of the circuit shown in FIG. 1 will be described below using the waveforms shown in the same figure.

Digit lines 4, 4' are precharged by transistor method by clock J3 and by transistor Q6, respectively, to equal levels at a certain point in time. Note that the transistor Q7, to which the clock ◇3 is applied, improves the efficiency in which the digit lines 4 and 4' are at the same level, and is necessary if the precharge clock signal J3 is sufficiently higher than the precharge level. I don't. Time t
, after the precharging is completed and the clock ◇3 goes to a low level, the address signal causes, for example, the address line 7
When selected and becomes high level, information in the memory cell 5 is read out. When the address line 7 becomes high level, charge is exchanged between the digit line 4 and the memory cell 5, and a change in potential appears on the digit line 4 in accordance with the information "1" or "0" of the cell. On the other hand, digit line 4'
is the cell information “1”, “0” by the reference voltage generation circuit 6'.
An intermediate potential is given. As a result, a potential difference of about 0.1 V occurs between the digit lines 4 and 4' before the time. When the clock signal is set to a high level and the amplifier circuit 1 is activated by the transistor Q8, the charges on the digit lines 4 and 4' are discharged through the transistors Q, Q3, respectively. Since there is a slight potential difference between the transistors Q and Q3 as described above, there is a difference in the on-resistance of the transistors Q, Q3. Now, if digit line 4 is higher, the resistance of transistor Q is smaller, and therefore the potential of digit line 4' becomes lower level more quickly. As a result, the on-resistance of transistor Q becomes increasingly large, further slowing down the potential drop of digit line 4, and amplifying the potential difference between the digit lines. As a result, the time t between the output nodes 2 and 3 of the flip-flop
A large potential difference occurs at 3. Therefore, at the time, the clock 02 is set to high level, and the digit line 4, which has become low, is set to high level again by the load transistor Q2.
Digit line 4' can be kept low. still,
Although the clock signals 02 and 02 have been explained separately, they can also operate with the same signal. In the amplifier circuit of FIG. 1, a DC current always flows through the transistor Q2 or Q4 while the clock 2 is at a high level.

Therefore, providing such an amplifier circuit for each digit line consumes a large amount of power. Furthermore, the transistor Q,,
It is also necessary to take a large ratio between the size of Q and the size of transistors Q2 and Q4. These are major drawbacks of this amplifier circuit. In addition, in this circuit example, it is also possible to make the common source connection point of transistors Q and Q common to multiple amplifier circuits, and to use only one transistor Q for activating the amplifier circuits for multiple amplifier circuits. It is. Furthermore, in this circuit, the digit line 4 is connected to the node 2 with a large stray capacitance together with the gate of the transistor Q3, so the effective capacitance of the digit line 4 is amplified, and this digit line is effectively It is difficult to cause potential changes.

In other words, the effective read sensitivity of the memory cell is reduced. The same applies to digit line 4'. An object of the present invention is to provide an amplifier circuit with low power consumption.

Still another object of the present invention is to provide an amplification circuit capable of amplifying minute difference signals.

Another object of the present invention is to provide an amplifier circuit suitable as a sense amplifier for a memory circuit having a one-transistor memory cell as a memory element.

The amplifier circuit according to the present invention includes a first transistor for amplification, a second transistor connected between the gate of the first transistor and a reference potential, a signal line, and a connection between the signal line and the second transistor. means for following the gate of the transistor; a third transistor connected between the signal line and the reference potential; and means for connecting the gate of the third transistor and the gate of the first transistor. It is characterized by having the following.

More preferably, the amplifier circuit is used as a sense amplifier of a memory circuit that uses a one-transistor memory cell as a memory element.

According to the present invention, since there is no direct current path in the amplifier circuit, there is no power consumption and dynamic operation is possible.
It becomes possible to use a radioless circuit, and therefore the area occupied on the integrated circuit of the MOST constituting the circuit can be reduced.

Hereinafter, the present invention will be described in detail using examples in order to better understand the present invention. The above-mentioned insulated gate field effect transistor used in the present invention has a source, a drain, and a control, ie, gate, electrode, but the source electrode may be used as a drain electrode, or the drain electrode may be used as a source electrode. Even if used as , it is equivalent and does not limit the present invention in any way.

FIG. 3 is a circuit diagram showing still another embodiment of the present invention.
Of the transistors constituting the flip-flop, the sources of the load transistors Q2 and Q3 are both applied with a flip-flop activation clock signal ◇, and the sources of the switching transistors Q, Q are both grounded. The signals on input lines (digit lines) 4 and 4' are input to the gates of transistors Q, 6, Q, and 7, respectively, and the drain outputs of transistors Q, 6, Q, and 7 are grounded to flip-flop outputs 3 and 2, respectively. ing. Also, the sources of Q, 6, Q, and 7 are all grounded. The input lines 4, 4' are further connected to transistors Q. 8, Q, 9 and grounded through Q, 8, Q. At the gate of 9, there is Flipf. Outputs 3 and 2 of the tup are respectively input. The operation of the circuit shown in FIG. 3 will be explained using the variant shown in FIG. By time t, nodes 8 and 9 are precharged to the same potential by clock signal 03.

Since the clock signal ◇, is at a low level and nodes 8 and 9 are precharged and at a high level, the transistor Q2
, Q4 are in the ON state, and nodes 2 and 3 are at the same low level as the clock signal G. If at least one of inputs 4 and 4' is a signal with a potential exceeding V of MOST, then when clock signal 0 changes to a high level, node 2
, 3 tries to reach a high level. However, input 4,4'
If there is a slight potential difference between the transistors Q, 6, Q, 7
Since there is a difference in the ON resistance of the two nodes, there is a difference in the speed at which the node 2.3 reaches the high level.

If input 4 is at a higher level than input 4', node 2 will be at a higher level than node 3, and transistor Q3 will be turned on earlier. For this reason, the potential difference between the nodes 2 and 3 increases further, and when the difference exceeds VTH at a certain time, the transistor Q is turned on and the electric charge at the muscle point 9 begins to be discharged. On the other hand, transistors Q, . is in the oR state because the source potential is higher than the gate potential, and as a result, there is a difference in the ON resistance of transistors Q2 and Q4, and node 2 goes to a higher level, but node 9 is discharged and transistor Q4 is in the OFF state. Therefore, the clock signal 0,
No current flows from to contact 3. Therefore, a signal obtained by amplifying the minute level difference between the inputs 4 and 4' is output to the flip-flop outputs 2 and 3. Here, as mentioned above, when both inputs 4 and 4' are at a high level, that is, at a level higher than the VTH of MOST, and for example, when the input 4 side is high, the output 2 of the flip-flop has a high level.
A low level is generated at output 3, but if a level higher than V of MOST is still applied to input 4',
Transistor Q, 7 maintains the ON state, so that node 2
Since the charge will be discharged through the transistor Q, 7, the transistor Q, 9 with a high level applied to its gate forces the input 4' to a low level, cutting off the above-mentioned discharge path. It is for.

Therefore, in a circuit system in which inputs 4 and 4' are both at a low level thereafter, transistors Q, 6, Q, and 9 are unnecessary, and even if input 4' is at a level lower than VTH in the above example, transistors Q, 6, Q, and 9 are unnecessary. Similarly, transistor Q. 5, Q, and 9 are no longer necessary. In this embodiment, input signal lines 4, 4' are connected to the gates of transistors Q, 6, Q, 7 and transistors Q, 8, Q,
Since it is only tangent to the drain of line 4,
4' capacity can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a sense amplifier section in a conventional memory circuit, FIG. 2 is an operating waveform diagram of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. The operating waveform diagrams of the circuits in Figure 3 are shown respectively. In the figure, Q,,Q3,Q9 and Q, . are switching transistors, Q2, Q, Q,. and Q and 2 are load transistors, 2 and 3 are flip-flop outputs, and 4 and 4' are digit lines, respectively. *
'Fig. 2. Younger brother 3. Fig. 4.

Claims (1)

[Claims] 1 first and second field effect transistors constituting a flip-flop, first and second input nodes,
the first input node and one end of the first transistor and the second
means for connecting the second input node to one end of the second transistor and the gate of the first transistor;
a third terminal whose ends are connected and whose gate is connected to the first input terminal;
a fourth field effect transistor having a gate connected to the first input node and one end connected to the first input terminal; and a fourth field effect transistor having one end connected to the second input node and having a gate connected to the second input node. a fifth field effect transistor each connected to the input terminal; and a sixth field effect transistor each having a gate connected to the second input node and one end connected to the second input terminal. Amplification circuit.