JPS6032985B2 - Fixed memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fixed memory circuit, and in particular to a bipolar vertical transistor constructed of a monolithic integrated circuit using bipolar transistors, in which a collector is connected to a word line and an emitter is connected to a bit line. A fixed memory circuit (so-called P
-ROM).

In the fixed memory circuit of the above type, there is no electrical connection between the word line and the bit line for all bits before writing.

That is, before writing, the junction of the transistor serving as a memory cell is not destroyed, so there is no conduction between its collector and emitter. Therefore, in this memory circuit, it has been impossible to check for disconnections during the manufacturing process. Therefore, if there was a disconnection defect in the word line, bit line, or between these and the collector or emitter, it could only be found and revealed that it could not be programmed with the write program mainly performed by the user. . The present invention has been made in order to provide a fixed memory circuit having the above-mentioned structure, which is capable of performing a disconnection check on all the bits before writing in the fixed memory circuit. This invention has 12 memory cells.
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The structure is such that the transistors that make up the memory cells can be turned on and off by the injector.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram of a memory cell that is an embodiment of the present invention.

The collector of this circuit is connected to the word line Wo,
An npn bipolar transistor Q, whose emitter is connected to the bit line Bo, and a pnp transistor Qi, whose base is shared with the collector, and whose emitter is connected to the control terminal INJ. A memory cell is formed by the two connected to the memory cell.

The transistor Q, has a vertical structure, and the transistor Q,' is a 12-structure transistor having a horizontal structure. The emitter of the npn transistor constituting the memory cell is common to all bits and is connected to the control terminal INJ. FIG. 2 shows a pattern diagram when this circuit is constructed as a monolithic integrated circuit.

In the figure, reference numeral 1 denotes an n-type epitaxial growth layer formed on a p-type substrate, as will be described later, and is a semiconductor region shared as the collector of the transistor Q, and the base of the transistor Q,'. 2 is the collector area 1
It is a p-type semiconductor region formed in transistors Q,
It is used together as the base of the transistor Q,' and the collector of the transistor Q,'.

3 is an n+ type semiconductor region, which is used as an emitter of the transistor Q. 4 is a p-type semiconductor region, which is the emitter of the transistor Q,', that is, the p-type semiconductor region.

This p-injector 4 is provided opposite to the base of the transistor Q, and constitutes a lateral transistor Q,'. In particular, in this embodiment, in order to improve the degree of integration, the transistor Q. It is arranged so that it can be shared as an emitter for ' to Q4'. Bo,
B, is a bit line, formed as the first wiring layer, and contact points C8o, CB,
It is connected to the emitter of each transistor Q, ~Q. On the other hand, Wo, W, is a word line, which is formed as a second wiring layer, and contact points Cwo,
Cw, which is connected to the collectors of the respective transistors Q, to Q4. On the other hand, the injector 4 is connected in the vertical direction using the first self-containing line layer or within the semiconductor region (not shown).

A sectional view taken along line A-B in this pattern diagram is shown in FIG.
With this cross-sectional view, the structure described above will be easily understood. That is, a collector buried layer 6 is formed on a p-type substrate 5, an n-type epitaxial growth layer 6 is further formed thereon, and p-type regions 4, 2 are formed in this epitaxial growth layer 1.
4 is a p-injector and 2 is a base. Furthermore, an n+ type region is diffused and formed in the base 2 to obtain an emitter 3. As a result, the transistor Q,
, Q,' are obtained. A first layer insulating film 7a is selectively formed on the surface of this semiconductor substrate, and aluminum or the like is selectively deposited thereon to obtain a wiring layer constituting a bit line. A second layer of insulating film is formed on this, and the first and second insulating films are selectively removed to form a contact hole for connection with the collector. Word line W made up of a second wiring layer. This is what you get. According to the embodiment described above, in the circuit shown in FIG. 1, even before writing, a predetermined voltage is applied to the control terminal INJ, and the current from the p-injector is used to connect the transistors constituting the memory cell. Q, to Q4 can all be turned on.

Then, by selecting the word line W and the bit line, each bit is inspected to determine whether these transistors are on or not, in other words, whether there is a disconnection or connection failure in each wiring. Can be done.
This inspection makes it possible to ship highly reliable and high quality memory circuits. When used as a fixed memory circuit, by setting the control terminal INJ to the reference voltage (off voltage of transistors Q,' to Q'), it operates as a normal memory circuit.
No inconvenience occurs due to the provision of this testing transistor.

The present invention is not limited to the embodiment described above, and the structure of the memory cell shown in FIG. can be used.

Furthermore, the conductivity types (p or n) of the semiconductor regions constituting the semiconductor element may all be reversed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a pattern diagram thereof, and FIG. 3 is a structural sectional view [1...
...Collector (base), 2...Base (collector), 3
...Emitter, 4...P injector, 5...Substrate, 6...Collector buried layer, 7a to 7c...
...Insulating layer. Kai-Zu Zhu-z series 3 diagrams

Claims (1)

[Claims] 1. A fixed memory circuit that performs writing using junction breakdown of a bipolar vertical transistor as a memory cell whose collector is connected to a word line and whose emitter is connected to a bit line, which constitutes the memory cell. A lateral transistor is provided, the collector region of which is formed by the base region of the bipolar vertical transistor, the base region of which is formed by the collector region of the vertical transistor, and the emitter region of which is coupled to a control terminal. A fixed memory characterized in that conduction of the vertical transistor before junction breakdown is enabled by operation of the horizontal transistor when a control voltage is applied to the control terminal. circuit.