JPS6034271B2 - Programmable ROM - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a P-ROM (Pro-amableReaper) to which memory contents can be written electrically after MOSIC is completed.
dOnlyMemory).

[Prior Art] At present, there are almost no MOS type P-ROMs based on MOSIC.

There is a fuse ROM type of bipolar type,
Among the MOS types, there are only ultraviolet erase type EPROMs such as mask ROMs and MNOS memories, and it is difficult to call them P-ROMs in a pure sense. That is, there is only a type of MNOS memory that is simply molded and cannot be erased by ultraviolet light, that is, an EPROM that can be written only once. However, this type of ROM requires one MOST of M disk 06 and one enhancement type MOST for switching for one bit, so it is difficult to increase the degree of integration.

Furthermore, since "1" and "0" are determined depending on whether MOST is ON or OFF, there is a problem in that the access time is long.

[Purpose of the invention]

The present invention has been made in view of these problems, and an object of the present invention is to provide a P-ROM that does not include a MOST in the memory array, has a high degree of integration, and is capable of high-speed reading.

[Structure of the invention]

In the present invention, a first conductive layer is formed on an island-like region formed on a substrate through a thin insulating film, and a different second conductive layer is provided on this island-like region through a PN junction. Accordingly, an electric field higher than the withstand voltage of the thin insulating film is applied between the island-like region and the first conductive layer to cause dielectric breakdown of the thin insulating film and electrically short-circuit the conductive haze layer and the island-like region. It is something to do.

[Example] Fig. 1 is a plan view of the P-ROM of the present invention, and Fig. 2 is a cross-sectional view taken along the Rolo line. It has a large number of separated N-type regions 2, 2....

In the embodiment shown in the figure, there are three island regions 2, 2, and 3 in each matrix.
The one with ... is shown. 3 is this island-like area 2
, 2... is an insulating film made of silicon oxide film etc. that is attached to the surface of the substrate 1, including the island regions 2, 2..., and most of the island regions 2, 2...
It is covered with insulating films 31, 31, . . . with a large thickness of about 00A, but the remaining parts are covered with thin insulating films 32, 32, .

When the insulating film 3 is made of silicon oxide, it has a dielectric breakdown voltage of about 7 to 10 MV/skin, but a thin insulating film 32 with a thickness of 200 A will cause dielectric breakdown when an electric field of 14 to 20 V is applied.

4, 4, 4 are first conductive layers provided in parallel across the island-like regions 2, 2, 2 in the column direction with at least a portion of the thin insulating film 32 interposed therebetween, and are made of molybdenum, polycrystalline silicon, or the like. It is made of high melting point conductive material.

Reference numeral 5 denotes an interlayer insulating film provided to cover the first conductive layers 4, 4, 4, and is made of an oxide film or the like having sufficient breakdown voltage.

6, 6, 6 are island-like regions 2 in the row direction on this interlayer insulating film 5.
, 2, 2, contact holes 7, 7 formed in the interlayer insulating film 5 and the thick insulating film 31.
. . and reaches even the island-like regions 2, 2, 2, . . . 8, 8... are P-type regions formed by diffusion of P-type impurities introduced from the contact holes 7, 7..., and are island-shaped with these P-type regions 8, 8... Area 2, 2・
... constitutes a PN chain.

Now, for example, the first conductive layer 4 at the rightmost end and the second conductive layer at the bottom end
Let us consider a case where an electric field of 30 V, which is higher than the withstand voltage of the thin insulating film 32, is applied between the second conductive layer 6' and the second conductive layer 6' side, with the second conductive layer 6' being positive.

The electric field passes through the second conductive layer 6', the P-type region 8', and the island region 2', and is applied to the thin insulating film 32' located between this region 2 and the first conductive layer 4'. The insulating film 32' is dielectrically broken down to bring the island region 2' and the first conductive layer 4' into a conductive state. Therefore, the first conductive layer 4' and the second conductive layer 6' meet via the diode D formed by the PN junction between the N-type island region 2 and the P-type region 8. By selectively breaking down the thin insulating films 32, 32, . . . in this way, a logical "1" can be written. Figure 1,
FIG. 2 shows a 3.times.3 bit memory array as a simple embodiment, and FIG. 3 shows a readout circuit for this 3.times.3 bit memory array.

As is clear from the above description, the location where the thin insulating film 32 between the island-like regions 2, 2, and the first conductive layers 4, 4, etc. is dielectrically broken is marked as "1", and the information is "1". A "0" corresponds to a location that is not destroyed, and a "1" location can be represented as a diode D. Therefore, the upper part of FIG. 3 is the memory array MA shown in FIGS. 1 and 2,
The first conductive layers 4, 4, 4 each have a readout switching M
It is connected to the read inverter circuit IN via the OSTs 91, 92, and 93. In addition, DT is each switching MOST
This is a high resistance depression type MOST connected to the collective connection point of 91, 92, and 93. In such a circuit configuration, for example, when reading the bit BI at the upper left end of the memory array MA, a positive potential is applied only to the second conductive layer 61 at the upper end, and the other second conductive layers 62 and 63 are connected to GND. , or OPEN, and only the leftmost switching transistor 91 is turned on.
Then, the input of the read inverter circuit IN becomes "1", and the output signal is "0". Further, for example, when reading the bit B2 at the center of the left end of the memory array MA, a potential is applied only to the second conductive layer 62 second from the top, and at the same time only the switching MOST 91 is turned on. At this time, since the diode D does not exist at the bit B2 position, the first conductive layer 4 on the left end becomes OPEN, but due to the existence of the depletion type MOST (DT), the input of the readout inverter circuit IN becomes "0". ” and “
1" is output. In this way, the contents of the memory array MA can be read out as appropriate. [Effects of the Invention] As is clear from the above description, the present invention does not require transistors as a memory array, so it is extremely efficient. It is possible to obtain a P-ROM with high integration and short access time.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the P-ROM of the present invention, and FIG. 2 is its 0-
3 is a readout circuit diagram of a P-ROM, in which 2 is an island region, 3 and 5 are insulating films, 4 and 6 are conductive layers, and 8 is a P-type region, respectively. It shows. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, an island-like region formed by introducing an opposite-conductivity type impurity into the substrate, an insulating film deposited on the substrate surface including the island-like region, and a A first conductive layer provided to overlap at least a part of the island-like region and the first conductive layer are in an insulating state and are connected to the island-like region via a PN junction. a second conductive layer;
The thickness of the insulating film in at least a portion of the overlapping portion of the island-shaped region and the first conductive layer is set to be thinner than other portions, and the thickness of the insulating film is set to be thinner than other portions, and the thickness of the insulating film is set to be thinner at the overlapped portion of the island-like region and the first conductive layer. A programmable device characterized in that an electric field higher than the dielectric strength voltage of the thin insulating film is applied between the first conductive layer and the island-like region to cause dielectric breakdown of the thin insulating film and bring the first conductive layer and the island-like region into a conductive state. R.O.
M.