JPS6034273B2 - MIS type semiconductor memory device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an MIS type semiconductor memory device.

As an MIS type semiconductor memory device, there is one in which a memory cell is formed by a flip-flop formed by connecting two inverters each consisting of a load MISFET and a driving MISFET in a fixed manner. This is called a static type memory for comparison with a dynamic type memory which will be described later. Incidentally, it is necessary to reduce the power consumption of a semiconductor memory device as much as possible, and for this purpose, it is necessary to reduce the power consumption of the memory cells that constitute the memory device.

To achieve this, it is necessary to reduce the channel conductivity 3 (channel width W/channel length 1) in the load MISFET, and as a result, the channel length 1 has to be increased. Therefore, M for load
A problem arises in that the size of the ISFET increases and the integration density deteriorates. Of course, dynamic memory type semiconductor storage devices do not consume unnecessary power and the size of the memory cells can be small, but since the stored information is lost due to leakage current, refreshing is required.
Since a complicated peripheral circuit Z is required to perform complicated circuit operations, this does not essentially solve the above problem.

Therefore, it is an object of the present invention to reduce power consumption in a static memory without increasing the area occupied by the semiconductor memory device.

To achieve the above object, the present invention includes a pair of inverters in which one end of a pair of load elements is electrically connected to the drains of a pair of drive MISFETs, and the drive MISFET of one of the inverters is a flip-flop configured by electrically connecting a gate and a drain to the drain and gate of the driving MISFET of the other inverter, and between the driving MISFET drain of the pair of inverters and the pair of digit lines; A pair of transmission MISFETs whose respective sources and drain-isolation paths are electrically connected and whose gates are electrically commonly connected to a word line, and for supplying voltage to the other ends of the pair of load elements, A first wiring for electrically connecting the ends of the transistors in common; and a second wiring for electrically connecting the sources of the pair of driving MISFETs to a reference potential. In a MIS type semiconductor memory device comprising a memory cell on a semiconductor substrate, the first wiring, the pair of load elements, and the pair of driving MISFETs.
Each of the gates is constituted by a polycrystalline silicon layer formed on the semiconductor substrate via an insulating film, and
It is characterized in that they are electrically interconnected using a polycrystalline silicon layer.

The present invention will be explained below with reference to Examples.

All drawings relate to one embodiment of the invention.

FIG. 1 is a layout diagram of memory cells.

There is a passivation Si02 film shown at 8a in FIG. 3 on the outer periphery of the area surrounded by the dashed line. Portions 2a, 2b, and 2c indicated by broken lines are polycrystalline silicon layers, 2a is a power supply line (VoDLine), and the lower part is a transmission FETQ3.
, Q4, the drains of driving FETs Q, , Q2, the gates of driving FETs Q2, Q, and load resistances R,, R
2c is a word line (Wo
rdLine). 3a and 3b are load resistances R,,R
In the polycrystalline silicon layer constituting 2, 3a is R2, 3b is R
, respectively.

This is formed integrally with the polycrystalline silicon layers 2a and 2b, but has a lower impurity concentration and a higher specific resistance than the polycrystalline silicon layers 2a and 2b. In addition, parts 7b and 7a surrounded by two-dot chain lines
is a contact portion between a portion of the silicon gate 2b of the drive FETs Q, Q2 and a diffusion layer forming one end of the transmission FETs Q4, Q. Portion 4 indicated by a thin solid line is a CVDO-S that covers the load resistance R, R2 portions 3b and 3a.
It is an i02 film. Therefore, the above passivation Si0
28a and the semiconductor substrate region not covered by the polycrystalline silicon layers 2a and 2b and the semiconductor substrate region of the contact portion (region indicated by dots), and the resistor plate covered with the CVD-Si02 film of the polycrystalline silicon layer, ,R
The parts 2a, 2b, 2c other than the two parts 3a, 3b include:
Impurities of a conductivity type opposite to that of the semiconductor substrate are diffused. Portions 5a, 5b, and 5c indicated by thick solid lines are aluminum electrode wiring films, and 5a is a true digital line (dOLine).
), 5b is the ground line (GND Line), and 5c is the bird's-eye line (d Li fertilizer).

Reference numerals 6a and 6b are contact portions between the electrode wiring portion and the diffusion layer forming the end portions of the transmission FETs Q3 and Q4.

Figure 2 is a wiring diagram of this memory cell.

FIG. 3 is a cross-sectional view of the semiconductor memory device showing the MISFET and the load polycrystalline silicon layer section. 1 is a diffusion layer, 8a
8b is a gate insulating film, and 9 is a semiconductor substrate 0 board.

Diffusion layer 1 is formed in a portion not covered by passivation film 8a and polycrystalline silicon layers 2a, 2b, and 2c. Further, 2a, 2b, and 2c are low resistance polycrystalline silicon layers, and 3a is a high resistance polycrystalline silicon layer constituting a load resistance.

As described above, according to the present invention, firstly, the load means of the inverter constituting the flip-flop is constructed of a polycrystalline silicon layer with a low impurity concentration or high resistivity containing no impurities, so that the area occupied by the load means can be reduced. , the resistance value can be increased, and the area occupied by the memory cell can be reduced.

Second, since the polycrystalline silicon layer constituting the load means and the polycrystalline silicon layer for applying the power supply voltage (Voo) to the load means can be formed integrally, This eliminates the need for a special area, and the area occupied by the contact area can be reduced. Thirdly, since the interconnections between the gates of the pair of driving FETs and the pair of load resistors are also made of a polycrystalline silicon layer, when the gates of the driving FETs or the load resistors are formed of a polycrystalline silicon layer, At the same time, these interconnections can also be formed. Therefore, compared to the case where different metals such as aluminum wiring are used as interconnections, the number of contact portions for interconnections can be reduced, and the area occupied by the entire memory cell can be further reduced. In addition, in order to retain memory information,
How much current should be supplied through the load means is shown in Figure 4 (at room temperature 260°C) and Figure 5 (
70oo).

This shows a correlation diagram between the holding current and the applied voltage V skin in two cells for four samples a, b, c, and d. As is clear from this figure, when the room temperature is 260, even in sample a which requires the largest holding current, when the current voltage VDD is 12V, it is approximately 5x per memory cell.
10-8A, which makes it possible to retain information.

Therefore, the power consumption per memory cell is 0.6x
It only takes lo-6W (0.61W). Note that as the temperature of the device increases, the current required to retain information increases.

This is because the current leaking through the junction increases as the temperature rises. FIG. 5 shows the required holding currents for the same samples a, b, c, and d as in FIG. 4, and the above-mentioned fact becomes clear when these two figures are compared. By the way, leakage current increases with temperature rise, but according to the present invention, the specific resistance of the polycrystalline silicon layer used as the load means decreases with temperature rise, so the supply current increases with the increase in leakage current. There is no fear that information retention will become impossible due to temperature rise.

Note that the resistance of the portion of the polycrystalline silicon layer constituting the load means is controlled by adjusting the amount of impurity implanted, for example, by ion implantation.

FIG. 6 is a correlation diagram showing the correlation between the amount of ion implantation and the resistance value. 1 when the ion implantation amount is less than 1 and 3/clump.
Beauty. Q/port and the resistance value have a substantially constant value, and the resistance value can be easily controlled. However, it goes without saying that when the holding current is large, it is necessary to increase the amount of ion implantation in order to lower the resistance value. The present invention can be widely applied to static MIS type semiconductor annotation devices.

Note that the film for covering parts 3a and 3b is CVD-Si.
The insulating film is not limited to the 02 film, but may also be an insulating film such as a Si3N4 film.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of a memory cell according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the memory cell, and FIG. 3 is a MISF
A cross-sectional view showing the ET section and the load resistance section, Figures 4 and 5 are correlation diagrams between the current required to retain information and the voltage used in the memory cell, and Figure 6 shows the amount of impurity implanted into polycrystalline silicon. It is a correlation diagram with resistance. 1... Diffusion layer, 2a, b, c... Polycrystalline silicon layer, 3a, b... Polycrystalline silicon layer constituting load resistance, 4... CVD-Si02 film covering the portion of the polycrystalline silicon layer that constitutes the load resistor, 5
a, b, c... Aluminum electrode wiring film, 6a
．． b. ...Contact part between the diffusion layer and the electrode wiring,
7a, b...Contact portion between polycrystalline silicon layer and diffusion layer, 8a, b...Si02 film, 9...Semiconductor substrate, Q...MISFET, R... resistance,
d, d...7 data line, V. . ...Power supply voltage, Word...Word line. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 One end of a pair of load elements is connected to a pair of driving MISFETs.
a pair of inverters electrically connected to the drains of the driving MISFE of one of the inverters;
a flip-flop configured by electrically connecting the gate and drain of T to the drain and gate of the driving MISFET of the other inverter, and the drain of the driving MISFET of the pair of inverters and a pair of digit lines; a pair of transmission MISFETs whose sources and drains are electrically connected to each other, and whose sources are electrically commonly connected to the word line; a first wiring for electrically commonly connecting the other ends thereof, and a first wiring for electrically commonly connecting the sources of the pair of drive MISFETs to a reference potential in order to supply In the MIS type semiconductor memory device, the first wiring, the pair of load elements, and the gates of the pair of driving MISFETs are respectively provided on the semiconductor substrate. An MIS type semiconductor memory device comprising polycrystalline silicon layers formed through an insulating film, and electrically interconnected by polycrystalline silicon layers. . 2. Each of the load elements consists of a region in which impurities are introduced by ion implantation into a selected portion of the polycrystalline silicon layer, and the region has a higher ratio than the polycrystalline silicon layer used as the interconnection. The MIS type semiconductor memory device according to claim 1, characterized in that it has a resistor. 3. Each of the load elements is comprised of a substantially impurity-free region in the polycrystalline silicon layer, and the region has a higher specific resistance than the polycrystalline silicon layer used as the interconnection. An MIS type semiconductor memory device according to claim 1.