JPH0337869B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MIS type semiconductor memory device.

As a MIS type semiconductor memory device, for load use.
There is a memory cell constructed by a flip-flop, which is formed by connecting two inverters each consisting of a MISFET and a driving MISFET in a fixed manner. This is called a starter type memory for comparison with a dynamic type memory which will be described later.

Incidentally, it is necessary to reduce the power consumption of a semiconductor memory device as much as possible, and for this purpose, it is necessary to reduce the power consumption of the memory cells that constitute the memory device. To achieve this, it is necessary to reduce the channel conductivity β (channel width W/channel length l) in the load MISFET, and as a result, the channel length l has to be increased. Therefore, for load
The problem arises that the size of the MISFET increases and the integration density deteriorates.

Of course, dynamic memory type semiconductor storage devices do not consume unnecessary power and the size of the memory cells can be made small, but since the stored information is lost due to leakage current, refresh is required and complicated circuits are required. Since it requires a complicated peripheral circuit for operation, it does not essentially solve the above problem.

Therefore, it is an object of the present invention to reduce power consumption in a starter type memory without increasing the area occupied by the semiconductor memory device.

One of the inventors of the present invention previously proposed using a high-resistance polycrystalline silicon layer as a pair of load elements of a memory cell, and it is disclosed in Japanese Patent Application Laid-open No. 11644/1983. According to this proposal, the conventional 6
- Compared to a transistor-type memory cell, the pair of transistor loads are replaced by a resistor of a polycrystalline silicon layer, so it has the advantage that the area occupied by the load element can be reduced;
Compared to the conventional 4-transistor dynamic memory cell, this memory cell has the advantage of not requiring a refresh circuit for reproducing information. However, although this proposal was aimed at improving the load element itself inside the memory cell, the connection layout between the power supply line and the memory cell for supplying voltage to a large number of memory cells arranged in rows and columns was Not directed. The present invention particularly relates to a layout from a power supply line extending between memory cells to a driving transistor via a load element inside the memory cell, in a semiconductor memory device using the high-resistance polycrystalline silicon load type memory cell. , which aims to reduce the occupied area.

To achieve the above object, the present invention includes a pair of digit lines extending in a semiconductor substrate, a word line extending in the semiconductor substrate in a direction orthogonal to the digit lines, and a pair of digit lines extending in the semiconductor substrate, and a word line extending in the direction orthogonal to the digit lines. a memory cell formed on the semiconductor substrate in association with a word line; a pair of driving power lines cross-coupled to each other;
A pair of MISFETs, each having a source and a drain path electrically connected between the drains of the pair of drive MISFETs and the pair of digit lines, and whose gates are electrically connected to the word line. In the MIS type semiconductor memory device, the power supply line is made of a polycrystalline silicon layer, and the electrical connection between the power supply line and the drain region of the drive MISFET of each memory cell is made of polycrystalline silicon. The polycrystalline silicon layer branches from the power supply line and extends to the drain region of the driving MISFET, and is electrically connected to the drain of the driving MISFET through the polycrystalline silicon layer, A polycrystalline silicon layer branched from the power supply line is provided with a region having a lower impurity concentration than the power supply line.

Such features of the present invention will become clear from the description of embodiments with reference to the following drawings.

All drawings relate to one embodiment of the invention.

FIG. 1 is a layout diagram of a memory cell.

A passivation SiO ₂ film shown as 8a in FIG. 3 is present on the outer periphery of the area surrounded by the dashed line.
Portions 2a, 2b, and 2c indicated by broken lines are polycrystalline silicon layers, 2a is a power supply line (V _DD Line), and 2b is a
One end of transmission FETQ ₃ , Q ₄ and drive FET Q ₁ , Q ₂
and the gates of driving FETQ ₂ and Q ₁ ,
Line interconnecting load resistors R ₁ and R ₂ , 2c
is a word line. 3a,
3b is a polycrystalline silicon layer forming load resistors R ₁ and R ₂ , and 3 a and 3 b act as R ₂ and R ₁ , respectively. This is because the polycrystalline silicon layers 2a, 2
Although it is formed integrally with b, it has a lower impurity concentration and higher resistivity than that. In addition, portions 7b and 7a surrounded by two-dot chain lines are drive FETQ ₁ ,
Part of silicon gate 2b of Q ₂ and for transmission
This is a contact portion with the diffusion layer forming one end of FETQ ₄ and Q ₃ (this diffusion layer is also the drain diffusion layer of driving MISFETQ ₂ and Q ₁ ). Further, as is clear from the figure, these portions 7b and 7a are also portions where the drain diffusion layers of the driving MISFETs _{Q 2} and Q ₁ are in contact with one end of the resistance regions 3a and 3b of the polycrystalline silicon layer. A portion 4 indicated by a thin solid line is a CVD-SiO ₂ film covering the load resistors R ₁ and R ₂ portions 3b and 3a. Therefore, the passivation SiO ₂ 8a and the polycrystalline silicon layer 2a,
2b and the semiconductor substrate region of the contact portion (area indicated by dots) and the polycrystalline silicon layer, CVD-
Resistor R ₁ and R ₂ portions 3a and 3b covered with SiO ₂ film
Impurities having a conductivity type opposite to that of the semiconductor substrate are diffused into the other portions 2a, 2b, and 2c. Portions 5a, 5b, and 5c indicated by thick solid lines are aluminum electrode wiring films, and 5a is the true digital line (d
Line), 5b is the ground line (GND Line), 5c
is the bardate line.
Reference numerals 6a and 6b are contact portions between the diffusion layers forming the other end portions of the transmission FETs Q ₃ and Q ₄ and the electrode wiring portions.

FIG. 2 is a wiring diagram of this memory cell.

FIG. 3 is a cross-sectional view of the semiconductor device showing the MISFET and the load polycrystalline silicon layer.

1 is a diffusion layer, 8a is a SiO ₂ film for semiconductor surface passivation, 8b is a gate insulating film, and 9 is a semiconductor substrate. The diffusion layer 1 is the passivation film 8
a and the portions not covered by polycrystalline silicon layers 2a, 2b, and 2c.

Further, 2a, 2b, and 2c are low resistance polycrystalline silicon layers, and 3a is a high resistance polycrystalline silicon layer constituting a load resistance.

As _is clear from the layout diagram _{of FIG} . , polycrystalline silicon which branches off from the power supply line polycrystalline silicon layer 2a extending to the substrate and is in direct contact with the drain semiconductor region of the driving MISFET (Q ₁ or Q ₂ ) in the region 7a or 7b. Layer branch (3b
or 3a). A feature is that the power supply line 2a and the polycrystalline silicon layers of the branch portions 3b and 3a are integrally formed. That is, the present invention integrates the power supply line (V _DD ) and the circuit that branches from the power supply line and extends through the load element of each memory cell to the drain semiconductor region of the driving MISFET using a single polycrystalline silicon layer. It is characterized by the formation of

According to the present invention, the area occupied by the entire semiconductor memory device can be significantly reduced for the following first to third reasons.

That is, according to the present invention, firstly, the load means of the inverter constituting the flip-flop is constructed of a polycrystalline silicon layer with low impurity concentration or high resistivity containing no impurities, so that the area occupied by the load means is small and the resistance The value can be increased, and the area occupied by the load element body of the memory cell can be reduced.

Second, since the polycrystalline silicon layer constituting the load means and the polycrystalline silicon layer for applying the power supply voltage (V _DD ) to the load means can be formed integrally, it is possible to make contact between the two. This eliminates the need for a special area, and the area occupied by the contact area can be reduced.

Thirdly, the connection between the drains of a pair of drive FETs or the drains of a pair of transmission MISFETs and a memory cell load element is made directly through the polycrystalline silicon layer where the resistance region of the load element is formed. Mutual wiring between these circuit elements can be omitted. Therefore, compared to the case where dissimilar metals such as aluminum wiring are used as interconnections, it is possible to reduce the formation of contact portions for interconnections, and to connect memory cell load elements and drive
The area required for electrical connection with the MISFET can be further reduced.

According to the present invention, the power supply line that supplies voltage to a large number of memory cells is formed integrally with the polycrystalline silicon layer for loading the memory cells, and the polycrystalline silicon layer branched from the power supply line also serves as a load for the memory cells. Since it is in direct contact with the drain semiconductor region of the driving transistor or the semiconductor region of the transmission transistor, the power supply line extending in connection with the memory cell can be formed in the same process as the formation of the load element of the memory cell. This not only makes it possible to reduce the area occupied by semiconductor memory device manufacturing technology, but also significantly reduces the defect rate during manufacturing, which is particularly advantageous for manufacturing semiconductor memory devices with large storage capacities. becomes.

Furthermore, Figure 4 (when the room temperature is 25°C) and Figure 5 (when the room temperature is 70°C) shows how much current should be supplied through the load means in order to retain the stored information. . This shows a correlation diagram between holding current and applied voltage V _DM in two cells for four samples a, b, c, and d.

As is clear from this figure, when the room temperature is 25°C, even in sample a, which requires a large holding current, when the power supply voltage _VDD is 12V, it is about 5 × 10 ^-8 A per memory cell, This allows information to be retained. Therefore, the power consumption per memory cell is only 0.6×10 ⁻⁶ W (0.6 μW).

Note that as the temperature of the device increases, the current required to retain information increases. This is because the current leaking through the junction increases as the temperature rises. FIG. 5 shows the required holding currents for the same samples a, b, c, and d as in FIG. 4, and the above-mentioned fact becomes clear when these two figures are compared.

Incidentally, leakage current increases as temperature rises, but according to the present invention, the specific resistance of the polycrystalline silicon layer used as the load means decreases as temperature rises, so the supply current decreases as the leakage current increases. There is no fear that information retention will become impossible due to an increase in temperature.

Note that the resistance of the portion of the polycrystalline silicon layer constituting the load means is determined by adjusting the amount of impurity implanted by, for example, ion implantation. FIG. 6 is a correlation diagram showing the correlation between the amount of ion implantation and the resistance value R ₀ .
When the ion implantation amount is 10 ¹³ /cm ³ or less, 10 ¹⁰ Ω/
The resistance value is approximately constant, and the resistance value can be easily controlled. However, it goes without saying that when the holding current is large, it is necessary to increase the amount of ion implantation in order to lower the resistance value.

The present invention can be widely applied to starter MIS type semiconductor memory devices.

In addition, the membrane for covering parts 3a and 3b is
It is not limited to the CVD-SiO ₂ film, but may also be an insulating film such as a Si ₃ N ₄ film.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a memory cell of a MIS type semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the memory cell section shown in FIG. 1, and FIG. 3 is a MISFET section and a load. Cross-sectional view showing the resistance part, No. 4
5 is a correlation diagram between the current required to retain information and the voltage used in a memory cell, and FIG. 6 is a correlation diagram between the amount of impurity implanted into polycrystalline silicon and the resistance. 1...diffusion layer, 2a, b, c...polycrystalline silicon layer, 3a, b...polycrystalline silicon layer constituting the load resistor, 4...portion of the polycrystalline silicon layer constituting the load resistor Covering CVD-SiO ₂ film, 5a,
b, c... Aluminum electrode wiring film, 6a, b...
...Contact portion between the diffusion layer and the electrode wiring, 7a, b
...Contact portion between polycrystalline silicon layer and diffusion layer, 8a, b...SiO ₂ film, 9...Semiconductor substrate,
Q...MISFET, R...resistance, d,...data line, V _DD ...power supply voltage, Word...word line.

Claims (1)

[Scope of Claims] 1. A pair of digit lines extending on a semiconductor substrate, a word line extending on the semiconductor substrate in a direction orthogonal to the digit lines, and a pair of digit lines extending on the semiconductor substrate, and a pair of digit lines extending on the semiconductor substrate in a direction perpendicular to the digit lines, and a pair of digit lines extending on the semiconductor substrate; Relatedly, a memory cell formed on the semiconductor substrate, and a power supply line extending over the semiconductor substrate from the memory cell formation region of the semiconductor substrate to another region for applying a voltage to the memory cell. The memory cell includes a pair of driving MISFETs cross-coupled to each other, and a pair of driving MISFETs cross-coupled to each other.
A pair of transmission devices, each of which has its source and drain path electrically connected between the drain of the MISFET and the pair of digit lines, and whose gate is electrically connected to the word line.
In an MIS type semiconductor memory device having an MISFET, the power supply line is made of a polycrystalline silicon layer, and is used for driving the power supply line and each memory cell.
Electrical connection with the drain region of the MISFET is made through a polycrystalline silicon layer, and the polycrystalline silicon layer is branched from the power supply line and used for the drive.
Extends to the drain region of the MISFET and for driving the
The drain of the MISFET is electrically connected to the polycrystalline silicon layer, and the polycrystalline silicon layer branched from the power supply line is provided with a region having a lower impurity concentration than the power supply line.
MIS type semiconductor memory device. 2. The polycrystalline silicon layer portion of the power supply line extends in the same direction as the word line, and the branched portion of the polycrystalline silicon layer branches in the same direction as the digit line. An MIS type semiconductor memory device according to claim 1, characterized in that: