JPS6041884B2 - differential amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a differential amplifier circuit configured with transistor circuits, and more particularly to a differential amplifier circuit configured with a monolithic integrated circuit having small offset current and offset voltage.

For example, when a differential amplifier circuit is configured with a monolithic integrated circuit, the differential amplifier included in the differential amplifier circuit maintains its balance by the current flowing from the circuit continuously connected to the differential amplifier circuit and the current mirror circuit that serves as the collector load. is greatly affected, and the resulting unbalance appears as an input offset current and an input offset voltage.

A conventional differential amplifier circuit constructed from a monolithic integrated circuit is constructed as shown in FIG.

The prior art will be explained below with reference to FIG. The illustrated differential amplifier circuit includes a current mirror circuit made up of transistors 1 and 2 and a differential amplifier made up of transistors 3 and 4. In this case, in transistor 3, the base is connected to input terminal 6 to give an input of 1, the collector is connected to the collector and base of transistor 1, and the emitter is connected to the collector of transistor 5 together with the emitter of transistor 4. ing. The base of transistor 1 is further connected to the base of transistor 2, and the emitter is connected to power supply terminal 7. On the other hand, in the transistor 4, the base is connected to the input terminal 8 to receive other inputs, and the collector is connected to the collector of the transistor 2 and the transistor 9 which provides the output of the differential amplifier, which constitutes the next stage amplifier circuit. The emitter of the transistor 2 is connected to the power supply terminal 7 while the emitter of the transistor 2 is connected to the base. The base of transistor 5 is transistor 10
and 11 are connected to the collector of the transistor 11, and the emitter is connected to the ground terminal 12. In the transistor 9, the emitter is connected to the power supply terminal 7, the collector is connected to the output terminal 13 together with the collector of the transistor 10, and provides the output of the differential amplifier circuit.

The emitters of transistors 10 and 11 are each connected to ground terminal 12.

The collector and base of the transistor 11 are both connected to one of the constant current sources 14, and the other of the constant current sources 14 is connected to the power supply terminal 7. In this case, the constant current source 14 generates a current from the power supply terminal 7 to the transistor 11 as indicated by the arrow in the figure. A differential amplifier circuit with such a connection configuration is usually manufactured so that the transistors 3 and 4 have the same element configuration, that is, the same shape, and their collector bias currents are approximately equal.

That is, the shapes of the elements are made the same, and the input offset voltage and input offset current are made as small as possible. However, in the differential amplifier transistors 3 and 4
The base currents of transistors 1 and 2, which correspond to the collector resistance of Flows into collector 4. Therefore, if the characteristics of transistors 1, 2, and 9 are all the same, the collector current of transistor 3 will be the base current equivalent to one transistor such as transistor 1, which will be greater than the collector current of transistor 4, and the difference due to this current will be This causes input offset voltage and input offset current of the differential amplifier. That is, in a differential amplifier circuit having such a configuration, it is essentially difficult to balance the current, and the input offset voltage and input offset current cannot be reduced. In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.
The purpose of this is to make the collector potentials of the two transistors constituting the differential amplifier circuit the same and at the same time make the collector currents the same, and also to easily reduce the input offset voltage and input offset current. It is an object of the present invention to provide a differential amplifier circuit that can easily maintain balance even when there are temperature fluctuations and can easily balance the currents flowing into the collectors of each transistor.

To achieve such an objective, the present invention provides a base-emitter junction structure identical to a current mirror circuit consisting of transistors that supply substantially equal collector bias currents to the respective collectors of a set of differential pair transistors. It has the same conductivity type as the transistor of the current mirror circuit, and is of the opposite conductivity type to the differential pair transistor, and its base, emitter, and collector electrodes are connected in parallel to each other, and the base is connected to the current mirror circuit. The first and second transistors of the next stage amplifier circuit are connected to the collector of the transistor on the side other than the transistor that has the diode function in the circuit, and the collectors of the first and second transistors are connected to determine the collector bias current. A third transistor for a constant current source, and a fourth transistor that is a current mirror circuit that operates as a constant current source that determines the bias current of the differential amplifier and is applied with the same base bias as the third transistor. bases of the third and fourth transistors;
The emitter-to-emitter junction area ratio is selected so that the collector potentials of the pair of differential pair transistors are the same and the collector currents are the same, and each of the pair of differential pair transistors is has the same base-emitter junction structure as a current mirror circuit configured with a first multi-collector transistor that supplies substantially equal collector bias current to the collector of the current mirror circuit, and has the same base-emitter junction structure as the first multi-collector transistor of the current mirror circuit. a next-stage amplifier circuit having the same conductivity type and opposite conductivity type to the differential pair transistors, and having its base connected to the collector on the side other than the collector having a diode function of the first multi-collector transistor in the current mirror circuit; a second multi-collector transistor, and a collector of the second multi-collector transistor. The first constant current source is connected at the same time and determines the collector bias current.
and a second transistor which is a current mirror circuit that operates as a constant current source that determines the bias current of the differential amplifier and to which the same base bias as the first transistor is applied, The base-emitter junction area ratio of the two transistors is selected so that the collector potentials and collector currents of the pair of differential pair transistors can be made the same. Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a connection diagram showing an embodiment of the differential amplifier circuit according to the present invention. Note that in FIG. 2, the same reference numerals as in FIG. 1 indicate corresponding parts. First, in Figure 2, the first
The main differences between the diagram and the circuit are transistors 9a and 9b.
This is because it was established. That is, transistors 9a and 9
In b, the collector, base and emitter of one are connected in parallel to the collector, base and emitter of the other, respectively. Therefore, the emitters of transistors 9a and 9b are the power supply terminal 7, the bases are the collector of transistor 4,
The collector is connected to the collector of the transistor 10 and to the output terminal 13, respectively. Here, transistors 1, 2, 9a, and 9b have the same structure, that is, the same shape, and have the same characteristics, such as collector current.

Therefore, in transistors 1, 2, 9a and 9b,
The DC amplification factor is HFE (PNP), and the base current is IB (P
NP), and the collector currents are expressed as IO and PNp), respectively. First, the collector current 1CQ3 of the transistor 3 is expressed by the following equation.

Also, the collector current of transistor 4.

4 is expressed by the following formula.

As is clear from equations 1 and 2, and from equation 3, the collector currents of transistors 3 and 4 are equal to each other.

That is, the differential amplifier composed of transistors 3 and 4 can balance the currents, thereby making it possible to reduce the input offset voltage and input offset current to approximately zero. Next, the collector current 10 of the transistor 5 in this case.

5 is expressed by the following formula.

From the relationship with the first to third equations, the fourth equation is as follows.

Furthermore, the collector current of the transistor 10 is as follows. As mentioned above, a necessary condition for minimizing the input offset voltage and input offset current is to make at least the collector currents of transistors 1, 2, 9a and 9b equal to each other.

From this, in the configuration of transistors 5 and 10,
The junction area ratio between the base and the emitter must satisfy at least the relationships shown in the fifth and sixth equations. Here, if the junction area ratio between the base and the emitter is represented by S, the following relationship holds true for the transistors 5 and 10.

Equations 5, 6, and 7 are as follows.

The 8th formula is DC amplification factor HFE3PNP)=L? UO related
From IB(PNP), it becomes as follows.

The junction area ratio S is determined from the ninth equation as follows.

Therefore, in order to minimize the input offset voltage and input offset current, transistors 1, 2, 9a and 9
It is sufficient that the shapes of b are the same, and further, the configuration of transistors 5 and 6, that is, the junction area ratio S, satisfies the condition shown in equation (10). FIG. 3 shows another embodiment of the differential amplifier circuit according to the present invention.

Transistor 1a in FIG. 3 corresponds to transistors 1 and 2 shown in FIG. 2, and is constituted by a multi-collector transistor in which the base and emitter are common and only the collector is provided separately. Similarly,
Transistor 9b is a multi-collector transistor corresponding to transistors 9a and 9b shown in FIG. In this case as well, the relationship from the first equation to the first test must be satisfied. FIG. 4 is a schematic pattern diagram for explaining the structure of a transistor used in the present invention.

FIG. 4a shows transistors 1a and 9a, and shows the patterns of collector 1b, 1d1, emitter 1C1 and base 1e. FIG. 4b shows the transistor 5 and shows the patterns of the collector 5a, base 5b1 and emitter 5c. Figure 4C is transistor 1
This shows a pattern of a collector 10a, a base 10b1, and an emitter 10c. In this case, by keeping the lateral lengths of the emitters 5c and 10c constant and changing the vertical length h, the junction area between the base and the emitter can be easily set as desired.
As is clear from the above, according to the differential amplifier circuit of the present invention, the transistors of the current mirror circuit and the differential amplifier circuit are balanced so that the collector bias current flowing into the transistors constituting the differential amplifier is balanced. By making the transistors of the next-stage amplifier circuit connected to the same shape, the input offset voltage and input offset current can be easily reduced, and balance can be maintained even when there are temperature fluctuations. It has the effect of making it easy to use.

[Brief Description of the Drawings] Fig. 1 is a connection diagram showing a conventional differential amplifier circuit, and Fig. 2 is a connection diagram showing an embodiment of the differential amplifier circuit according to the present invention.
FIG. 3 is a connection diagram showing another embodiment of the differential amplifier according to the invention, and FIG. 4 is a pattern diagram showing the shapes of transistors used in the differential amplifier circuit of the invention. 1, 2, 3, 4, 5, 9, 10, 11... Transistor, 6, 8... Input terminal, 13...
...Output terminal, 14... Constant current source.

Claims (1)

[Claims] 1. A current mirror including a differential amplifier including at least one set of differential pair transistors, and configured with transistors that supply substantially equal collector bias currents to the respective collectors of the set of differential pair transistors. A differential amplifier circuit in which the circuits are connected has the same base-emitter junction structure as the current mirror circuit, has the same conductivity type as the transistor of the current mirror circuit, and is opposite to the differential pair transistor. Each base with conductive type,
The first and second transistors of the next stage amplifier circuit have their emitter and collector electrodes connected in parallel and their bases are connected to the collector of the transistor on the side of the current mirror circuit that is not the transistor that has the diode function; a third transistor for a constant current source that is connected to the collectors of the first and second transistors and determines a collector bias current; and a third transistor that operates as a constant current source that determines a bias current of the differential amplifier; and a fourth transistor which is a current mirror circuit to which the same base bias is applied, and the collector of the pair of differential pair transistors is selected by selecting the base-emitter junction area ratio of the third and fourth transistors. A differential amplifier circuit characterized by having the same potential. 2. A current mirror circuit comprising a first multi-collector transistor that includes a differential amplifier including at least one set of differential transistors and supplies substantially equal collector bias currents to the respective collectors of the set of differential pair transistors. The connected differential amplifier circuit has the same base-emitter junction structure as the current mirror circuit, has the same conductivity type as the first multi-collector transistor of the current mirror circuit, and has the same conductivity type as the first multi-collector transistor of the current mirror circuit. a second multi-collector transistor of the next stage amplifier circuit, which is of a conductivity type opposite to that of the current mirror circuit and whose base is connected to the collector of the side other than the collector having a diode function of the first multi-collector transistor in the current mirror circuit; a first transistor for a constant current source that is connected to the collector of the multi-collector transistor and determines the collector bias current; and a first transistor that operates as a constant current source that determines the bias current of the differential amplifier and that has the same base as the first transistor. a second transistor which is a current mirror circuit to which a bias is applied, and selects a base-emitter junction area ratio of the first and second transistors to determine the collector potential of the pair of differential pair transistors. What is claimed is: 1. A differential amplifier circuit characterized in that the circuits are the same and the collector currents can be the same.