JPS6041893B2 - Synthesizer receiver program reservation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program reservation device for a synthesizer receiver, which is suitable for use in a synthesizer receiver, for example, and is capable of reserving a plurality of programs without using a special timer. be.

2. Description of the Related Art Conventionally, a program reservation device as shown in FIG. 1 has been proposed as a program reservation device capable of reserving a plurality of programs for an FM synthesizer receiver using a PLL circuit. That is, in FIG. 1, 1 indicates an antenna capable of receiving FM broadcasting, and 3 indicates a local oscillator that supplies a signal obtained from this antenna 1 to a front-end circuit 2, or a local oscillator that determines the reception frequency. This PLL circuit constitutes
By determining the division ratio N of the N frequency divider 3a provided in the circuit 3, the local oscillation frequency is determined and the receiving frequency is determined. In this synthesizer receiver, normally, the channel selection signal selected by the channel selection device 4 is supplied to the PLL circuit 3 via one fixed contact 55 and the movable contact 5a of the switching device 5, The frequency division ratio N of this N divider/frequency unit 3a is determined by the signal. In this Figure 1, 6 is an intermediate frequency amplification circuit, 7
1 is an FM multiflex demodulation circuit, 8 is an audio signal amplification circuit, 9 is an audio signal output terminal connected to a speaker, etc.
0 is the power supply circuit of this synthesizer receiver. From this power supply circuit 10, a front end circuit 2, a PLL circuit 3
, the channel selection device 4, the intermediate frequency amplification circuit 6, the FM multiflex demodulation circuit 7, and the audio amplification circuit 8 are each supplied with DC power. Conventionally, as a program reservation device capable of reserving a plurality of programs for such a synthesizer receiver, a dedicated special timer having a programmer as shown in FIG. 1 has been used. That is, 11 is a timer, an input terminal 11a of this timer 11 is connected to, for example, a commercial power source, this input terminal 11a is connected to an output terminal 11b via a connection switch 12, and this output terminal 11b is connected to a synthesizer. It is designed to be connected to a commercial power input terminal of a power supply circuit 10 of the receiver. Further, 13 is a control device configured to control the on/off state of the connection switch 12 at a predetermined time, and 14 is a programmer configured in substantially the same manner as the channel selection device 4 of the synthesizer receiver. Accordingly, the frequency division ratio of the blue frequency divider 3a of the PLL circuit 3 can be determined statically, and the content of the output signal, that is, the channel selection signal, can be selected as desired. The programmer 14 is also controlled to operate or not to operate by the control device 13. When attempting to reserve a program using such a timer 11, a desired broadcasting station is selected in advance by the programmer 14, and the control device 1
In step 3, the scheduled time is set, the input terminal 11a is connected to a commercial power supply, the output terminal 11b is connected to the commercial power input terminal of the power supply circuit 10 of the synthesizer receiver, and the output side of the programmer 14 is connected to a switch. 5, and the movable contact 5a of this switching device 5 is connected to the other fixed contact 5T. In this state, when the scheduled time comes, the control device 13 operates to turn on the connection switch 12, and commercial power is supplied to the power circuit 10 of the Synsensor receiver.
A power supply voltage +B is obtained on the output side of the circuit, and this is supplied to the front end circuit 2, PLL circuit 3, intermediate frequency amplification circuit 6, multiplex demodulation circuit 7, audio amplification circuit 8, etc. to operate this synthesizer receiver. state. At this time, the programmer 14 is also brought into operation by the control device 13, and the channel selection signal selected by the programmer 14 is supplied to the PLL circuit 3 via the switch 5.
A desired broadcast can be received by this synthesizer receiver during a predetermined four-hour period. However, such a program reservation device requires a special programmer 14 that can be programmed as a timer 11, and the receiver side also requires a device that can handle this. There were also various inconveniences such as receiver compatibility. In view of this, the present invention is designed so that a normal timer that turns on and off the power supply line at a set time can be used for program reservations for the above-mentioned synthesizer receiver. An embodiment of the program reservation device for a synthesizer receiver according to the present invention will be described below with reference to FIG.

In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In FIG. 2, 15a, 15b, 15c and 15d are similarly constructed channel selection memories, respectively.
c and 15d can each be set as desired (for example, by turning on/off a connection switch) to generate a desired tuning signal, and this tuning signal changes the frequency division ratio blue of the blue frequency divider 3a of the PLL circuit 3. It is designed to determine the
FIG. 2 shows an example in which reservations for up to four programs can be received. Further, in FIG. 2, +B indicates the power supply terminal to which the positive DC voltage obtained on the output side of the power supply circuit 10 is supplied, and this power supply terminal +B is connected to the resistor 16 and capacitor 17 that constitute the time constant circuit. The connection point of this resistor 16 and capacitor 17 is connected to the input side of the one-shot multivibrator circuit 19 via the Schmitt circuit 18, and the connection point of this resistor 16 and capacitor 17 is connected to the input side of the one-shot multivibrator circuit 19. The resulting trigger pulse is supplied to the trigger terminal CP of one of the flip-flop circuits 20 constituting the quaternary counter, and when this flip-flop circuit 20 is set, a high level signal "F'" is generated.
The Q terminal from which is obtained is connected to the trigger terminal CP of the other flip-flop circuit 21 constituting the quaternary counter. Further, 22a, 22b, 22c, and 22d each indicate an AND circuit constituting a decoder circuit, and the Q terminal of one flip-flop circuit 20 is connected to one input terminal of each of the AND circuits 22b and 22d. When the flip-flop circuit 20 is reset, the O terminal from which a high-level signal "゜1" is obtained is connected to one input terminal of each of the AND circuits 22a and 22c, and when the other flip-flop circuit 21 is set. The Q terminal from which a high-level signal "F' is obtained is connected to the other input terminal of each of the AND circuits 22c and 22d, and when the other flip-flop circuit 21 is reset, a high-level signal "゜1'' is obtained. The O terminals of the AND circuits 22a and 22b are respectively connected to the other input terminals of the AND circuits 22a and 22b.
The output sides of the channels a, 22b, 22c and 22d are connected to the gate signal input terminals of the channel selection memories 15a, 15b, 15c and 15d, respectively. In this case, the channel selection memory 1 is supplied with the high level signal "゜1゛" from the output side of each of the AND circuits 22a, 22b, 22c and 22d.
The output signals of 5a, 15b, 15c and 15d are supplied to the PLL circuit 3. That is, the reception frequency is determined by the contents of the selected channel selection memory 15a, 15b, 15c115d. Also, flip-flop circuit 20
and 21 are grounded via a reset connection switch 23. In this case, the connection switch 23 is configured as an automatic recovery type switch, and each time the connection switch 23 is turned on, the flip-flop circuit 2
0 and 21 are each reset. Reference numeral 24 denotes a backup battery, which prevents the memory states of the flip-flop circuits 20 and 21 from changing even if the power from the power supply circuit 10 is turned off. In the example shown in FIG. 2, a conventional control device 13 is used as the timer 11.
A connection switch 12 that can be turned on and off is used. The rest of the structure is the same as in FIG. In the configuration shown in FIG. 2, when the timer 11 is not used, the power supply circuit 1
Connecting switch 23 for supplying commercial power to 0 and for resetting
Once turned on.

At this time, the flip-flop circuits 20 and 21 are each reset, so the output side of the AND circuit 22a becomes a high level signal "゜1", and the output signal of the channel selection memory 15a is supplied to the PLL circuit 3. In this case, only the channel selection memory 15a is used, and this channel selection memory 1
5a, the desired broadcasting station can be received. Next, the case where a plurality of programs are reserved using the timer 11 will be explained.

It is assumed that a program reservation is made when the flip-flop circuits 20 and 21 are each in a reset state. In this case, as time passes, the reservation for the first program is set in the channel selection memo 1 river 5b, the reservation for the second program is set in the channel selection memo 1 river 5c, and the reservation for the second program is set in the channel selection memo 1 river 5c. The reservation for the fourth program is set in the channel selection memory 15d, and the reservation for the fourth program is set in the channel selection memory 15a. In addition, the input terminal 11a of the timer 11 is connected to a commercial power supply, and the output terminal 11b is connected to a commercial power input terminal of the power supply circuit 10.
The control device 13 of this timer 11 sets, for example, the times at which to turn on and off the first, second, third, and fourth subprograms. In this state, when the first set time t1 comes, the connection switch 12 is turned on by the operation of the control device 13 of the timer 11, and the commercial power is supplied to the power supply circuit 10. The output side changes from zero voltage to power supply voltage ■Cc as shown in Figure 3A.
Then, the Synsensor receiver is put into operation, and at this time, the voltage at the midpoint of the connection between the resistor 16 and the capacitor 17 is as shown in FIG. 3B.
gradually increases with a time constant determined by .

When this voltage exceeds the threshold level of the Schmitt circuit 18, the output side of the Schmitt circuit 18 becomes
As shown in FIG. 3, the low level signal ゜"0" becomes a high level signal ゜゜1゛, and one trigger pulse as shown in FIG. 3D is obtained on the output side of the one-shot multivibrator circuit 19, and this trigger pulse circuit 2
0 to the trigger terminal CP, and as a result, the Q terminal of the flip-flop circuit 20 becomes a high level signal "゜1" as shown in FIG. As shown in FIG.
The output sides of each of a, 22c and 22d are shown in FIG. As shown in I and J, the low level signal becomes "0", and as a result, the output signal of the channel selection memory 15b is supplied to the PLL circuit 3, and the broadcasting station previously selected by the channel selection memory 15b is received at this time. Next, when the connection switch 12 of the timer 11 is turned off at a certain time, the voltage on the output side of the power supply circuit 10 becomes zero and the sensor receiver becomes inoperable. timer 11
When the connection switch 12 is turned on and the output side of the power supply circuit 10 rises from zero to the power supply voltage Vcc, the same operation as described above occurs, and at this time, a trigger pulse is supplied to the trigger terminal CP of the flip-flop circuit 20, and the flip-flop The Q terminals of the pull-up circuits 20 and 21 receive a low level signal ``0'' and a high level signal ``1'', respectively, as shown in FIG. 3E and F, respectively, and only the output side of the AND circuit 22c receives a high level signal ``1''. ) At this time, the output signal from the channel selection memory 15c is supplied to the PLL circuit 3, and the desired broadcasting station reserved by the channel selection memory 15c can be received. The same operation is performed when the program comes, and the desired program reserved in the channel selection memories 15d and 15a can be received.As described above, according to the present invention, it is possible to reserve a plurality of programs. It is advantageous to be able to simply use a regular timer that turns on and off at predetermined times without using a special dedicated timer.

FIG. 4 also shows another embodiment of the invention.

In FIG. 4, a microcomputer is used as the channel selection device. In FIG. 4, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In FIG. 4, 25 indicates a microcomputer, and 27 is assigned an address for storage and reading, and at least the frequency division ratio of the frequency divider 3a of the PLL circuit 3 is stored as a channel selection signal. Tuning memory 2
7a, 27b, 27c, and 27d, 30 indicates a signal instructing the tuning memory at a predetermined location in the tuning memory device 27, a tuning signal stored in the tuning memory, and the operation of the microcomputer 25. An input device consisting of a connection switch is shown for inputting a signal instructing the microcomputer 25 to the microcomputer 25. Normally, the input device 30 is used to supply the channel selection signal selected by the microcomputer 25 to the latch circuit 26. The signal stored in the latch circuit 26 is supplied to the PLL circuit 3, and the PLL circuit
The frequency division ratio of the frequency divider 3a of the circuit 3 is determined, and the reception frequency of the synthesizer receiver is determined. Do as you decide.

When reserving a plurality of programs using a timer, the memory device 27 has a plurality of channel selection memories 27a, 27b, 27c, and 27d, and the channel selection memory 27a,
27b, 27c and 27d. The input device 30 is used to store a desired channel selection signal, respectively, and when the output signal of each AND circuit 22a, 22b, 22c, and 22d becomes a high level signal '4r', this signal is stored. The tuning signal stored in the tuning memory at the address corresponding to this in the memory device 27 is read out, and the signal is sent to the latch circuit 26.
This channel selection signal is supplied to the PLL circuit 3 to receive the reserved program.

The rest of the structure is the same as in FIG. Therefore, in FIG. 4 as well, each time the connection switch 12 of the timer 11 is turned on, the AND circuit whose output side becomes a high level signal ゛"1" changes in sequence, and the reserved programs can be sequentially received. .

Therefore, it is easy to understand that the example shown in FIG. 4 has the same effect as that shown in FIG. 2. In the above-described embodiment, the case where four programs can be reserved has been described, but it is easily understood that a plurality of other programs can be reserved in a similar configuration.

Furthermore, it will be easily understood that the present invention is not limited to the above-described embodiments, and that various other configurations can be taken without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional program reservation device for a synthesizer receiver, FIG. 2 is a block diagram showing an example of a program reservation device for a synthesizer receiver according to the present invention, and FIG. 3 is an explanation of the present invention. FIG. 4 is a diagram showing another embodiment of the present invention. 2 is a front end circuit, 3 is a PLL circuit, 3a is a frequency divider, 10 is a power supply circuit, 11 is a timer, 15a, 15
b, 15c and 15d are channel selection memories 20 and 21, respectively.
Each of the flip-flop circuits 22a, 22b, 22c and 22d is an AND circuit.

Claims (1)

[Claims] 1 A PLL circuit, a tuning memory that stores a plurality of tuning signals that control the frequency division ratio of the PLL circuit, a detection circuit that detects the rise of a power supply voltage that is controlled on and off by a timer, and an output of the detection circuit. and a memory control circuit that sequentially selects the tuning signal stored in the tuning memory each time the tuning signal is supplied, and the tuning signal stored in the tuning memory is sequentially supplied to the PLL circuit to receive the tuning signal. A program reservation device for a synthesizer receiver, characterized in that the program reservation device performs the following steps.