JPH023566B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a controller that constitutes a digital tuning system such as a radio receiver or a television receiver.

Figure 1 shows a phase locked loop (PLL).
This figure shows the general configuration of a radio receiver using a digital tuning system. antenna 1
The signal received at 6 is amplified by a radio frequency amplifier (RF) 1, and then mixed by a mixer (MIX) 2 with a local oscillation frequency controlled by a phase locked loop from a voltage controlled oscillator (VCO) 7. and converted to an intermediate frequency signal. This intermediate frequency signal is amplified by an intermediate frequency amplifier (IF) 3, detected into an audio signal by a detector (DET) 4, and then amplified by a low frequency amplifier (AF) 5 and extracted as audio from a speaker 6. It will be done. In a receiver for FM stereo broadcasting, a stereo demodulator (not shown) is generally inserted after the detection section (DET) 4 to perform left and right stereo separation.

Phase locked frequency that determines the local oscillation frequency
The loop includes a voltage controlled oscillator (VCO) 7, a prescaler 8, a programmable counter (P counter) 9, a phase comparator 11, a reference frequency oscillator (Fref) 12, and a low pass filter (LPF).
10, a controller 13 for determining the frequency division ratio of the programmable counter 9, an operation switch 14, and a display 15 as an auxiliary circuit. When the desired reception frequency is set by the operation switch 14, the controller 13 displays the desired frequency, reception channel, broadcasting station name, etc. on the display 15, and the local oscillation frequency corresponding to the desired reception frequency is controlled by voltage. The frequency division ratio of the programmable counter 9 is set so that the oscillator 7 outputs the frequency. In this way, the operating state of the phase locked loop is set. Next, the oscillation frequency from the voltage controlled oscillator 7 is once divided by the prescaler's frequency division ratio by the prescaler 8 to lower the frequency.
The frequency is further lowered by the frequency division ratio determined by the counter 9, the phase is compared with the reference frequency from the reference frequency oscillator 12 by the phase comparator 11, and the phase comparison output is converted into DC by the low-pass filter 10. It is added to a variable capacitance diode (not shown) constituting the voltage controlled oscillator 7, and controls the local oscillation frequency by changing its capacitance.

Digital tuning systems usually have a memory function that stores multiple desired reception frequencies. The method of storing the frequency in the memory includes a function that updates the frequency by pressing the switch provided on the operation switch 14 once at a time, or a function that updates the frequency continuously by pressing the switch for more than a certain period of time until it is released. This can be achieved by setting the desired frequencies one by one using the numeric keypad and then writing them into the memory, or by using the numeric keys 0 to 9 to set the desired frequencies one by one and then writing them into the memory. ing.

Multiple frequency information once stored in memory using the above method is stored in a large capacity capacitor or battery when the main power supply (operating power supply) of the set is cut off in a radio receiver or television receiver. It is configured to be held for a long time by the holding power supply. Random access memory (hereinafter abbreviated as RAM) is generally used to store multiple frequency information.

The contents of the RAM will be destroyed if the voltage value of the holding power supply falls below a certain value, so a power failure detection circuit is built in to detect this state and set the contents of the RAM to the initial state when the main power is turned on. That is, in addition to the RAM, the holding power supply source is connected to a discrimination circuit (consisting of a prep-prop, etc.) whose output state changes depending on the potential and whose output state is maintained. This discrimination circuit determines that if the voltage of the holding power supply is higher than a certain potential, the above-mentioned flip
The output state of the flop is set to 0, for example, and the output state is forcibly set to 1 when the potential falls below a certain level. In other words, when the state of the flip-flop becomes 1, it is determined that the power has been cut off, and regardless of the state of the RAM contents in which frequency information is stored, when the receiver's operating power is turned on again, A function that sets the contents of RAM to its initial state is activated (hereinafter referred to as the power-on clear function).

The power-on-clear function initializes the RAM so that the lowest or highest frequency in the receiving frequency range is called for a radio receiver, or channel 1 for a television receiver. is common.

Now, the potential at which the flip-flop becomes 1 is
V _T1 and the threshold voltage at which the RAM data changes (destroys) are V _T2 . There is no problem if the relationship between V _T1 and V _T2 is always V _T1 = V _T2 . Normally, RAM and flip-flops for power failure detection are integrated and made on the same chip, but due to differences in their circuit configurations, their respective threshold voltages may vary.
A difference occurs between V _T1 and V _T2 . In addition, the threshold voltage V _T1 of the flip-flop for power failure detection may vary depending on the conditions in the integrated circuit production process.
Because the threshold voltage V _T2 of the RAM is different, there are differences between production rods. V _T1 and V _T2 also vary depending on the ambient temperature in which the device is used. Therefore, in the conventional power failure detection circuit,
It is almost impossible to design so that the relationship V _T1 =V _T2 holds true under all conditions.

When the relationship V _T1 <V _T2 exists, even if the data in the RAM has already been destroyed, there is a period in which a power outage is not detected, and if the operating power of the set is turned on during this period, the RAM will not be able to return to its initial setting state. Therefore, the set is treated as defective because it malfunctions, such as calling an undesired frequency or displaying an irrelevant display.

For the above reasons, conventional power failure detection circuits are designed so that the relationship _VT1 > _VT2 holds true. However, as mentioned above, V _T1 and V _T2 may vary depending on the conditions in the production process or the environment such as ambient temperature.
Because of the variation in ΔV _T =V _{T2 −V T1, if the value of ΔV T =V T2} −V _T1 is not made sufficiently large, V _T2 <V _T1 may occur.

If V _T2 is made sufficiently larger than V _T1 , problems such as malfunctions will disappear, but the limit of the voltage that can be held will be higher, and as a result, the period that can be held by a holding power source such as a large capacity capacitor or battery will be shortened. This is a big drawback.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a power failure detection circuit that does not malfunction when power is turned on for operation of a set and that can extend the holding period.

According to the present invention, a controller constituting a digital tuning system is provided with a second memory that is supplied with the same holding power as a first memory capable of storing a plurality of frequency information, and further includes a second memory that can store data in the second memory. and detecting means for storing certain information in the second memory when the initial operating power is applied, and storing certain specific information in the second memory when changing from the holding power application state to the operating power application state. By detecting the change in , a digital channel selection device is provided with a built-in power failure detection circuit that does not cause malfunction when power is turned on and can extend the holding period.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 shows the configuration of a power failure detection circuit as an embodiment of the present invention. The first memory 17 is a memory that stores a plurality of frequency information, and is programmable.
A frequency division ratio, a binary coded channel number, etc. to be output to the counter 9 are stored. The first memory 17, which stores a plurality of pieces of frequency information, has addresses corresponding to the plurality of preset switches provided in the operation switch 14, respectively.
When writing frequency information, the control circuit 19 specifies the address of the first memory 17 corresponding to the pressed preset switch, and the information output from the read/write circuit 20 is written to that address. The control circuit 19 reads/writes information to be written into the first memory 17 through the read/write circuit 2
0, the content of the memory read out by the read/write circuit 20 is determined, and a corresponding control function is performed. In the case of calling, the control circuit 19 similarly specifies the address of the first memory 17, and the contents of the specified memory are output and read by the read/write circuit 20.

When starting normal operation, first turn on the main SW
(Operating power supply) 22 is connected. At this time, +B power is stored in the holding power supply 21 via the diode 24, and is further applied to the first memory 17 and the second memory 18 in the controller 13, and is also applied to the control circuit 19 via the diode 25. applied. Hold power supply 2 when first operating power is turned on.
Since no charge is stored in memory 1, the data in first memory 17 and second memory 18 can be considered to have been destroyed.

Next, the control circuit 19 specifies the address of the second memory 18 by triggering the rising edge of the signal input through the diode 25. The contents of the designated address are read out by the read/write circuit 20 and compared with a certain predetermined value (for example, "1100" in a 4-bit configuration) in the detection circuit 23. This value is stored in a read-only memory (ROM), a latch circuit, etc. If the contents of the second memory 18 read at this time are equal to the value of the detection circuit 23, normal operation is performed;
A control signal is output to 9. This control signal causes the read/write circuit 20 and the control circuit 19 to
sets the first memory 17 to the initial setting state and sets the second memory 17 to the initial setting state.
A value equal to a specific value ("1100") prepared in advance in the detection circuit 23 is written into the memory 18, and the process then proceeds to normal operation.

Next, when the main SW 22 is disconnected, a low level signal is input to the control circuit 19 via the diode 25 to stop the operation, and the data in the first memory 17 and second memory 18 is transferred to the holding power supply 21. The stored charge holds the voltage up to the threshold voltage.

When the potential of the holding power supply 21 is higher than the threshold voltage of the first memory 17 and the second memory 18, when the main SW 22 is connected again and the operating power is applied, the first memory 17 and the second memory 18 are Since both the second memories 18 hold the data, the second memory 18 which is compared in the detection circuit 23
The content of 8 is equal to a specific value (“1100”) prepared in advance in the detection circuit 23.

Therefore, no control signal is output from the detection circuit 23 to the control circuit 19, and normal operation is performed.

If the potential of the holding power supply 21 is lower than the threshold voltage of the first memory 17 and second memory 18, the data (“1100”) in the second memory 18 has been destroyed, so the detection circuit 23 outputs the control signal. is output, and the first memory 17 and second memory 18 are initialized. Thereafter, when a channel selection operation is performed by the operation switch 14, the information is written into the first memory 17.

Here, the diode 24 is a diode for preventing reverse current from the holding power supply 21;
5 indicates that a voltage equal to the operating power supply applied to the first memory 17 and the second memory 18 is applied to the detection circuit 23.
This is a leveling diode for applying voltage to

Typically, the controller 13 uses an integrated circuit. Therefore, since the first memory 17 and the second memory 18 are both manufactured on the same chip and have the same circuit configuration, the conditions in the production process are the same, and as a result, the threshold voltages of each are also the same. Furthermore, since the chips are on the same chip and have the same circuit configuration, they are affected by the ambient temperature in the same way, and the variation width due to temperature is also the same, so that the threshold voltages of each are always the same. Using the same symbols as in the explanation of the conventional power failure detection circuit, the threshold voltage of the first memory 17 is V _T2 , and the threshold voltage of the second memory 18 is V T2 .
can be directly replaced with V _T1 , and the relationship V _T1 = V _T2 holds true.

In addition, in FIG. 2, the first memory 17 and the second
Although the blocks of the memory 18 have been described separately, the second memory 18 may be placed in an unused address of the first memory 17. Therefore, when the controller 13 is implemented using a microprocessor or the like, both the first memory 17 and the second memory 18 can be placed in the RAM section within the microprocessor, and this does not lead to any increase in costs. Furthermore, since most of the contents of RAM are all 0 or all 1 below the threshold voltage, the specific value written to the second memory 18 must be a value other than "0000" or "1111". In addition to the above-mentioned "1100", values such as "1010" or even "0101" may be used. Of course, it may be other than 4 bits.

According to the embodiment described above, the relationship V _T1 =V _T2 can be maintained under all conditions, so
The holding voltage can be lowered to the limit of the RAM threshold voltage. As the holding voltage decreases, the current consumed from the holding power source also decreases, and as a result, the period during which the holding power source such as a large capacity capacitor or battery is held is sufficiently longer than in conventional power failure detection circuits. Furthermore, since there is no relationship of V _T2 <V _T1 , malfunctions cannot occur when the operating power is turned on.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a radio receiver using a general PLL type digital tuning system, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1...High frequency amplification section, 2...Mixing section, 3...Intermediate frequency amplification section, 4...Detection section, 5...Low frequency amplification section, 6...Speaker, 7...Voltage controlled oscillator, 8
...Prescaler, 9...Programmable counter, 10...Low pass filter, 11...
Phase comparator, 12...Reference frequency oscillator, 13...
...Controller, 14...Operation switch, 15...
...Display device, 16...Antenna, 17...Memory for storing a plurality of frequency information, 18...Memory for storing information for power failure detection, 19...Control circuit, 2
0...Read/write circuit, 21...Large capacity capacitor for holding power supply, 22...Main switch, 23...Power failure detection circuit, 24, 25...Diode, 26...Resistor.

Claims (1)

[Claims] 1 A first storage section that can store frequency information input by a channel selection operation, and a second storage section that stores predetermined information by applying a power supply voltage and destroys the predetermined information by supplying a voltage below a predetermined value. A digital channel selection device comprising: a storage section; a detection means for detecting the contents of the second storage section; and means for bringing the contents of the first storage section into an initial state based on the output of the detection means.