JPS6042973B2 - Input/output information check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for checking input/output information in input/output registers used in electronic computers and the like.

Conventional methods for checking input/output information in this type of input/output register cannot completely detect errors in storing information in the register.

FIGS. 1 and 2 each show a conventional input/output information checking system, and FIG. 3 is a diagram showing the sending timing of each signal used therein. In these figures, 1 to 4 are receivers, 5 are decoders, 6 to 8 are AND gates, 9 to 11 are inverters, 101 to 103 are parity check circuits,
201 to 203 indicate input/output registers, respectively.
Generally, input/output information is transferred between a data transfer bus line DTB that sends transfer data and a data transfer/parity line DT that sends odd or even parity bits of transfer data.
P, a function line FUN that sends a code signal for selecting an input/output register, and a data transfer sampling line DTS that sends a pulse signal for sampling transfer data are prepared. This is done by sending each signal as an interface signal at the timing shown in FIG.

In other words, in FIG. 3, the period in which the logical values of the transfer data on the DTB line, the parity bit on the DTP line, and the code signal on the FUN line each exhibit a certain constant value, that is, the data This shows that data and parity bits are captured and registers are selected using sampling pulses on the DTS line during the data confirmation time. Now, in the conventional system shown in FIG.
02 and 203, and is also sent to the parity check circuit 101.

R1 due to the code signal just sent by the FUN line.
If the input/output register 201 is specified, the code signal is input to the decoder via the receiver 4, decoded by the decoder 5, and outputted to the AND gate 6, and the AND gate 6 enters the enabled state. Thereafter, when a sampling pulse is input from the DTS line through the receiver 3, an output is sent from the AND gate 6 to trigger the R1 input/output register 201, and the transferred data is stored in the register R1. On the other hand, the parity bit of the transfer data is sent from the DTP line to the parity check circuit 101 via the receiver 2, and the parity check of the transfer data is performed using a sampling pulse from the DTS line. If it is true, it will be detected. Data storage in other input/output registers 202 and 203 is performed in a similar manner. Next, the conventional method shown in Fig. 2 will be explained.The difference between the method shown in Fig. 2 and that shown in Fig. 1 is that the place where the parity check of the transferred data is performed is In contrast to the input side of the input/output register in the case of the method shown in FIG. 2, it is the output side of the input/output register. That is, in FIG. 2, I is similar to the case in FIG.
The parity bit is sent from the DTI line to the input side of the parity check circuit 101 via the receiver 2.
It is being sent to 103. Assuming that the R1 input/output register 201 is now specified by the code signal sent from the FUN line, the code signal is input to the decoder 5 via the receiver 4, decoded there, and the output is sent to the AND gate 6. , the AND gate 6 enters the permission state. After that, when a sampling pulse is input from the DTS line via the receiver 3, the AND gate 6
An output is sent from the register R1, triggering the R1 input/output register 201, and the transfer data is stored in the register R1. On the other hand, the output of the AND gate 6 is sent to the parity check circuit 101 via the inverter 9, and input/output register R1
A circuit 1011 performs a parity check on the output data stored in the . In the conventional input/output information checking method as explained above, if an error occurs in storing an even number of bits in the input/output register due to a defective circuit element or an external factor (induction nozzle, etc.), a parity check is performed. The inspection cannot detect errors, and as a result, program processing or input/output device operations in computers, etc., may be executed due to the incorrect information output from the register, resulting in loss or destruction of important information. Become. The present invention was made to overcome the drawbacks of the conventional system as described above, and an object of the present invention is to provide an input/output register that can detect errors in storing transfer information over multiple bits in an input/output register. The purpose of the present invention is to provide an output information checking method.

The main point of the configuration of the present invention is to detect an error in storing information in an input/output register by comparing the input information with the output information stored in the register and output at the same time. The configuration is as follows. Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing one embodiment of the present invention. In FIG. 4, 301 to 303 each indicate a comparison circuit. The difference between the embodiment of the present invention shown in FIG. 4 and the conventional system shown in FIG. 1 is that the input/output register 2
Comparison circuits 301 to 303 are provided on each output side of 01 to 203.
The point is that it has been established.

The operation of this circuit will be explained as follows. That is, the first
In the same way as explained in the figure, the transfer data from the DTB line is passed through the receiver 1 to each input/output register 2.
Input side of 01 to 203 and comparison circuits 301 to 3
03. Assuming that the code signal from the FUN line is a code signal specifying the input/output register R1, the output is sent from the decoder 5 to the AND gate 6 in the same manner as described above with reference to FIG. is in the permitted state. Next, when a sampling pulse is input from the DTS line via the receiver 3, the pulse passes through the AND gate 6, and at its leading edge, the input/output register R1
is triggered and the transfer data is stored in the register R1.
At the same time, the sampling pulse is transferred to the inverter 9.
is applied to the comparator circuit 301 via the sampling pulse, so that the trailing edge of the sampling pulse triggers the comparator circuit 301, and the output data that has just been stored in the register R1 and is output at the leading edge of the sampling pulse. A comparison is made with the input data on the input side of the register to check for errors in the data stored in register R1. FIG. 5 is a diagram showing another embodiment of the present invention, and in FIG. 5, reference numeral 401 indicates a selection circuit.

In the embodiment of FIG. 5, unlike that of FIG. 4, instead of providing a comparison circuit for each of the input/output registers 201 to 203, the output of each register is connected to
The voltage is applied to two comparison circuits 301. Therefore, in the same manner as described above, while the transfer data from the Dnl3 line is applied to the input sides of the input/output registers 201 to 203 via the receiver 1, and is also applied to the comparison circuit 301, Assume that the code signal from the FUN line is a code signal that specifies the R1 register 201. The decoded output of the decoder 5 opens the AND gate 6, and the DTS
A sampling pulse from the line passes through the AND gate 6 and triggers the R1 register 201.The transfer data applied to the input side of the register is captured, and at the same time, the captured stored data is outputted from the R1 register to select the circuit. Send to 401. On the other hand, R1 from the FUN line
In addition to being applied to the decoder 5, the code signal specifying the register 201 is also applied to the selection circuit 401, and R1
It functions to pass only the output of the register 201 to the comparison circuit 201. Thus, in the same manner as described with reference to FIG. via, the trailing edge triggers the comparator circuit 301,
The input side data of the R1 register 201 and the data stored and output to the register R1 are compared to detect a storage error in the register R1. Even when the code signal from the FUN line specifies other registers R2, RN, etc., the checking operation is exactly the same. The embodiment shown in FIG. 5 requires an extra selection circuit compared to the embodiment shown in FIG. 4, but only one comparison circuit is required, and overall the number of circuit elements has been successfully reduced. As is already clear from the above explanation, according to the present invention, it is possible to completely detect input/output register storage errors involving even number bits, which could not be detected by conventional checking methods. This has the advantage that malfunctions and incorrect processing can be prevented, and important information can be avoided from being lost or destroyed.

[Brief explanation of the drawing]

1 and 2 respectively show the conventional input/output information checking system, FIG. 3 shows the sending timing of each signal used therein, FIG. 4 shows an embodiment of the present invention, and FIG. 5 shows the conventional input/output information checking method. FIG. 7 is a block diagram showing other embodiments.

Claims (1)

[Claims] 1 Data transfer bus line (hereinafter referred to as D) that sends transfer data
TB line), a function line (hereinafter referred to as FUN line) that sends a code signal for input/output register selection, and a data transfer sampling line (hereinafter referred to as DTS line) that sends a pulse signal for sampling transfer data. Therefore, when selecting a specific one of the plurality of input/output registers and transferring data to that register, the data as input/output information transferred by the DTB line is transferred to the plurality of input/output registers. The code signal sent via the FUN line is then decoded to select a specific one of the plurality of input/output registers, and then the DT
In the input/output information transfer method, the sampling pulse from the S line is applied only to the selected specific input/output register, and the transfer data applied to the input side of the register is taken in and stored. Using sampling pulses given to specific input/output registers,
The data captured in the specific register and the result,
An input/output information checking method characterized by comprising a comparing means for comparing data to be output from the register and detecting whether or not there is a match.