JPS6318223B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of the Invention The present invention relates to an error processing circuit, and particularly to an error processing circuit that checks input data and stops sending out a clock signal from an oscillator when an error is detected. Related.

(b) Technical background In electronic devices, reliability of processing results is as important as data processing speed. In other words, a device with a high processing speed but with low reliability of its results is inferior to a device with a slightly slower processing speed but with high reliability of the results. To this end, various techniques for checking whether the data to be processed is correct have been developed and put into practical use. Parity check method is a typical data check technology.
Examples include the CRC method.

(c) Problems with the conventional technology As described above, from the viewpoint of the reliability of processing results, if an error is found in the data to be processed, the subsequent processing must be stopped. The practice is to stop the clock signal that controls the timing of the circuit if an error is discovered in the data. However, stopping the clock signal is accomplished by blocking the output of the clock signal in the oscillator. Therefore, a clock signal is input to the data buffer between the time the error check circuit detects the error and the time when the oscillator stops sending the clock signal, and as a result, the next data is set in the data buffer, causing an error. The data will be lost. Therefore, it has the disadvantage that it is impossible to investigate the cause of the error.

(d) Purpose of the Invention In view of the above, an object of the present invention is to provide an error processing circuit that does not erase data in which an error has occurred even if a data error occurs.

(e) Embodiments of the Invention Below, embodiments of the error processing circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram schematically showing an error processing circuit, in which 1 is a data buffer, 2 is a data check section, 3 is an oscillator, 4 is an error state section, G1 is a first gate, and G2 is a second gate. be.

The data buffer 1 has a function of receiving data to be processed from the outside and temporarily storing it, and is composed of registers. The data check section 2 checks the data stored in the data buffer 1, and is composed of, for example, a parity check circuit. The error detection signal from the data check section 2 is sent to the second and error state holding section 4. The gate 2 has a function of preventing the input signal from being sent to the output terminal when the error detection signal is output from the data check section 2. Therefore, the clock signal being sent from the oscillator 3 is blocked by the gate, and the input of the clock signal to the data buffer 1 is blocked immediately after a data error occurs. Therefore, the next data is not set in the buffer, and the data in which the error occurred remains in the buffer. On the other hand, since the gate G1 is gated later than the gate G2 by the output of the error state holding section 4, the transmission of the clock signal from the oscillator 3 is stopped.

FIG. 2 shows an error processing circuit showing the details of FIG. 1. REG1 is a 9-bit register, PC is a parity check circuit, FF1 and FF2 are flip-flop circuits, A1 to A3 are AND circuits, OR1 is an OR circuit, OSC is an oscillator.

Register REG1 is a set clock signal CLKS that inputs data to be processed from the outside to terminal C.
be memorized in synchronization with the arrival of The output of register REG1 is connected to parity check circuit PC. Parity check circuit PC is register REG1
It has a function of checking data stored in the memory using a parity check method. An error detection signal ERD1 which becomes logic 1 when an error occurs in the data is connected from the output terminal of the parity check circuit PC to the set terminal J of FF1 via an AND circuit A2. A check timing signal CHT is input to the other input terminal of the AND circuit A2.
The error signal ER from the Q terminal of FF1 is an OR circuit.
A clock inhibit signal CLKI from the Q terminal is connected to an AND circuit A1. The output from the FF of another parity check circuit is connected to the OR circuit OR. The output of the OR circuit OR is input to the set terminal J of FF2. FF
An inhibit signal ST is sent from the Q terminal of 2, which prevents the reference clock signal CLK from being sent out.
It is connected to one input of AND circuit A3,
The clock signal from the oscillator OSC is input to the other side. The output of the AND circuit A3 is input to the AND circuit A1 as a reference clock signal CLK. A clock gate signal CLKG is further input to the AND circuit A1. Note that the signal RST is a reset signal and is input to the reset terminals R of the registers FF1 and FF2. Also, CLK1 is FF
This is the clock signal for FF1 and FF2. An alarm signal ALRM is sent from the Q terminal of FF2.

Next, the operation of this circuit will be briefly explained along the time chart of FIG. Note that the signal names in FIG. 3 match the signal names in FIG. 2. The non-stop clock signal NCLK is sent out from the oscillator OSC as shown in a, and since the inhibit signal ST is logic 1, the reference clock signal CLK which is in phase with the signal NCLK is input to ANDA1. Since the clock inhibit signal CLKI and the clock gate signal CLKG are logic 1, the set clock signal CLKS is in phase with the reference clock signal CLK.
is the data register REG via the AND circuit A1
Input to terminal C of 1. Therefore, 9-bit data is set in the register by a certain set clock signal CLKS. This data is checked by the check circuit PC, and if an error is detected, the circuit PC sets the error detection signal ERD1 to logic 1. As a result, FF1 is set and the error state is maintained. By setting FF1, the terminal becomes logic 0, so the clock inhibit signal CLKI gates the AND circuit A1 and registers.
Input of set clock signal CLKS to REG1 is blocked. Therefore, data in which an error has been detected remains held in the register. on the other hand,
Since the error signal ER output from the Q terminal becomes logic 1, FF2 is also set, and as a result, the inhibit signal ST becomes logic 0, so the nonstop clock signal NCLK is blocked by the AND circuit A3, and the reference clock signal CLK is transmission is stopped.

(g) Effects of the Invention As described above, according to the present invention, input of the set clock signal CLKS to the data register is blocked at the time when an error occurs in the data.
The resulting data in error is held in that register. Therefore, it is convenient for investigating the cause of errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the outline of the error processing circuit, FIG. 2 is a block diagram showing the details of the error processing circuit shown in FIG. 1, and FIG. 3 is a time chart of the main signals in FIG. In the figure, 1 is a data buffer, 2 is a data check section, 3 is an oscillator, 4 is an error state section, G1 is the first gate, G2 is the second gate, REG1 is 9
Bit register, PC parity check circuit,
FF1 and FF2 are flip-flop circuits, A1 to A
3 represents an AND circuit, OR1 represents an OR circuit, and OSC represents an oscillator.

Claims (1)

[Claims] 1. A storage means for storing input data, a data check means for checking the data stored in the storage means, an oscillation section for sending a clock signal for controlling data storage timing to the storage means, and a data check means for the data check means. Accordingly, when a data error occurs, an error state holding section stores and holds the state; a first gate means prevents the sending of a clock signal in the oscillation section by the output of the holding section; An error processing circuit comprising second gate means for blocking input of a clock signal to the storage means.