JPH0750454B2 - Channel device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel device, and more particularly to a channel device suitable for processing when a data overrun occurs when data is transferred by a data streaming method.

[Conventional technology]

In data transfer of the data streaming system, the input / output control device issues data transfer requests one after another without waiting for a response from the channel device, so that high throughput can be obtained and the possibility of data overrun also increases.

Conventionally, in the case of data streaming type data transfer, the input / output control device compares the number of tag signals (INTAG) of the data transfer request sent to the channel device with the number of tag signals (OUTTAG) responded by the channel device. Detect overrun. When a data overrun is detected during data transfer, the input / output control unit sets the unit check bit of the device status byte after the data transfer to "1" and reports the abnormal end of the data transfer to the channel device. In this case, the hardware tries to transfer the data.

On the other hand, the channel device reports the state of the channel to the program as a channel status byte after the completion of all data transfer. The channel status byte contains an interface control check bit that indicates a failure on the IO interface. When the value of the unit check bit of the device status byte reported from the input / output control device is "1", the channel device reports the interface control check bit to "1" to the program. In this case, the program tries to retry the IO instruction.

Note that, for example, Japanese Patent Laid-Open No. 59-165121 discloses that a data overrun is detected by the channel device itself. However, it is detected that the data transfer is abnormally terminated due to the data overrun, and Is left to the I / O controller, and no consideration is given to the case where the I / O controller has not detected the data overrun despite the occurrence of the data overrun. The following cases may be considered as a case where the input / output control device does not detect the data overrun despite the occurrence of the data overrun. When the overrun detection circuit of the I / O control unit failed and did not operate normally. When it cannot be detected in principle due to the configuration of the overrun detection circuit of the input / output control device. this is,
It occurs because the number of INTAG and OUTTAG is counted by the finite number of bits counter. For example, when counting with a 4-bit counter, if the difference between the number of INTAGs and the number of OUTTAGs is an exact multiple of 16, it cannot be detected.
When due to noise. This is because there is noise on the IO interface or inside the IO controller even though the channel device overruns and responded with less OUTTAG by 1 byte, and the IO controller received this noise and an extra byte was added. As a result of counting OUTTAG
This is the case where the number of INTAGs and the number of OUTTAGs match and they are not detected as an overrun.

[Problems to be solved by the invention]

In the prior art, when data transfer is performed between the channel device and the input / output control device by the data streaming method, the input / output control device side reports to the input / output control device side whether or not the data transfer is normally completed. In this case, if a data overrun occurs due to an error in the IO interface cable or the I / O controller, but the I / O controller does not detect it, the unit check bit in the device status byte will change. Since it is "0", the channel device reports the interface control check bit of the channel status byte to the program as "0" (normal), and the data in the memory may be destroyed.

An object of the present invention is to input erroneous data to a memory even if the input / output control device does not detect the data overrun when the data overrun occurs. Another object of the present invention is to provide a highly reliable channel device capable of preventing a phenomenon of so-called data destruction, in which incorrect data is output to an external output device.

[Means for solving problems]

The purpose of the above is to detect and store a data overrun in the channel device, to detect whether or not a unit check bit is attached to the device status byte reported by the input / output control device, and after the data transfer is completed. ,
When the means for storing the overrun is "1" and the value of the unit check bit of the device status byte reported by the I / O controller is "0", the interface control check bit of the channel status byte is set to " This is achieved by providing a means for setting the 1 ".

[Action]

When the channel device detects that a data overrun has occurred during data transfer by the data streaming method, for example, the flip-flop indicating that is set to "1". After the data transfer is completed, the unit check bit of the device status byte reported from the input / output control unit is checked, and even if the bit is "0" (normal), if the flip-flop is "1", Set the interface control check bit of the channel status byte to "1" (abnormal) and report to the program. As a result, it is possible to prevent the data in the memory from being destroyed due to the abnormality of the IO interface cable or the input / output control device. In addition, the abnormality of the IO interface cable or the input / output control device here is the overrun detection circuit. Alternatively, it is assumed that the report circuit or the like is partially abnormal or accidental. Generally, the input / output control device can report the device status byte to the channel device even if there is a partial abnormality or accidental abnormality.

It is obvious that the phenomenon of memory data destruction must be absolutely avoided regardless of which device in the data processing system is abnormal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing a relationship among a memory device, a channel device and an input / output control device. The channel device 2 and the input / output control device 3 transfer data by the data devices BUSI0-8 and BUSO0-8 having a 1-byte width. The data transfer is controlled by INTAG (SRVI or DATI) of the data request from the input / output control device 3 and OUTTAG (SRVO or DA of the response from the channel device 2 to the INTAG.
TO) and. The channel device 2 includes a data buffer control circuit 10, a tag control circuit 20, and an abnormality report bit (interface control check bit) setting circuit.
30 and an abnormality report bit latch 40.

FIG. 2 is a diagram showing a part of the configuration of the tag control circuit 20 in FIG. 1, and is a circuit for outputting the SRVO signal in response to the SRVI signal. The SRVI signal received by the channel device 2 is sent to the SRVO sending circuit 23 through the synchronizing circuit 21 and the stage circuit 22. On the other hand, the overrun detection circuit 24 is the data request SRVI signal, the output of the stage circuit 22 is the rising differential signal of the SRVI signal, the SRVIUP signal, the output of the data buffer control circuit 10, and the data buffer can be used. Input the DATRDY signal indicating that the data transfer is being performed and the DSM signal indicating that the data is being transferred by the data streaming method. If the data transfer request exceeds the processing capacity of the channel device 2, the OVRUN signal is sent. Output a signal. The SRVO sending circuit 23 is the output of the stage circuit 22.
STSRVO signal, DRDY which is the output of overrun detection circuit 24
Input the STOP signal that indicates the stop of signal and data transfer,
SRVO signal is output in response to SRVI.

FIG. 3 is a diagram for extracting and explaining the abnormality report bit set circuit 30 in FIG. This abnormality report bit set circuit 30 is an output signal of the data buffer control circuit 10.
BUSI7 (unit check bit of device status byte), output OVRUN of overrun detection circuit 24, tag signal STAIN indicating that device status byte is placed on BUSI0-8 from input / output control device 3, between devices Is a circuit for inputting a signal BURST indicating that data transfer is currently being performed or after data transfer is completed, and sets the abnormality report bit latch 40. The output of the latch 40 becomes an interface control check (ICC) bit which is an abnormality report signal to the program.

The operations of the SRVO transmission circuit 23, the overrun detection circuit 24, and the abnormality report bit set circuit 30 according to the present invention will be described in detail below.

FIG. 4 shows that when the SRVI signal for data request exceeds the processing capacity of the channel device 3 in the SRVO sending circuit 23 and the overrun detection circuit 24, the SRVI signal for the data request is issued.
A configuration example in which the SRVO signal with respect to the signal is made non-responsive and at the same time the overrun flip-flop 107 is set and stored is shown. In FIG. 4, 100, 104, and 105 are clock drivers with AND gates, and 108 and 109 are inverters.

The SRVI signal from the input / output control device 3 is received by the receiver 111. If no data is prepared in the data buffer (not shown) when this SRVI signal rises, DATRDY
The signal is "0", the flip-flop 101 is reset to "0", and the DRDY signal becomes "0". Then, AND gate 1
The output of 02 becomes "0" regardless of the value of the STOP signal, the flip-flop 106 is set to "0", and the output of the driver 110
SRVO becomes “0” and there is no response. At the same time, in the case of data streaming type transfer, the signal DSM is “1”,
The AND condition of the AND gate 103 is established via the inverter 108, and the flip-flop 107 that stores the overrun is set to "1" by the rising differential signal SRVIUP of the SRVI signal and the clock, and the OVRUN signal becomes "1". .

FIG. 5 is a detailed diagram of the abnormality reporting bit set circuit 30,
A configuration example in which the interface control check bit (ICC: error report bit) of the channel status byte is set to "1" even if the unit check bit of the device status byte is "0" when the overrun flip-flop 107 is "1" Show. In FIG. 5, 200
And 205 are clock drivers with AND gates.

The unit check bit BIN7 in the device status byte reported by the input / output control device 3 is set in the flip-flop 201. When the status is received at the end of the data transfer, the BURST signal is "1" and the STAIN signal is "1", so that the AND condition of the AND gate 202 is satisfied.
At that time, even if the flip-flop 201 is "0" ,. OVR
If the UN signal is "1", the AND condition of the AND gate 203 is satisfied, the abnormality report bit latch 40 is set via the OR gate 204 and the driver 205, and the driver 207 sets the ICC bit of the channel status byte to "1". "It becomes.

〔The invention's effect〕

According to the present invention, when a data overrun occurs during data transfer in the data streaming system, the device status byte of the unit check is not reported to the channel device due to an abnormality in the IO interface cable or the input / output control device. However, since the abnormal data transfer is reported to the program from the tunnel device, the data destruction of the memory can be prevented and the reliability is improved.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a configuration example of a tag control circuit of the present channel device in FIG. 1, and FIG. 3 is an abnormality report bit set circuit of the same channel device. Showing the input / output relation of the circuit, FIG. 4 is a diagram showing a concrete configuration example of the SRVO sending circuit and the overrun detection circuit in FIG. 2, and FIG. 5 is a concrete configuration example of the abnormal bit setting circuit in FIG. FIG. 1 ... Memory device, 2 ... Channel device, 3 ... Input / output control device, 10 ... Data buffer control circuit, 20 ... Tag control circuit, 30 ... Abnormality report bit set circuit, 40 ... Abnormality report bit latch.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Mr. Tadashi Sato, 1 Horiyamashita, Horiyamashita, Hadano, Kanagawa Prefecture (56) References Japanese Patent Laid-Open No. 59-165121 (JP, A)

Claims (1)

[Claims] Claim: What is claimed is: 1. A channel device for performing data transfer with an input / output control device according to a data streaming method, means for detecting and storing an overrun of data transfer, and a unit check bit of a device status byte reported from the input / output control device. Means for detecting whether the data transfer is abnormally terminated, and when the data transfer is completed, the data transfer overrun is performed even if the unit check bit of the device status byte does not indicate the abnormal end of the data transfer. A channel device having means for setting an abnormality report bit of a channel status byte to be reported to a program when is stored.