JPS6045453B2 - multiprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor, and more particularly to a method for stopping debugging in a multiprocessor system including a plurality of processors.

Conventionally, this type of debugging stop has been performed for each processor, so in a multiprocessor system consisting of a plurality of processors, when debugging is stopped, each processor operates asynchronously.

As a result, a situation occurs where one processor in the system has stopped, but other processors are still executing instructions, so the contents of resources commonly used in the system, such as the contents of main memory, may change. The drawback was that it could not necessarily be used as debugging data. Furthermore, when starting instruction execution in a state where debugging is stopped, there is a drawback in that an instruction to start instruction execution must be given to each processor. The purpose of the present invention is to
In order to eliminate the above-mentioned conventional drawbacks, the state of the system when a debug stop condition is detected can be accurately used as debug data, and all processors in the system that are in a debug stop state can be instructed to execute instructions. The object of the present invention is to provide a multiprocessor capable of performing initiation.

In a multiprocessor system consisting of a plurality of processors, the present invention provides a means for setting a condition for stopping debugging, a means for detecting that the condition for stopping debugging is satisfied, and a means for detecting whether the condition for stopping debugging is met, and a method according to the output of the detecting means. An object of the present invention is to provide a multiprocessor, characterized in that the multiprocessor is equipped with means for instructing its own processor and other processors in the multiprocessor system to stop debugging.

In a multiprocessor system consisting of a plurality of processors, the present invention also provides a means for setting a condition for stopping debugging, a means for detecting that the condition for stopping debugging is met, and an output of the detecting means. means for instructing the own processor and other processors in the multiprocessor system to stop the debugging in response;
means for instructing the start of instruction execution; means for detecting that this instruction has been issued in a debugging halted state; An object of the present invention is to provide a multiprocessor comprising means for activating a starting operation of a multiprocessor.

Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a system configuration diagram having a debug stop function in a multiprocessor system.

In the first figure, 1 and 2 are processors, and these processors 1 and 2 are instruction execution units 1a and 2a1, and an inter-instruction event control unit 1 that controls events processed between instructions.
b, 2b1 a debug stop control unit 1c that detects conditions for debug stop and instructs to stop debug and start executing instructions;
2c, communication control units 1d and 2d that perform communication between processors;
and maintenance panel control units 1e and 2e having an interface with the maintenance panel. Further, 3 is a main storage device, and this main storage device 3 includes a debug control table 3a. Such a debug control table 3a is
As shown in FIG. 2, debug stop start point address 3a1
, debug stop target address 3a2, and debug stop target data 3a3. The flowcharts shown in FIGS. 3 and 4 show the operations of the inter-instruction event control section and the debug stop control section regarding 5 debug stops.

Next, a case will be described in which, in the multiprocessor according to the present invention as described above, the condition for stopping debugging is satisfied when the contents of a specified address on the main storage device 3 is rewritten as a condition for stopping debugging. .

The debug stop condition is set by, for example, executing an instruction to enable debug stop in the instruction execution unit 1a of the processor 1, and preparing the debug stop start point 3a1 and debug stop target address 3a2 on the debug stop table 3φa. The activation of debug stop is instructed and recorded.

Furthermore, as shown in the flowchart of FIG. 3, in the inter-instruction event control unit 1b, when the execution of an instruction is completed (41 and 42 in FIG. 43 in FIG. 3) If activated, an instruction to detect a debugging stop condition is given to the debugging stop control unit 1c (45 in FIG. 3). Furthermore, when detection of debugging stop conditions is instructed (51 in Figure 4), it is checked whether the debugging stop starting point has been passed (52 in Figure 4).
, the instruction counter value at that time is compared with the debug stop start point address 3a of the debug control table 3a (53 in Figure 4). Suspension target address 3
The contents of the main storage device 3 at that point indicated by a2 are read out and stored in the debugging stop target data 3a3,
The passage through the starting point is recorded (54 in FIG. 4), and execution of the next command begins (55 in FIG. 4).

Further, when the instruction counter value and the debug stop start point address 3a1 of the debug control table 3a are compared and they do not match, the comparison operation between the instruction counter value and the debug stop start point address is performed every time one instruction execution is completed until they match. (41 → 42 → 4 in Figures 3 and 4)
3→45→51→52→53→55 are repeated).
In this way, the debugging stop starting point can be passed through 5 in Figure 4.
2, the contents of the main memory indicated by the debug stop target address 3a2 are read out and compared with the debug stop target data 3a3 (56 in FIG. 4). When the debug stop target data 3a3 match in this way, the communication control unit 1d is requested to instruct all processors in the system to stop debugging (57 in FIG. 4), and the own processor is placed in the debug stop state. and records that the debugging stop state has been entered (58 in FIG. 4). Further, if the debug stop target data 3a3 do not match, the process is repeated until the debug stop target data 3a3 match each time one instruction is executed (41 → 42 → 4 in FIGS. 3 and 4).
3→45→51→52→56→55). The communication control unit 1d, which has thus received the instruction to stop debugging from the debugging control unit 1c, communicates with the processor 2 on the receiving side to stop debugging. In the processor 2 on the receiving side, the communication control unit 2d receives the communication, determines that the content of the communication is an instruction to stop debugging, and displays that it is an instruction to stop debugging from another processor. This display is determined by the inter-instruction event control unit 2b when one instruction is completed (
44) in FIG. 3, the debugging stop control unit 2c is instructed to stop debugging (46 in FIG. 3). The debug stop control unit 2c receives an instruction from 59 in FIG. 4, stops its own processor, and records that it has entered the debug stop state. From the operation explained above, all processors in the multiprocessor system (in this example, two processors 2)
, 3) enters the debugging stopped state. Next, the operation of starting execution of instructions in a system that is in a debugging halt state will be described. When a switch on the maintenance panel of a certain processor (for example, processor 1) in the system instructs the maintenance panel control unit 1 to start executing instructions, the maintenance panel control unit 1
e instructs the debug stop control unit 1c to start executing instructions. This debug stop control unit 1c determines that the command to start instruction execution (61 in FIG. 4) is made in the debug stop state (62 in FIG. 4), and instructs other processors to start instruction execution. Instruct. With this instruction, the communication control unit 1d is started (63 in Fig. 4) and instruction execution is started in the own processor.
64 in FIG. 4) and instructs the inter-instruction event control unit 1b (4th
At 65) in the figure, instruction execution begins. The communication control unit 2d of the processor 2 that received the communication debugs the debug stop control unit 2c.
The debugging stop control unit 2c issues an instruction to start instruction execution to the
Then, an instruction to start executing the command (66 in FIG. 4) is received. With this instruction, what was done during the debug stop is checked (67 in Figure 4), the debug stop is activated, the debug start point has been passed, and the debug stop state is returned to its original state, and an instruction is given to the inter-instruction event control unit 2b. (65 in FIG. 4), the execution of the instruction begins. Through the operations described above, instruction execution by all processors in the system is started. Therefore, according to the multiprocessor according to the present invention, a processor that detects a debugging stop condition when stopping debugging not only stops debugging itself, but also stops all other processors in the system. By instructing debugging to stop and causing all processors in the system to stop debugging, the state of the system when the debugging stop condition is detected can be accurately used as debugging data.

In addition, when starting instruction execution in a system that is in a debugging halt state, in any one processor,
By instructing the start of instruction execution, all processors in the debugging halted state in the system can be caused to start executing instructions. By configuring a multi-processor system using the processors described above, the present invention makes it possible to collect accurate data with no time constraints when debugging is stopped, and to start instruction execution from the maintenance panel of one processor. This has effects such as being able to start execution.

BRIEF DESCRIPTION OF THE DRAWINGS The drawing shows an embodiment of a multiprocessor according to the invention,
Fig. 1 is a system configuration diagram that has a debug stop function in a multiprocessor system, Fig. 2 is an explanatory diagram showing the seven contents of the debug control table in Fig. 1, and Fig. 3 is an instruction for the processor shown in Fig. 1. FIG. 4 is a flowchart showing the operation of the debug stop control section of the processor shown in FIG. 1.

11, 2... Processor, 1a, 2a... Instruction execution section, 1b, 2b... Inter-instruction event control section, 1c, 2c.
...Debug stop control unit, 1d, 2d...Communication control unit, 1e, 2e...Maintenance panel control unit, 3...Main storage device, 3a...Debug control table, 3a1...
Debugging stop start point address, 3a2...Debugging stop target address, 3a3...Debugging stop target data.

Claims (1)

[Claims] 1. In a multiprocessor system consisting of a plurality of processors, means for setting a condition for stopping debugging, means for detecting that the condition for stopping debugging is met, and means for detecting that the condition for stopping debugging is satisfied. A multiprocessor comprising means for instructing its own processor and other processors in the multiprocessor system to stop the debugging in response to an output. 2. In a multiprocessor system consisting of a plurality of processors, there is a means for setting a condition for stopping debugging, a means for detecting that the condition for stopping debugging is satisfied, and a means for setting the own processor and the means for instructing other processors in the multiprocessor system to stop the debugging; means for instructing the start of instruction execution; means for detecting that this instruction is made in a debugging stopped state; A multiprocessor comprising means for activating an instruction execution start operation for the own processor and other processors in the multiprocessor system in response to an output.