JPS6155684B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time-of-day clock synchronization method in an information processing apparatus having a multiprocessor configuration.

Generally, an information processing device has a built-in clock that shows a consistent elapsed time in order to display the date and time, that is, a means called a time-of-day clock (TOD). This clock is usually
It takes the form of a 64-bit binary counter, whose bit positions are numbered from 0 to 63, corresponding to the bit positions of an unsigned double-precision fixed-point number. The time is obtained by incrementing the value of a counter based on the rules of unsigned fixed-point arithmetic. Basically, the counter is incremented by adding 1 to bit position 51 every 1 microsecond.

By the way, when configuring a multiprocessor, each processing unit has a time-of-day clock (TOD) as described above, but from the perspective of the program, it is logically necessary to assume that there is one TOD. Therefore, the TOD value of each processing device must always have the same content. In such cases, conventional methods such as those described below are used to
The TODs are synchronized to ensure that the TOD contents of each processing device match.

Figure 1 shows an example of a multiprocessor configuration.
CPU-A and CPU-B are processing units each with a built-in TOD, MS is a main memory shared by CPU-A and CPU-B, and SCU is a storage controller that controls memory access from CPU-A and CPU-B. The device, SVP, is a service processor. In addition, in Figure 1
Although we assumed that the SVP connected to CPU-A has a clock (CLOCK), this clock is equipped with battery power and can operate even when the CPU system power is off, so it can be used when starting up the system, etc. The contents are moved to TOD in CPU-A.

FIG. 2 is a flowchart for explaining a conventional TOD synchronization method for the multiprocessor configuration shown in FIG. First, an initial program load (IPL) operation is performed from CPU-A to load a program into the MS, and then control is given to the program. In this way, after CPU-A has performed some work necessary for IPL operation, CPU-A
To start B, SIGP (SIGNAL
PROCESSOR) instruction and SCK
(SET CLOCK) instruction. The SCK instruction is
This is an instruction to set a value in TOD. For example, the value is X "AAAAAAAAAOOOOOOOO" and the lower 32 bits are set to zero. At this time, the operator normally turns on the instruction suppression switch SW, so the SCK instruction is not executed, and the idle reading of the SCK instruction is repeated several times as shown in FIG. During this time, CPU-B also issues the SCK instruction after performing various preprocessing. The value at this time is X "AAAAAAABOOOOOOOO", which is 1 added to bit position 31 of TOD of CPU-A, but since execution of this instruction is inhibited by the instruction suppression switch SW, the SCK The blank reading of the command will be repeated several times. After that, when the instruction suppression switch SW is turned off by the operator's manual operation, the TOD of CPU-A is
“AAAAAAAAAOOOOOOOO” is set,
X for TOD of CPU-B
The value “AAAAAAABOOOOOOOO” is set. Thereafter, the value of TOD of CPU-A increases by adding 1 to bit position 51 every 1 μs. During this time, the TOD of CPU-B is in a stopped state. And TOD of CPU-A
When the carry goes up to bit position 31, the TOD of CPU-B becomes active in synchronization with it, so the TOD of CPU-A and CPU-B will have the same contents from now on and will be updated synchronously. .

As described above, it has conventionally been common for an operator to manually turn on and off the command suppression switch to synchronize the TOD. The disadvantage of this conventional method is that the instructions are looped until the instruction inhibit switch is manually turned off, which wastes the computer and takes a long time to complete the synchronization. In addition, as the automation of operations has progressed recently, there has been a demand for an automatic IPL function that automatically performs IPL operations without human intervention, and the conventional TOD synchronization method that required manual operations has It is becoming increasingly difficult to meet such demands.

An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to make it possible to perform TOD synchronization on a program without manual operation when a multiprocessor is configured.

Therefore, a feature of the present invention is that TOD is synchronized by executing an instruction to set a value in TOD regardless of the state of the instruction inhibit switch.

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 3 is a diagram in which the conditions for setting a value in TOD according to the present invention are realized in hardware. In Figure 3, signal 1 is the conventional SCK (SET
CLOCK) A signal indicating that the instruction is being executed, and signal 2 indicating the state of the instruction inhibit switch.
When the AND condition is set by the AND circuit 4 and the instruction inhibit switch is turned off, the TOD set enable signal 9 is generated through the OR circuit 6, and the TOD set permission signal 9 is generated through the OR circuit 6.
The above contents (value set to TOD) are set to TOD7.

The above is the conventional case, but in the present invention, in addition to this, signal 3 indicating that an automatic IPL mechanism is provided, and the command suppression switch newly introduced in the present invention can be set to TOD regardless of the state. A signal 10 indicating that an instruction is to be executed enters the AND circuit 5, and when the AND condition of both signals is taken,
TOD set permission signal 9 is generated through OR circuit 6, and the contents on bus 8 are set to TOD 7.

Next, the TOD synchronization operation of the present invention will be explained using the multiprocessor configuration shown in FIG. 1 as an example. Figure 4 is a flowchart for this purpose. IPL operation is
This is done from CPU-A, and at this time, the contents of the SVP's battery-powered clock (CLOCK) are automatically set to CPU-A's TOD. After CPU-A performs several operations necessary for IPL operation, CPU-A issues a SIGP instruction and STCK (STORE) to start CPU-B.
CLOCK) command and saves the contents of TOD of own CPU-A to MS. For example, the content at this time is
“AAAAAAAAAOXXXXXXX”. here,
Although the lower 28 bits do not necessarily have to be zero, it is desirable that they be zero, considering that sufficient time is required until CPU-B is started and the SCK instruction is executed. From now on, CPU−
The value of TOD of A increases by adding 1 to bit position 51 every 1 μs.

On the other hand, CPU-B adds 1 to bit position 31 of the value saved in the MS and sets the lower 28 bits to zero, that is, X “AAAAAAABOOOOOOOO”.
is set to the TOD of own CPU-B by the SCK command. After that, the TOD of CPU-B is the same as that of CPU-A.
It is in the stop state until the carry rises to bit position 31 of TOD and is at rest. CPU-A
When the carry goes up to bit position 31 of the TOD, the TOD of the CPU-B becomes active at that timing, and the contents of the CPU-A and CPU-B are thereafter updated synchronously with the same content.

In addition, when implementing the method, the conventional manual method is also necessary in cases such as when the SVP's battery-equipped power supply breaks down, and as shown in Figure 3, the conventional method and the method of the present invention can be used together. desirable.

With the configuration as described above, the following effects can be obtained in the present invention.

1. When a multiprocessor is configured, each TOD can be synchronized without manual operation, so IPL operations can be fully automated.

2. Synchronization time can be shortened because instructions do not loop during TOD synchronization processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a multiprocessor configuration, FIG. 2 is a flowchart for explaining a conventional TOD synchronization method, FIG. 3 is a diagram showing a hardware configuration of an embodiment of the present invention, and FIG. The figure is a flowchart for explaining the TOD synchronization method of the present invention. 4, 5...AND circuit, 6...OR circuit, 7...
Time of Day Clocks (TOD).

Claims (1)

[Claims] 1. In a multiprocessor that includes a plurality of information processing devices each having a built-in clock means (time-of-day clock) that continuously indicates elapsed time to display the date, time, etc., the information processing device sets an initial value to the clock means. first means manually operated to permit or inhibit the execution of an instruction to set an initial value; and second means for enabling execution of an instruction to set an initial value in said clock means, regardless of the state of said first means.
When the second means sets an initial value in the clock means of the own device according to a command, the first information processing device starts the clock means to advance, Storing the value in the memory and instructing another second information processing device to set the clock means, the second information processing device receiving the instruction reads the contents of the memory,
A value obtained by adding a predetermined value thereto is set in the clock means of the own device, and the progress of the clock means of the first information processing device is inhibited until the contents of the clock means of the first information processing device match the set value of the clock means of the own device. A time-of-day clock synchronization method characterized by: