JPS604658B2 - Inverter control signal method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control signal system for an inverter, and more particularly to a signal system that allows the phases of a basic signal and an output voltage to always match despite fluctuations in load and input voltage.

A so-called commercial synchronous uninterruptible power supply shown in FIG. 1 is generally known as an example of operating an inverter in synchronization with a basic signal.

This function is such that the inverter normally operates in synchronization with the commercial power supply to supply power to the load, and also has the function of switching the load without momentary interruption in the event of an inverter failure.This will be explained below. FIG. 1 is a block diagram showing an example of the configuration of the device.
1 is a commercial power supply input terminal, 2 is a DC power supply input terminal, 3 is an AC output terminal, and 4 is a known semiconductor inverter in which the outputs of inverter units 5 and 5' are multiplexed by output transformers T1 and T2. be.

6 is a control circuit for the inverter 4, 7 is an LC filter circuit for making the output of the inverter a sine wave, and 8 is a semiconductor switch for switching the commercial power supply and the inverter output to the load without disconnection.

FIG. 2 is a block diagram showing an example of the configuration of the control circuit 6. The PLL is composed of a phase comparator PC, a low-pass filter LPF, a voltage controlled oscillator Vco, etc., and has the function of sending basic pulses as a signal synchronized with an external signal. integrated circuit (
PmseLockedL momme p) FD is a frequency divider, AMP is an intensifier, DT is a detector, and PS is a phase shifter.
This will be explained using the waveform diagram of each part shown in the figure.

First, to explain the constant voltage control operation of the inverters 5 and 5', the integrated circuit PLL of the control circuit 6 receives, for example, a 50Hz commercial basic pulse (Fig. 3a), and transmits it to the voltage controlled oscillator Vco via the low-pass filter LPF. It is sent out as a synchronized signal (Fig. 3b) at 6 times the frequency (300Hz).

The frequency divider FD divides the signal into a 50Hz signal (Fig. 3c
o) and two signals with a phase shift of 600 (same cl
, c2) and sends it to the multiplier AMP. This causes the intensifier AMP to generate a sawtooth comparison pulse (the third
dl, d2) (or a triangular wave pulse described later) and output voltage detection level of the detector DT (L1, d2 in the same figure).
Control pulses having different phases formed in comparison with L2) are sent out as signals for the inverters 5 and 5'. As a result, the output voltages of inverter units 5 and 5' are
As shown in Figures g1 and g2, the output becomes a controlled waveform, and these are connected in series on the secondary sides of transformers T1 and T2 and are superimposed (Figure 3H). It is shaped into a wave (Fig. 3, 1) and supplies power to the load. - direction phase shifter PS detects the above output phase and compares it with the reference phase by 90°.
0 shift (FIG. 3J) By sending this as an external signal to the phase comparator PC of the integrated circuit PLL, the commercial power supply and the inverter output voltage are synchronized. In an inverter control system having such a configuration, the integrated circuit PLL cannot immediately follow a sudden change in the commercial frequency due to the action of the low-pass filter LPF. Therefore, there is no problem in steady state, but when the load suddenly changes (for example, when the load power supply is switched from the commercial power source to the inverter or vice versa by the semiconductor switch 8), a phase shift occurs between the commercial power source and the inverter output. This is because, as shown in FIG. 4, the inverter output voltage deviates from the filter input voltage due to the load current flowing through the LC filter 7 for making it a sine wave.

Incidentally, Figures 5A to 5A are experimental diagrams showing the relationship between the filter input voltage waveform VI and the output voltage waveform VO due to the load current (in the figure, the input voltage waveform a and the output voltage waveform b are shown superimposed on each other). ) Diagrams A to C are invars.
input voltage (DCIOOV), output voltage (AC100V)
), the load current is zero (Fig. 1) and 3 (Fig. 1) and 3, respectively.
The waveform diagram shows the state in which the current has changed to 0A (Fig. C), and the waveforms shown in Fig. 2 and 2 are the waveforms when the full load current (3M) is supplied at the same input voltage (DC90V) (Fig. 2) and (Fig. E) (DC80V). As is clear from each figure, the peak of the output voltage (sine wave) is synchronized at the end of the peak point of the filter input voltage. This is because, as shown in FIG. 4, when the load current changes due to the reactance of the transformers T1, T2 and the filter L, a phase shift occurs between the filter input current and the same voltage. Figures 6A to 6C are waveform diagrams that actually measured this situation (VI in the figure is the input voltage waveform, 11 is the input current waveform), respectively. As is clear from the figure, when there is no load (OA), the lead current is approximately 90o, and when the load is intermediate (1h), the lead current decreases, and when everyone is loaded (30A). becomes a leading current of about 20o.

In this way, in the conventional system, even if the commercial power supply and the inverter output are synchronized in steady state, a sudden change in load causes a shift in the output phase of the filter 7, so the phase shifter PS
The feedback signal B sent to the integrated circuit PLL' via the integrated circuit PLL' is not synchronized with the external signal A, and the integrated circuit PLL has a response time corresponding to the detection phase shift in response to the action of the low-pass filter LPF. It shifts. As a result, there are drawbacks such as the inability to perform instantaneous commercial synchronization. The present invention aims to solve the above-mentioned drawbacks at once and provide an inverter control signal system that can be instantaneously synchronized to commercial power regardless of sudden changes in load, etc., and focuses on the phase of the front and rear stages of the filter depending on the load current. , a reverse sawtooth wave is used as a comparison pulse in the intensifier, and output control is performed from the front end of the control pulse by comparison with a detection level.

7 and 8 are block diagrams showing a configuration example of the inverter AMP applied to the present invention and waveform diagrams of each part for explaining the control signal system. circuits D1 and D2 that generate inverse sawtooth waves (waveforms with fast rising slopes and gentle falling slopes) having a frequency twice the fundamental (output) frequency to be used; dl, d2) of the detector DT (Fig. 8L)
1, L2), the front end is controlled (front edge) according to the detection level, and the square wave voltage is applied only during the period when the rear end is synchronized with the rise of the reverse mirror tooth wave (Fig. 8 el, e2). It is composed of a comparison circuit COP that generates a square wave voltage, a flip-flop circuit (FF1, FF3) that inverts when the square wave voltage rises, a flip-flop circuit (FF2, FF4) that inverts when the square wave voltage falls, etc.
'The signals g1, g2, g3, and g4 in FIG. 8 are sent to the gates, respectively.

In response to such signals, the inverter units 5 and 5' generate output voltages as shown in FIG. 8 V1 and V2 at full load to the transformers T1 and T2 (output medium 1), and at light load, output voltages shown in FIG. 8 VI' are generated.
, V2' (during output a2), respectively, generate controlled output voltages.

The voltages V1, V2, VI', V2' are V12, V12' on the secondary side of the transformer, that is, on the input side of the filter 7.
After being superimposed as shown in FIG. 3, the signals are shaped by a filter 7, and the sine wave output shown in FIG. VO' is supplied to a load. As described above, according to the method of the present invention, when applied to a commercial synchronous type uninterruptible power supply device, etc., as shown in FIG. There is no phase shift. Therefore, there is no phase shift between the filter input voltage and the output voltage, and no phase change occurs in the feedback signal B transmitted to the integrated circuit PLL via the phase shifter PS, so that stable commercial synchronization can always be achieved. Incidentally, FIGS. 9 and 10 show waveform diagrams of various parts of the conventional system in comparison with the embodiment of the present invention, and FIG. A method of controlling from the rear end of the pulse and a method of controlling from the center of the pulse using the same triangular wave are shown in FIG. 10, respectively.

As is clear from the drawing, in the conventional system, a phase shift 6 occurs in the inverter output voltage VO' at full load and at light load. According to experiments conducted by the inventor, the phase difference between the filter input voltage and the output voltage when the inverter input voltage is constant and the load is changed to no load for the embodiment of the present invention and the conventional method described above has been determined. In the case of the control method (Fig. 9), 22o, triangular wave (
In contrast to the phase difference of 11 o in the case of FIG. 10), it was confirmed that the phase difference was 0 in the case of the control method of the present invention. 1st
Figure 1 is a waveform diagram of each part of the embodiment of the present invention measured when the load power supply is switched from commercial power supply to inverter output in the power supply device, and Figures 12 and 13 are waveform diagrams of corresponding parts of the conventional system. In each figure, A is the commercial output voltage waveform, A' is the inverter output voltage waveform, C is the output (load) voltage waveform, C is the inverter output current waveform, and T is the load current waveform when switching between the commercial CM and the inverter INV. show. That is, as is clear from the drawing, in the method of the present invention (FIG. 11), when the load is switched from the commercial CM to the inverter INV (time T), both A and A' are synchronized after only half a cycle. In both conventional methods (FIGS. 12 and 13), the time tl required until synchronization is long, indicating that instantaneous synchronization is impossible.

As is clear from the above description, according to the method of the present invention, synchronization can be performed without disconnection during sudden load changes or load switching, so it is suitable for controlling commercial synchronous type uninterruptible power source devices.
The practical effect is extremely large.

[Brief explanation of the drawing]

Figures 1, 2, and 4 are block diagrams of the commercial synchronous uninterruptible power source, a block diagram of its control circuit, and a filter circuit diagram, and Figures 3, 5, and 6 are the same power supply. FIG. 7 is a block diagram of an increaser circuit applied to an embodiment of the present invention. FIG. 8 and FIG. 11 are waveform diagrams of various parts to explain an embodiment of the present invention. , FIG. 10, FIG. 12, and FIG. 13 are waveform diagrams of various parts for explaining the conventional system. In the figure, 1 is a commercial power supply input terminal, 2 is a DC power supply input terminal, 3 is an AC output terminal, 4, 5, and 5' are a semiconductor inverter and an inverter unit, 6 is a control circuit, T1,
T2 is a transformer, 7 is a filter circuit, 8 is a semiconductor switch, PLL is an integrated circuit, FD is a frequency divider, AMP is an amplifier, DT is a detector, PS is a phase shifter, D1 and D2 are reverse mirror teeth. In the wave generating circuit, CI and C2 are basic pulses, dl and d2 are comparison pulses, L1 and L2 are detection levels, COP is a comparison circuit, and FF1, FF2, FF3 and FF4 are flip-flop circuits. Figure 1, figure 2, figure O, figure 4, figure 5, figure 74, figure 6, figure 11, figure 8'g, figure 4, figure 70, figure 12, figure O, J, figure.

Claims (1)

[Claims] 1 includes a control circuit that superimposes the outputs of two inverter units, supplies the superimposed inverter output to a load via an LC filter circuit, and sends a control signal to each inverter unit.
A circuit that generates two sawtooth waves having a phase difference of 100 degrees and a frequency twice as high as the inverter output with a fast rising slope and a gentle falling slope, and the sawtooth waves and the output voltage detection level. a comparison circuit whose front end is controlled according to the output voltage detection level and generates a square wave voltage only during a period in which the rear end is synchronized with the rise of the sawtooth wave; and a comparison circuit that is inverted at the rise of the square wave voltage. An inverter control signal system comprising a flip-flop circuit and a flip-flop circuit that inverts when falling, and the conduction width of the inverter is controlled by applying the output of each of the flip-flop circuits as a control signal to the inverter. .