JPS6029414B2 - error correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction circuit for an information processing device using an error correction code.

The demand for higher performance for information processing equipment is increasing, and it has long been known that the use of error correction codes is an effective method to meet the demand for high reliability for these equipment. well known.

In conventional devices, errors in a given binary information code and its error correction code are corrected using a configuration in which a large number of logic integrated circuits are interconnected.

On the other hand, with the rapid development of integrated circuit technology in recent years, logic circuits used in error correction circuits can now be configured by interconnecting several large-scale integrated circuits, but conventional logic configurations are usually Since the configuration is designed to reduce the amount of hardware, there is a drawback that the delay time due to interconnection between these large-scale integrated circuits becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction circuit that reduces the error correction time of a logic circuit whose delay time due to interconnections cannot be ignored compared to the delay time within a logic block such as a large-scale integrated circuit. It is in.

The circuit of the present invention includes a first calculation means that performs an exclusive OR operation based on an information code and an error correction code corresponding to the information code, and an output means that outputs the exclusive OR result to the outside.
a second calculation means for generating a syndrome by performing an exclusive OR operation based on an exclusive OR result given from the outside and an exclusive OR result given from the first calculation means; A decoding means for decoding the syndrome from the decoding means and a correction means for correcting errors in the information code and the corresponding error correction code based on the decoding result from the decoding means are formed on the same substrate. shall be.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

An embodiment of the invention in the figure shows a first logic block 1
The first and second logic blocks 11' and the second logic blocks 11' are configured by interconnecting each other, but the internal logic configurations of the first and second logic blocks 11 and 11' are the same, and the respective circuits and terminals are 1 to 10. and 1' to 10', therefore, the first logical block 11 will be mainly explained below, and the second logical block 11' will also be explained if there are differences.

That is, in the embodiment of the present invention, an n-bit information code and a C-bit error correction code among the momme-bit information code and the real-bit error correction code are supplied from the input terminal 5, and the syndrome generation generated from the n-bit information code and C-bit error correction code are A syndrome generation code generation circuit 1 outputs a code for syndrome generation, a syndrome generation code output terminal 6 provided from the syndrome generation code generation circuit 1, and a syndrome generation code input terminal 7 for the syndrome generation code and syndrome generation code input terminal 7. a syndrome generating circuit 2 which inputs a code for inputting the information code and outputs a syndrome 9; and a syndrome decoding circuit which inputs the syndrome 9 and outputs an error position specifying code 10 which specifies the error position of the n-bit information code given from the input terminal 5. 3 and an error correction circuit 4 which inputs the n-bit information code and the error position designation code 10 given from the input terminal 5 and outputs the information code corresponding to the n-bit information code to the output terminal 8. A first logical block 11 configured and a first logical block.

Similar to the block, the remaining n-bit information code and C-bit error correction code are input to the input terminal 5', and the syndrome generation code is input to the input terminal 5'. A syndrome generation code generated from the n-bit information code and C-bit error correction code applied to the input terminal 5' is applied to the syndrome generation code input terminal 7'.
In addition, the syndrome generation code output terminals of the second logic block 11' and the first logic block 11 output an information code corresponding to the n-bit information code applied to the input terminal 5' to the output terminal 8'. 6 and the second logic block 11
', the syndrome generation code output terminal 6' of the second logic block 11', and the syndrome generation code input terminal 7 of the first logic block 11. and second connecting lines 12 and 12'. The operation of the embodiment of the present invention will be explained in detail with reference to the drawings.
Of the fox bit information code and the error correction code of these main bits, the n-bit information code and the C-bit error correction code are input to the input terminal 5 of the first logic block 11, and are connected to the remaining n-bit information code. When the C-bit error correction code is applied to the input terminal 5' of the second logic block 11', the respective syndrome generation code generation circuits 1 and 1'
, syndrome generation codes are generated from the codes applied to the respective input terminals 5 and 5', and these are applied to the syndrome generation circuits 2 and 2' in the block, and also to the syndrome generation code output terminal 6.
and 6' to the first and second connecting lines 12 and 12
', it is applied to the syndrome generation code input terminals 7 and 7' of other logic blocks, so it is also applied to the syndrome generation circuits 2 and 2' of different logic blocks, and the first and second logic blocks The syndromes 9 and 9' of the next bits generated in the syndrome generation circuits 2 and 2' are decoded by the syndrome decoding circuits 3 and 3' of the respective logic blocks, and errors are detected in the n-bit information code given to the blocks. If there is, the error position is designated by the error designation code 10 or 10', and the error correction circuit 4 or 4'
The bit information code is regenerated and output to output terminal 8 or 8'.

As is clear from the above description of the embodiments of the present invention, since the first and second logic blocks 11 and 11' have syndrome generation circuits 2 and 2' that generate all syndrome next bits, Although the number of logic circuits increases somewhat, compared to having C-bit syndrome generation circuits distributed in each logic block, the number of syndrome 9
and 9' need not be applied to other logic blocks, so there is no time delay due to interconnection between blocks.

In the present invention, in an error correction circuit consisting of a plurality of logic blocks into which information codes and error correction codes are distributed and input to each logic block, a part of the syndrome generation circuit is included in each logic block. This has the effect of reducing delay time due to block interconnection.

[Brief explanation of drawings]

The figure shows an embodiment of the invention. In the figure, 1, 1'... code generation circuit for syndrome generation, 2, 2'... syndrome generation circuit, 3, 3
'...Syndrome decoding circuit, 4,4'...Error correction circuit, 5,5'...Input terminal, 6,6'...Syndrome generation code output terminal, 7,7'For syndrome generation Sign input terminal, 8, 8'... Output terminal, 9, 9'...
・Syndrome, 10, 10'...error locating code, 11...first logic block, 11'...second logic block, 12...first connection line, 12'...th 2
connection line.

Claims (1)

[Claims] 1 Consists of multiple logical blocks with the same configuration,
Each logic block includes a first calculation means that performs an exclusive OR operation based on an information code and a corresponding error correction code, an output means that outputs this exclusive OR result to the outside, and all other logic blocks. a second calculation means for generating a syndrome by performing an exclusive OR operation based on the exclusive OR result given from the logic block and the exclusive OR result given from the first calculation means; A decoding means for decoding the syndrome from the arithmetic means and a correction means for correcting errors in the information code and the corresponding error correction code based on the decoding result from the decoding means are formed on the same substrate. An error correction circuit characterized by: