JPS6047614B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and more particularly, to a control data register setting mechanism in an information processing apparatus employing a microprogram control method.

In an information processing apparatus that employs a microprogram control method, there is a method of pre-reading a microprogram from a control memory as one means of improving processing performance.

FIGS. 1a and 1b are diagrams showing time charts of the conventional method. Here, Figure a is an example where the address to be executed next in the microprogram is determined in advance, and in the cycle where address n of the control memory is being executed, address n+1 of the control memory is read. . Therefore, in this case, the readout time is masked, resulting in an improvement in throughput. As shown in Figure 1, a conditional branch microinstruction is executed at address n of the control memory, the branch condition is met, and then
Consider the case of executing a street address. In this case, the contents of address n+1 of the control memory that were read during execution of address n of the control memory are invalidated by pre-reading, address m of the control memory is newly read, and address m is further executed in the next cycle. become. That is, in the case of a conditional branch microinstruction, if the branch condition is satisfied, the read-ahead effect disappears. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide an information processing apparatus using a microprogram control system in which processing performance does not decrease even when a branch condition of a conditional branch microinstruction is satisfied.

In other words, in the present invention, the signal under test is determined by the condition judgment circuit in the execution cycle of the conditional branch microinstruction as in the past, and when the branch condition is satisfied, the branch target microinstruction is read from the control memory in the next cycle and the control data is stored. In addition to storing it in a register, in the case of a specific conditional branch microinstruction, the contents of the microinstruction that have been read out in advance by the condition judgment instruction signal and the signal under test are changed in the execution cycle of the microinstruction, and this change is performed. This is characterized in that the microinstruction that has been executed is used as a branch destination microinstruction when a branch condition is satisfied.

As a result, when a branch condition is met, the cycle of reading the branch target microinstruction from the control memory and storing it in the control data register can be omitted, and the branch target operation can be executed immediately in the cycle following the conditional branch microinstruction execution cycle. becomes possible. FIG. 2 shows an embodiment of the invention.

In the figure, 1 is an address determining circuit that determines the read address of the control memory, 2 is an address register, 3 is a control memory that stores a microprogram, and 4 is a signal from the control memory 3, which is a feature of the present invention. 5 is a data register; 6 is a decoder for a test designation field in the data register; 7 is a condition determination circuit; and 8 is a controlled section of the processing device. It is now assumed that the conditional branch microinstructions of this processing device are divided into type A and type B.

Type A is similar to a conventional conditional branch microinstruction.
That is, the conditional branch microinstruction is specified by the test specification field of the data register 5, and is decoded by the test specification field decoder 6, but in the case of type A,
The judgment designation signal is subjected to a desired logic in the condition judgment circuit 7 with the signal to be tested given from the controlled section 8. When the branch condition is met, the address determining circuit 1 selects the branch address (address field of the data register 5), sets it in the address register 2, and controls! The control memory 3 is read, and the branch destination operation is executed in the cycle following this read cycle. On the other hand, type B is a conditional branch microinstruction that uses a circuit added in the present invention, and the judgment designation signal decoded by the test designation field decoder 6 closes the input gate from the control memory 3 in the switching circuit 4 and receives the The input gate for the signal under test from the control unit 8 is opened, and the value of the corresponding bit of the data register 5 is updated with the value of the data under test. In other words, the contents of the four data registers 5 obtained in this manner represent the control word when the branch condition is satisfied, and the branch destination operation is executed in the next cycle using this control word. Specifically, a case where a type B microinstruction stored in one area of the control memory 3 is being executed will be explained as an example.

When this type B microinstruction is executed, the contents of the control word read ahead from the control memory 3 are ゛゜10.
10, 101, 101, 0010゛ (from the left, 4 bits of the arithmetic control field, 3 bits of the flag control field, 3 bits of the test designation field, and 4 bits of the lower address fin L). If the branch condition in this execution cycle is not satisfied, the signal under test becomes non-signal, the switch circuit 4 does not operate, and the data register 5 stores the control word content of the next address read in this cycle. This will be executed in the next cycle. On the other hand, if the branch condition is satisfied, the contents of the data register 5 will become "1011, 101, 111, 001r" through the switching circuit 4, for example.
This indicates the contents of the control word at the branch destination, and is immediately executed in the next cycle. As is clear from the above description, according to the present invention, in an information processing device that employs a microprogram control method, an operation at a branch destination can be performed immediately in the cycle following the execution cycle of a conditional branch microinstruction. It is expected that the processing capacity will be improved.
Moreover, the hardware configuration required for this purpose is only adding a gate circuit to the input section of the data register, and the increase in the amount of hardware is small.

Note that in this type of information processing device, there are only a few conditional branch macro instructions that severely affect basic processing performance.
Therefore, it is sufficient to implement the present invention for a specific conditional branch microinstruction, and the hardware configuration does not become so complicated. Furthermore, since the control word for the branch destination is obtained by changing the previously read control word, there is no need to prepare the control word for the branch destination in the control memory, which has the effect of reducing the storage capacity of the control memory. There is also.

[Brief explanation of the drawing]

Figures 1a and 1b are time charts illustrating conventional pre-reading of a control memory in an information processing device that uses a microprogram control method. In the case of a microinstruction, the branch condition is satisfied and pre-reading is disabled. FIG. 2 is a block diagram showing one embodiment of the present invention. 1
...address determination circuit, 2...address register circuit,
3... Control memory, 4... Switching circuit, 5... Data register, 6... Test specification field decoder,
7... Condition determination circuit, 8... Controlled section.

Claims (1)

[Claims] 1 A control memory in which a microprogram is stored, and a data register in which a microinstruction read from the control memory is set, and the microinstruction is executed in parallel with the execution of the microinstruction set in the data register. In an information processing device that employs a microprogram control method in which a microinstruction to be executed next is prefetched from a control memory, a gate circuit is provided at the input section of the data register to pass a signal to be tested by a microinstruction, When executing, the test result by the microinstruction is given to the data register through the gate circuit to rewrite the contents of the microinstruction set in the data register, and the rewritten microinstruction is executed in the next cycle. Characteristic information processing device.