JPS6048077B2 - Memory refresh control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a refresh control method for dynamic memory.

In a conventional dynamic memory refresh control method, a dynamic memory refresh operation that requires a refresh operation is executed when a refresh cycle counter provided in the memory reaches a certain value, and at the same time all processing units Requests from are suppressed.

Therefore, when a memory control method is used in which the memory usage status is managed within the processing unit and a memory request is sent only when memory is free, as described above, the refresh operation temporarily causes the The disadvantage is that the memory busy management of the memory is disturbed and the effective utilization of memory cycles is impaired. In order to solve this drawback, the refresh cycle counter itself is incorporated into the central processing unit and the central processing unit itself generates the refresh operation timing, and when memory busy management including the refresh operation is performed, the central processing unit If the device itself stops operating due to a failure, refresh operations cannot be guaranteed, and there is a risk that the contents of the memory may also be destroyed. To avoid this, CP
If a refresh operation cycle counter is provided in both the central processing unit and the memory so that the memory itself can refresh itself only when U is down, a drawback arises in that the amount of hardware increases. An object of the present invention is to provide a memory refresh control method that can increase the utilization rate of memory cycles without increasing the amount of hardware, and can guarantee the stored contents of the memory even when the processing device is stopped. be.

The method of the present invention is a memory refresh control method that refreshes the contents of a main memory based on a request from a central processing unit, in which the main memory has a clock means for clocking a period of refresh operation, and a clock means for clocking a period of refresh operation. and display signal sending means for sending a refresh request display signal to the central processing unit when the value reaches a predetermined first value, and the central processing unit receives the display signal from the display signal sending means. and request signal sending means for sending a refresh request signal when there is no memory request signal from within the central processing unit and the storage device is in a busy state, and the refresh operation for the main storage device is performed by the request signal sending means. or a refresh request (signal) from the request signal sending means of the central processing unit when a second value indicating the limit value of the refresh operation is given from the time counting means. It is characterized in that it is performed regardless of the presence or absence of supply.

Next, one embodiment of the present invention will be described in detail with reference to the drawings. In the figure, reference number 1 indicates a central processing unit;
It has a busy management circuit 11, a request selection circuit 12, an AND gate 13, and a multiplexer 14.

Further, reference number 2 indicates a memory, which includes a cycle counter 21 for counting refresh cycles, a refresh address counter 22, comparison circuits 23 and 24, flip-flops 25 and 26, an OR gate 27, an AND gate 28, and a delay circuit 29. It has a multiplexer 30, a decoder 31, an ornate 32, and a memory element 33.
The cycle counter 21 is incremented by +1 every clock, and this output is sent to the comparators 23 and 24 as a signal 201.
are given to each. The value of the signal 201 is determined by the comparator 2.
When the signal 204 which is the output of the comparator 23 reaches the same value as the signal 203 which is the other input of the comparator 23, that is, (Xj), the signal 204 which is the output of the comparator 23 becomes a logical value ゛゛1゛ and sets the flip-flop 25. The positive output of this flip-flop is applied as signal 3 to the request selection circuit 12 of the central processing unit, which selects the output signal 1 of the busy management circuit.
01 and the normal memory request signal 103, when it is determined that the upstream refresh operation of the check can be accepted, the signal 104 is generated and the multiplexer 1
4 output as normal memory request code signal 107
The refresh request code 106 is switched to the refresh request code 106 and sent to the memory as a signal 6. Further, the output 102 from the request selection circuit is given to the busy management circuit 11 to update information regarding memory busy management within the central processing unit. When the request code from the central processing unit in the memory 2 is a refresh operation, the output 208 of the decoder 31 becomes logic "゜1", and the output signal 207 of the multiplexer 30 is changed to the normal request address by the signal 209 via the OR gate 32. A certain signal 5
is switched to the signal 206 which is the output of the refresh address counter 22 indicating the refresh address, and instructs the memory element 33 to refresh.
The refresh address counter 22 is incremented by +1.
Output 208 of decoder 208 also becomes signal 212 via OR gate 27 and resets flip-flop 25. The central processing unit 1 has lost memory 2 for some reason.
While the flip-flop 25 remains set because a refresh operation instruction cannot be sent to When this is reached, the output 205 of the comparator 24 becomes a logic 4°1, which becomes a signal 212 via the OR gate 27 to reset the flip-flop 25, and at the same time becomes a signal 210 via the AND gate 28, setting the flip-flop 26.

The output 4 of this flip-flop is given to the central processing unit, and the AND gate 13 suppresses all requests generated in the central processing unit, and it becomes the signal 209 via the OR gate 32, which refreshes the memory element 33 and refreshes the refresh address. Counter 22 +1
make progress. The flip-flop 26 is automatically reset by a signal 211 which is outputted after a certain clock has elapsed from the set signal 210 of the flip-flop 26 via the delay circuit 29. As mentioned above, after the value of the cycle counter 21 in the memory 2 reaches (Xi), the timing at which a refresh instruction is actually issued to the storage element 33 in the memory is from the central processing unit 1.
Although the central processing unit 1 reflects this timing in the busy management circuit 11, the busy management information is not disturbed in any way by indicating where to refresh. .

Furthermore, if the central processing unit 1 is unable to instruct the memory 2 to refresh for some reason, the memory 2 will be refreshed when the value of the cycle counter 21 reaches (Xj).
automatically performs a refresh operation. As is clear from the above, the present invention has the following advantages: By placing the refresh operation execution timing completely under the control of the central processing unit, effective use of memory cycles is always possible, and hardware duplication is avoided. This has the advantage that the contents of the memory can be retained even when the central processing unit is stopped.

[Brief explanation of the drawing]

The figure shows an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Memory, 11...Zeezy management circuit, 27, 32...OR gate, 12...
Request selection circuit, 13, 28...and gate,
29... Delay circuit, 14, 30... Multiplexer, 21... Cycle counter, 31... Decoder,
22・Refresh address counter, 23, 24...
・Comparator, 33...Storage element, 25, 26...Flip-flop, 5, 6, 106, 107, 206, 20
7,201-203...Data lines, 3,4,101-104,204,205,208-212...Control lines.

Claims (1)

[Claims] 1. In a memory refresh control method that refreshes the contents of a main storage device based on a request from a central processing unit, the main storage device includes a timer for timing a refresh operation cycle, and a predetermined first display signal sending means for sending a refresh request display signal to the central processing unit when the value of and a request signal sending means for sending a refresh request signal if there is no memory request signal from within the device and the storage device is in a busy state, and the refresh operation for the main storage device is performed by the request signal sending means. whether or not a refresh request signal is supplied from the request signal sending means of the central processing unit when the refresh operation is performed by a request signal or when a second value indicating the limit value of the refresh operation is given from the timer. A memory refresh control method characterized in that: