JPS6054694B2 - storage controller - Google Patents

Description

[Detailed description of the invention] object of invention The present invention relates to a storage control device for a computer.

Prior Art FIG. 1 shows a conventional storage control system. 1,
Reference numerals 2 and 3 denote access request stacking devices, which sequentially assign access requests stacked in the access request stack IA in the device to one of the access request priority determining devices 5, 6, 7, and 8 according to their address information. Send it to the crab.

The access request priority determining devices 5, 6, 7, and 8 are provided for each independently accessible storage unit (referred to as a port). The access request priority determination device selects one of the access requests received from each access request stack device and sends it to the corresponding port. Let us consider an access request sent from the access request stack device 1. It is assumed that this access request is sent to the access request priority determination device 5 by its address information. It is assumed that the above access request is selected by the priority determination logic 5A. The access request priority determination device 5
The access request is sent to the storage device, and at the same time, a signal 4 is sent to the access request stack device 1 indicating that the access request from the stack device has been selected. When the access request stack device 1 receives the signal 4, the control unit IB selects the next access request from the stack IA and sends it to the access request priority determining device. J In this way, in the conventional storage control method, one access request stack device sends out one access request, and when this access request is processed, it sends out the next access request, so it has the following three drawbacks. have

Gate (1) From one access request stack device, at the same time
Only one access request can be made.

(2) Only the access request stack device has a stack.
Since there is no stack, the stack will run out.

(3) When the number of access request stack devices increases in the future, the access request is read from the stack 1A, until the next access request is read from the stack 1A after receiving the signal 4 indicating that the access request has been processed. It is thought that the time required will be longer than the conventional one clock time due to the increase in the number of logic stages.

When this happens, in the conventional system, the interval at which access requests are sent to the storage device becomes two clock pitches from the conventional one clock pitch, resulting in a decrease in performance. OBJECTS OF THE INVENTION An object of the invention is to enable having more access requesting devices and stacking more access requests:
The object of the present invention is to provide a storage control device that can perform the following functions.

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a storage control device that independently receives access requests from a plurality of access request devices and generates access requests to a storage device composed of a plurality of independently accessible boats. It is characterized in that access requests from requesting devices are simultaneously set corresponding to each boat, and the order of the access requests is maintained while being sent to the storage device.

Embodiments of the invention and their effects FIG. 2 shows the main parts of a computer system, including an arithmetic unit 10
, a plurality of (here, four) access request control devices 20, 21, 22, 23 as access request devices.
, a storage control device 30, and a storage device 40, the storage device 4
0 consists of a plurality of (here, four) storage devices (the unit is called a boat) 400, 401, 402, and 403, each of which can be accessed independently.

Each boat further consists of a plurality of independently accessible storage devices (the unit is called a bank). The access request control device 20 is as shown in FIG. , data buffer 2
00 and an address generator 201, and a data buffer 2.
00, data read from the storage device 40 is sequentially stored and sent to the arithmetic device 10.

The access request control devices 21 and 22 have the same structure as the access request control device 20, and the access request control device 23 has the same structure as the access request control device 20.
The access request control device 20 has the same structure as the access request control device 20, except that data is stored in the storage device 40 from the data buffer. Vector data AO, al,...
... is read from the storage device 40 and the data buffer 20
Let's look at the operation of setting 0 in this order.

The address generation unit 201 sequentially generates atos information in which each piece of data is stored. FIG. 4 shows an outline of the storage control device 30.

Access request stack devices 300, 301, corresponding to the access request control devices 20, 21, 22, 23, respectively
302 and 303 are provided. Furthermore, access request priority determination devices 310, 311, 312,
313 is provided.

For example, the access request control device 20 sends an access request and address information to the access request stack device 300 at one clock pitch. Access request stack device 3
00 as an example, the access request stack device 300 stacks the received access requests in the order in which they are received.
Stored in A [7, In the order received, the address information is decoded and the corresponding access request priority determination device 310, 3
11, 312, or 313. Access request priority determination devices 310, 311,
312 and 313 are storage device ports 0 and 400, respectively.
Boat 1,401, Boat 2,402, Boat 3,40
Corresponds to 3. In other words, if the access request is
If there is one for the access request, it is sent to the access request priority determination device 310. Access request priority determination device 31
0 prioritizes the access requests sent from each access request stack device, selects any one access request, and transfers that access request to storage device boats 0 and 40.
Send to 0. At that time, a number (
The access request controller number) is set in the shift register circuit 310A. When an access is actually performed, data is read out after, for example, n clocks. The access request priority determination device 310 sequentially shifts the access request control device numbers set in the shift register circuit 310A, and after n clocks, simultaneously reads them into the data buffer of the access request control device indicated by the access request control device number. Set the data. This method prevents the order of access requests and read data from getting out of order. FIG. 5 shows an embodiment of the present invention in which access request control devices 20, 21, 22, and 23 access a storage device 40.

As an example, let us consider an access request sent from the access request control device 20.

The access request control device 20 sequentially sends access requests to the access request stack device 300. The access request stacking device 300 sequentially stacks access requests on the stack 300A. The stacked access requests are processed by the access request priority determining devices 310, 311, 312, 3 according to their address information in the stacked order.
13, latches 310B, 311B, 312B
, 313B. To be more specific, the bit pattern in the lower 5th and 4th bits of the address of the access request is 00. If so, the access request is distributed to the access request priority determination device 310,
ROlJ, rlOyo, RllJ are 311 and 3 respectively.
It will be divided into 12,313. Here, latch 310
C, 311C, 312C, 313C are the latches 310D, 311D, 31 from the access request stack device 301.
2D, 313D from 302, latches 310E, 311
Access requests are set for E, 312E, and 313E from 303. Access request priority determination device 31
0, latches 310B, 310C, 310D, 3
10E are access request control devices 20, 21, 2, respectively.
Corresponds to 2 and 23. Access priority determination device 311
, 312, 313 have similar relationships. what if,
When the access request priority determination device 310 is capable of accepting an access request from the access request stack device 300 and there is a valid stack request in the stack 300A, the access request set signal creation logic 300D of the access request stack device 300 generates the signal 50. Send out. The contents of the stack numbered by the out pointer 300B in the stack 300A are set in the latch 310B,
Out pointer 300B is incremented to point to the next stack. The access request priority determination device 310 includes 310B,
The priority order of the access requests set in 310C, 310D, and 310E is determined by logic 310K, and one of the access requests is selected and set in latch 310F. At this time, the access request selected by the priority determining logic 310K may not be set in the latch 310F depending on the contention state of the access requests and the bank free state. This suppression logic is access request permission logic 310M, which will be described in detail later. The access request set in latch 310F is sent to storage device 400 (boat 0).
Here, the bank free state display logic 310L of the storage device has information regarding the free state of banks, and sees which bank the access request is for, and the inhibition logic 310G, 310H,
3101 and 310J and is not entered into the priority determination logic 310K. If the access request set in latch 310F comes from latch 310B,
A signal 51 is sent to the access request stack device 300. A signal 51 indicates that the access request sent from the access request stack device 300 has been sent to the storage device 400. Other access request priority determination devices 311, 3
12 and 313 also perform similar operations, and latches 311F,
Access requests set in 312F and 313F are sent to storage devices 401, 402, and 403, respectively.
If the access requests set in the latches 311F, 312F, and 313F come from the access request stack device 300, signals 52, 53, and 54 are sent to the access request stack device 300, respectively. Also the fifth
In the figure, 300C is a latch that stores the number of access requests sent by the access request stack device to the access priority determination device.

300D is an access request set signal 50 that instructs to set an access request in the stack 300A to one of the latches 310B, 311B, 312B, and 313B.
, 55, 56, and 57.

Reference numeral 300E denotes an access request permission signal creation logic that creates an access request permission signal that allows the access request selected by the priority determination logic to be set in the latches 310F, 311F, 312F, and 313F.

The busy latch 300C, access request set signal creation logic 300D1, and access request permission signal creation logic 300E will be described in detail later. According to this, it has the following features and effects.

By providing the latches 310B to 313E, access requests can be set in a plurality of ports simultaneously from one access request stack device, unlike the conventional method.

By setting access requests to latches 310B to 313E, the access request stack device equivalently
It will have more stacks than the number of stacks in the device.

Temporarily, latches 310B, 311B, 312B, 313B
Considering that an access request is included in the access request stack device 300, the access request stack device 300 equivalently has the number of stacks in one stack 300A + 4 stacks.
The logic from latch 310B to latch 310F takes one clock time.

In the conventional method, the logic during this time was shorter than the above time, but since the computer system to which the present invention is applied has more access request control devices than the conventional method, the number of logic stages increases, which is an inevitable result. be. For these reasons, compared to the conventional method, this method has two advantages: it is possible to have more than one access request control device, and each access request control device can have more access request stacks. Excellent points.

However, as can be seen from FIG. 5, conventionally, for one access request stack device, after the access request sent from the access request stack device is sent to the storage device (that is, the signals 51, 52, 53, 54 (after receiving one of the following) the next access request. In this case, access requests can only be sent to the storage device at a two-clock pitch, resulting in lower performance than in the past. Therefore, the control described below is performed.

ζ will be explained using the access request stack device 300 as an example.

Access request stack device 300 has a 2-bit busy latch 300C. The busy latch 300C has a counter structure, and the access request set signal generation logic 300D
When any one of the access request set signals 50, 55, 56, and 57 is sent from the access request set signal 50, 55, 56, and 57, it is incremented by +1, and when any one of the access request sending signals 51, 52, 53, and 54 is received, it is made -1. This will cause the busy latch 300C
The access request issued from the access request stack device 300 is sent to the latches 310B, 311B, 312B,
313B. Access request set signals 50, 55, 56, and 57 are sent from access request set signal generation logic 300D when any of the following conditions is satisfied.

The access request sent last time will be called the previous access request, and the access request to which the out pointer is currently pointing (the access request to be sent from now on) will be called the current access request. (1) Busy latch 300C is 0.

(2) The r busy latch 300C is L and the current access request is an access request to a different boat from the previous access request.

:-(3) r busy latch 300C is 1J and 1 signal 5
Either 1, 52, 53, or 54 is 1J0 (4) 1 Busy sending 300C is 2 and 1 The current access request is an access request to a different boat from the previous access request and 0
If any of the signals 51, 52, 53, and 54 is 1, the access request set signal creation logic 300D realizes the above operation as follows.

FIG. 6 shows the structure of the access request set signal generation logic 300D. 3000 is a latch that stores the boat number of the access request sent from the stack 300A.

Therefore, the port number of the previous access request is set in latch 3000. 3001 is logic that decodes the boat number of the current access request in the stack 300A.

3002 is logic that decodes the value of the busy latch 300C.

A circuit 3003 compares the port number of the current access request in the stack 300A with the port number of the previous access request in the latch 3000. If the two differ, the signal 63 becomes 1.

When the values of busy latch 300C are 0, 1, and 2, signals 65, 68, and 69 become 1, respectively. Therefore signal 65
, 64, 66, and 67 satisfy the conditions (1) and (
2), (3), and (4), and the signal 70 becomes a signal instructing to send the access request to the access request priority determining device. The decoder 3001 decodes the boat number of the current access request, and if the signal 70 is 1, the access request set signals 50, 55, 5 of the corresponding boat
6,57 becomes 1. As a result, up to two access requests issued from the access request stack device 300 can exist simultaneously in the latches 310B, 311B, 312B, and 313B.

In principle, there can be up to four, but the control would be complicated, so we chose two.

However, access requests cannot be made consecutively to the same boat. Here, depending on the conflicting state of access requests issued from each access request stack device and the bank free status of the storage device, the order of two access requests issued from the same access request stack device may be swapped. It may be sent to storage.

In this computer system, the following control is performed so as not to change the order of access requests sent from one access request control device to a storage device. Otherwise, the third
The order of the data stored in the data buffer shown in the figure ends up being changed. Each access request stacking device issues a signal to the access request prioritization device that grants the access request selected by the prioritization logic. For example, the access request stacking device 300 sends signals 58,
59, 60, 61 are sent. The access request prioritization device that receives these signals performs the following operations. For example, regarding the access request priority determination device 310, the device 310 receives signals 58, 59, 60, 61.
receive.

For example, if the access request selected by the priority determining logic 310K is the one sent from the access request stacking device 300, then if the signal 58 is RL, the access request is set in the latch 310F, If so, set invalid data in 310F. Kotote signal 5
8, 59, 60, 61 are access request stack devices 30
Since the R2 access request sent from 0 is sent at the same time as being set in the access request priority determination device, the second access request is sent to the latches 310F and 31.
It is possible to prevent it from being set to 1F, 312F, and 313F. Access request permission signals 58, 59, 60, and 61 are created by the following three operations. Take the access request stack device 300 as an example. (1) r busy latch 300C is 2
When not, all signals 58, 59, 60, and 61 are set to r1.

(2) r busy latch 300C is 2J and 1 signal 51,
When any of 52, 53, 54 is RlJJ, signal 5
8, 59, 60, and 61 are all set to RlJ.

(3) Cases other than (1) and (2), that is, 1 busy latch 300C is 2. J and 0 signals 51, 52, 53, 54
If all of them are 0J, the access request permission signal to the destination boat of the last access request is set to ROJ.

The access request permission signal generation logic 310E realizes the above operation as follows. FIG. 7 shows the access request permission signal generation logic 310E.

The latch 3004 and decoder 3005 are the same as in FIG. What should be noted here is the latch 3004 and the latch 3
The same access request is set to 10B, 311B, 312B, and 313B at the same time. Therefore, it is possible to permit or prohibit the access request of the boat indicated by the value of this latch 3004 from being set to 310F, 311F, 312F, and 313F. 1 busy latch 300
When C is not 2, signal 79 is 0, so signal 5
8, 59, 60, and 61 all become RlJ and perform the above operation (1).

1 busy latch 300C is 2 and 1 signal 51, 52,
When either 53 or 54 is 11, signal 79 or 62
becomes 1, so signals 58, 59, 60, and 61 are all R
lJ and performs the above operation (2).

1 busy latch 300C is 2J and 1 signal 51, 52,
If 53 and 54 are all 0, then the latch 3000
Assuming that the boat number set in , that is, the destination boat number of the last access request issued, is 0, signal 71 becomes 1, signals 62 and 75 become 0, and signal 58 becomes 0. , since signals 72, 73, and 74 are 0, signals 59, 60, and 61 become 1, and the above operation (3
).

As a result, the access request sent from the access request stack device 300 is transferred to the latches 310B, 311B, 3
When two are set in 12B and 313B, the access request sent later is sent to the storage device after the access request sent earlier is sent to the storage device.

FIG. 8 is a best time chart in which access requests are issued only from the access request control device 20 in the order of ports 0, 1, and 2, and access requests are issued only to empty banks.

When the 1 busy latch 300C becomes 0 at timing TO, a signal 50 is sent, and at timing T1, the latch 310
Access request 1 is set in B, and the busy latch 300
C becomes 1.

Access request 1 set in latch 310B is prioritized. 1 busy latch 300C is at 1, so signal 58 is sent, and at timing T2, access request 1 after priority determination logic 310K is set in latch 310F.

At timing T1, 1 busy latch 300C is at 1, so signal 55 is sent, and at timing T2, access request 2 is set to latch 311B, and busy latch 2 is set at timing T2.
become. Access request 2 set in latch 311B
are given priority. 1 busy latch 300C is 2J
Since the 1 signal 51 is RlJ, the signal 59 is sent out, and the access request 2 after the priority determination logic is set in the latch 311F at timing T3.

Also, at timing T2, 1 busy latch is 2 and 1 is busy.
Upon receiving the signal 51, the signal 56 is sent out, and at timing T3, the access request 3 is set in the latch 312B, and the busy latch 300C is set to 2 (the value remains unchanged since the signal 51 and the signal 56 exist at the same time). At timing T3, access request 3 set in latch 312B is prioritized. Ru. At this time,. Since the busy latch 300C is 2 and the 0 signal 52 is r1, the signal 60 is sent, and the access request 3 after the priority determining logic 310K is set in the latch 312F at timing T4. As can be seen from Fig. 6, in this method, 1 ku.
Access requests can be issued to the storage device at lock pitch. Although FIG. 8 shows a case where there is an access request only from the access request control device 20, FIG. 9 shows a case where there is an access request from other access request control devices as well.

FIG. 9 shows an access request sent from the access request control device 20. It is assumed that access requests are sent from the access request control device 20 in the order of ports 0, 1, and 2. When the 7 busy latch 300C is set to 0J at timing TO, a signal 50 is sent out, and access request 1 is set in the latch 310B at timing T1.

Since 1 busy latch 300C is 1J at timing T1, signal 58 is 11J, signal 55 is sent, access request 2 is set in latch 311B, access request 1 enters priority determining logic 310K, and at timing T2 Bifugi Latch 300C becomes 2. Here, access 1 is not selected by the priority determination logic 310K,
Assume that an access request from another access request stack device is selected. Therefore, access 1 is not set in latch 310F. At timing T2L, 1 busy latch is 2J and 1 signals 51 to 54 are 0J, so signal 59 for boat 1 where access request 2 is set is 0.
There is. Furthermore, the signal 58 for access request 1 issued earlier is r1. Therefore, in the access request priority determination device 311, even if access request 2 is selected by the priority determination logic, the latch 311F is closed at timing T3.
Access request 2 is not set. timing T2
Then, 1 busy latch 300C is 2 and signals 51 to 54 are 0.
Therefore, signal 56 does not appear. Also, busy latch 300
C remains unchanged at timing T3. If access request 1 is selected by priority determining logic 310K at timing T2, access request 1 is set in latch 310F at timing T3, and signal 51 becomes 1. At timing T3, 1 busy latch 300C is 2J and 0 signal 5
Since 1 is 1J, the signal 59 becomes 1, and if access request priority determination device 311 selects access request 2 by the priority determination logic, latch 311 is activated at timing T4.
Access request 2 is set in F, and signal 52 becomes 1. At timing T3, 1 busy latch 300C becomes 2. J
Since the 1 signal 51 is at L, the signal 56 becomes 1 and access request 3 is set in the latch 312B. As can be seen from FIG. 9, access request 2 is sent to the storage device after access request 1 is sent to the storage device. If the earlier issued access request is not prioritized and remains in the access request priority determination device, the later issued access request may overtake the earlier issued access request. controlled so that there is no In this case, access requests cannot be issued to the same boat at one clock pitch, but this case is rare. According to this embodiment, access requests can be set in a plurality of boats at the same time, and the access requests sent from one access request control device can be controlled without changing the order.

Effects of the Invention According to the present invention, it is possible to have more access request control devices than in the conventional system, so access requests from more devices can be accepted.

In addition, the access request priority determining device is also equipped with a latch for setting access requests, so that one access request control device can issue multiple access requests at the same time, which equivalently increases the stack and increases the number of access requests. Stack functionality will be enhanced. Furthermore, the number of logic stages in the priority determination logic is increased compared to the conventional method, and this logic alone takes one clock time, whereas the conventional control method requires two clocks.
Access requests that would otherwise be sent to the storage device at a clock pitch can be controlled to maintain the conventional performance of one clock pitch.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing the main parts of a computer system to which the present invention is applied, and FIG. 3 is a block diagram showing a specific example of the access request control device shown in FIG. , FIG. 4 is a block diagram showing a specific example of the storage control device shown in FIG. 2, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is a block diagram showing an example of the access request set signal generation logic shown in FIG. FIG. 7 is a block diagram showing a specific example of the access request permission signal creation logic of FIG. 5, and FIGS. 8 and 9 are time charts illustrating the present invention. 10...Arithmetic device, 20-23...Access request control device, 30...Storage control device,
40...Storage device, 300-303...
・Access request stack device, 300A...Stack, 300B...Out pointer, 300
C: Busy latch, 300D: Access request set signal creation logic, 300E:
Access request permission signal creation logic, 310 to 313...
...Access request priority determination device, 310B to 31
0E: Latch, 300K: Priority determination logic, 310M: Access request permission logic.

Claims (1)

[Claims] 1. In a storage control device that independently receives access requests from a plurality of access request devices and generates access requests by prioritizing the access requests to a storage device composed of a plurality of independently accessible storage units, stacking means for stacking access requests from the access requesting devices in correspondence with the access requesting devices; latching means for setting access requests from each of the stacking means in correspondence to the storage units; means for prioritizing the set access requests and sending the access requests to the corresponding storage unit; means for storing the number of access requests set in the latch means corresponding to the access requesting device; Storage control comprising means for sending access requests from the stack means to the latch means according to the contents of the means, and controlling sending access requests from the same access request device to the storage device in order. Device.