JPS6057595B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention multiplies a time-division multiplexed signal indicating the pressed state of a plurality of keys and a waveform signal generated in a time-divisional manner corresponding to this time-division multiplexed signal. This invention relates to an electronic musical instrument that can simultaneously produce musical tones, and is equipped with an opening/closing control circuit that can prevent the occurrence of click noise caused by key ink in musical tone signals that correspond to key operations such as key presses and key releases. Regarding electronic musical instruments.

This applicant previously provided an electronic musical instrument of the invention described in the specification of Japanese Patent Application No. 52-150895 (Japanese Unexamined Patent Publication No. 54-834M) entitled "Electronic Musical Instrument."

The present invention includes a plurality of key switches, a key switch scanning circuit that sequentially scans these key switches at a predetermined speed and outputs a time division multiplexed signal indicating the pressed state of each key, and comprising a time-division waveform generation circuit that time-divisionally generates a waveform signal corresponding to the key, and a multiplier that multiplies the output signal (waveform signal) of the time-division waveform generation circuit by the time-division multiplexed signal, This electronic musical instrument is characterized in that a musical tone signal is obtained from the output signal of this multiplier. Another invention presented in the same specification includes a plurality of key switches and a key switch scanning circuit that sequentially scans these key switches at a predetermined speed and outputs a time division multiplexed signal indicating the key depression state of each key. a time-division waveform generation circuit that time-divisionally generates a waveform signal corresponding to each pitch in synchronization with the key switch scanning; and a delay that outputs the time-division multiplexed signal after a predetermined delay. a coupler control circuit having a circuit, and a multiplier that multiplies the output signal (waveform signal) of the time-division waveform generation circuit by the time-division multiplexed signal TDM and the output signal of the coupler control circuit, the multiplier This electronic musical instrument is characterized in that a musical tone signal is obtained from the output signal of the electronic musical instrument, and both of the above-mentioned inventions have an excellent feature of being able to simultaneously produce a large number of musical tones with a simple configuration. By the way, in the former invention mentioned above, the waveform signal outputted in a time-divisional manner and the time-division multiplexed signal are directly input to the multiplier, and in the latter invention, the waveform signal outputted in a time-divisional manner, A signal corresponding to the time-division multiplexed signal (that is, a signal obtained by outputting the time-division multiplexed signal via the power supply control circuit) is directly input to the multiplier.

However, in this case, the amplitude value of the waveform signal input to the multiplier is not always near its "0" level.In other words, the waveform signal output from the time-division waveform generation circuit is One waveform (one period) is divided into multiple sample points, and the waveform amplitude values at each divided sample point are sequentially output one by one for each scanning period of the key switch (i.e., output in a time-division manner). ), and assuming that the waveform signal is a sine waveform, this sine waveform is 0
It changes from the highest level (maximum amplitude value) on the positive side to the highest level (maximum amplitude value) on the negative side with the level as a reference. Furthermore, since the key is pressed at an arbitrary time, the amplitude value of the waveform signal first output when the key starts scanning is not always around the ``0'' level.
Therefore, if the time division multiplexed signal is input to the multiplier when the amplitude value of the waveform signal is near the highest level, the output of the multiplier (that is, the multiplication value of the waveform signal and the time division multiplexed signal) will be ゛0゛. There may be a sudden rise from the highest level to the highest level (when the key is pressed), or a sudden drop from the highest level to the ``゜0゛ level (when the key is released), which may cause an unpleasant lick noise. It occurs and is musically undesirable.

The present invention has been made in consideration of the above circumstances, and its purpose is to provide an electronic musical instrument that can reliably prevent the occurrence of the above-mentioned lick noise when a key is pressed or released. That's true.

Therefore, in the present invention, when the absolute value of the amplitude value of the waveform signal is less than or equal to a predetermined value (that is, when the amplitude value is near the "0" level) is detected, and based on this detection, the time division multiplexed signal is It is designed to be sent to a multiplier.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, the electronic musical instrument of the present invention is roughly divided into a key switch circuit 1 having a large number of key switches arranged in a matrix and provided for each key on a keyboard (not shown); - a key switch scanning circuit 2 that sequentially scans each key switch of the key switch circuit 1 and outputs a time division multiplexed signal TDM representing the open/closed state of each key switch, that is, the key pressed state; A timing signal generation circuit 3 generates a timing signal for controlling the operation of a time-division waveform generation circuit 4, which will be described later, and a waveform signal (sound source signal) having a period corresponding to each pitch in synchronization with the scanning of the key switch circuit 1. or a time-division waveform generation circuit 4 that generates a musical tone signal S) in a time-division manner, and a time-division multiplexed signal T.
A coupler control circuit 30j inputs DM, delays this time division multiplexed signal TDM for a predetermined period of time, further performs predetermined processing on this delayed signal DTDM, and then outputs the waveform signal S and the coupler control circuit 30j. Output signal TDM,
An opening/closing control circuit 6 receives and stores the output signals TDM and DTDM of the coupler control circuit 30 only when DTDM is input and the amplitude value of the waveform signal S is near the "0" level.
0, a multiplier 5 that multiplies the signal stored in this opening/closing control circuit 60 and the waveform signal S, and the output signal of this multiplier 5 is input, and at the start of one scan of the key switch circuit 1. an accumulator 6 for cumulatively adding up the output signals within a certain scanning period from the time to the end of scanning; a latch circuit 7 to which the contents of the accumulator 6 are input and latched at the end of each scanning period; and this latch circuit 7. A DIS9 converter 8 that converts the output signal (digital signal) of the D8 converter 8 into an analog signal, and an amplifier 9 that amplifies the output signal of the D8 converter 8.
and a speaker 10 that produces musical tones from the output signal of the amplifier 9. Next, the configuration of each part mentioned above will be explained in detail with reference to FIGS. 2 to 6.

As we all know, one octave has 12 notes: C, C#, D,
..., B, but in this example, the 12 keys of the first octave (these keys are Cl, C#, Dl, ...
, B1), 12 keys of the second octave C2
, C valve, D2, . omitted)
It shall be placed on top.

The 61 key switches corresponding to these 61 keys are arranged in a matrix in the key switch circuit 1 as shown in FIG. That is, the column lines 11 to 16 of the key switch circuit 1 correspond to the first to sixth octaves, respectively, and the row lines L1 to Ll2 correspond to each note name C, C#, . . .
・,B is supported. For example, a key switch for the first octave key E1 is disposed on the intersection of the column line 11 and the row line L5. In addition, column line 11 in the figure
16 and row lines L1 to 142 indicate that the above-described key switch is connected in series with a forward diode between the corresponding column line and row line. Here, the configuration of the timing signal generation circuit 3 will be explained.

This circuit 3 consists of a 4-bit hexadecimal counter 1 driven by a clock pulse φ that is constantly output at a predetermined period.
5 (Contents of this counter 15 “0000” to “1101”
”, w-adic display “0” to “11J and below are expressed in w-adic; correspond to each pitch name C-B respectively),
The most significant bit (4th bit) of this hexadecimal counter 15
A 4-bit decimal counter 16 is driven by the bit output signal N4 (the content of this counter 16 is ``000'').
” to “101”, w-adic representation “0” to “6”: hereinafter expressed in decimal notation; corresponds to the first to sixth octaves, respectively), and the first octave of the decimal counter 15.
, 2, 4-bit output signals Nl, N2, N4 and the first and 4-bit output signals Bl, B4 of the w-adic counter 16 are directly input, and the third-bit output signal N3 of the hexadecimal counter 15 and the decimal counter 16 are directly inputted. 16 second and third bit output signals B2 and B3 respectively correspond to the inverter 6.
5, 66, and 67, and an AND gate 17.

The output signal of this AND gate 17 is called a signal SYC, and one scanning period, which will be described later, is defined by this signal SYC. 1st to 4th bit output signal N of hexadecimal counter 15
1 to N4 are input to the decoder 12 in the key switch scanning circuit 2. That is, the signals N1 to N4 representing the contents of the counter 15 are decoded by the decoder 12 and output as a ゜"1゛ signal to any one of the output terminals 01 to 012 provided in the decoder 12. For example, 12 The contents of the decimal counter 15 correspond to the pitch name G 7 (
In the case of W-ary number display), the “゜1゛” signal is output only from the output terminal 08 of the decoder 12.
~4th bit output signal 8~B is input to another decoder 11 in the key switch scanning circuit 2. That is,
Signals B1 to B4 representing the contents of the counter 16 are decoded by the decoder 11, and the output signal is outputted to any one of the column lines 11 to 15 of the key switch circuit 1 as a "6r" signal. For example, when the content of the counter 16 is content 2 representing the third octave (W-adic representation), the ゜゜1゛ signal is output only to the column line 13, and each key C3, C#, C# of the third octave is output.
. . , B3 are configured to be scanned during this period.
The output signal of the row line Ll2 of the key switch circuit 1 is sent to the corresponding AND gate 131 in the key switch scanning circuit 2.
1312, respectively. The output signals from the output terminals 01 to 012 of the decoder 12 are input to the second input terminals of the AND gates 131 to 1312, respectively. Also, each AND gate 131-131
The output signal of 2 is inputted to the above-mentioned coupler control circuit 30 via an OR gate 14 as a time division multiplexed signal TDM. Since the timing signal generation circuit 3 and the key switch scanning circuit 2 are configured as described above, both counters 15 and 1
6 forms a 12 pheasant counter, and the output signals of this 12 pheasant counter N1 to N,, Bl to B4 (contents 0 to 119
) defines one scanning period (FIG. 5) of the key switch circuit 1 consisting of 61 key switches.

That is, FIG. 5 shows the contents of the one acceleration counter (each bit time) within one scanning period consisting of 120 bit times.
The correspondence between 0 to 119 and the type of key to be scanned is shown. Since the number of keys used in this invention is 61, 12
During the period in which the contents of the 0-base counter are 61 to 119, key switch scanning is not actually executed. The decoder 12 to which the bit output signals N1 to N4 of the hexadecimal counter 15 are input,
As mentioned above, when the content of the hexadecimal counter 15 is between 0 and 11, the ゜゜1゛ signal is sequentially outputted to its output terminals 01 through 012.

Therefore, when the content of the hexadecimal counter 15 is, for example, 0, the AND gate 131 is open, and at this time, the keys Cl, C2, .
...If the key C6 is pressed, a key press signal is output from the AND gate 131, and this signal is further sent to the OR gate 14.
is output as a time division multiplexed signal TDM. When one scanning period is started in this manner, the pressed states of the 61 keys Cl, C#, ..., BS, C6 are determined by the 12-digit counter consisting of the hexadecimal counter 15 and the w-base counter 16.
When the contents of the hexadecimal counter change sequentially from 0 to 119,
The keys are scanned sequentially starting from the first octave key. Further, the AND gate 17 outputs the signal SYC only at the end of one scanning period, that is, only when the contents of the 1 (to) counters 15 and 16 are 119. This signal SYC is input to an accumulator 6 and a latch circuit 7, which will be described later. Further, the first to fourth bit output signals N1 to N of the first-stream counter 15 in the timing signal generation circuit 3 and the first to fourth bit output signals 2 to 8 of the W-ary counter 16 are both generated by the time-division waveform generation circuit. The frequency number memo I in 4 is input as an address designation signal.

As a result, the frequency number memo I river 8 is addressed in synchronization with the scanning of each key switch in the key switch circuit 1, and from this frequency number memory 18, a numerical value proportional to the frequency corresponding to the pitch of the key being scanned at that time is generated. (hereinafter referred to as frequency number) R is output, and this frequency number R (1
(data represented by 7 bits) is input to the first input terminal A of the adder 19.

Note that keys C# to Cl are not actually provided in this frequency number memory 18. A frequency number memory R corresponding to (for 48 keys) is also stored. That is, the time division multiplexed signal TDM output from the key switch scanning circuit 2
is input to the shift registers 31 to 38 (48 stages in total) in the coupler control circuit 30 and is delayed as described later, so the delayed signal DTDM is also given a corresponding frequency number R and handled accordingly. This is because it is necessary to generate a waveform signal S that The second input terminal B of the adder 19 receives output data (20 bits) from a shift register 20, which will be described later.
9 adds the frequency number R<5 - the output of the shift register 20, and the added value is input to the shift register 20 as 20-bit parallel data. shift register 20
has 120 stages and a capacity of 20 bits per stage, and is driven by a clock pulse φ to sequentially shift the added value outputted from the adder 19. That is, the adder 19 and the shift register 20 independently and sequentially repeatedly add the frequency numbers R corresponding to each pitch. Among the output data (120th stage output) sequentially output from the shift register 20 in a time-division manner, the upper 8 bits of data are input to the sign table 21 as an address signal. This 8-bit data has contents corresponding to the pitches of keys C1 to C6 being scanned at that time, as well as contents corresponding to the pitches of keys C# to ClO mentioned above, and according to this data, 12-bit data S representing a sine amplitude value is sequentially outputted from the sine table 21 in a time-division manner and sent to the multiplier 5 and the switching control circuit 6.
It is input to 0. The coupler control circuit 30 includes eight shift registers 31 to 38 connected in series, and nine weighting circuits each connected to the output side of the key switch scanning circuit 2 and the output side of each shift register 31 to 38. 39～
47 and the output signals k1 of these weighting circuits 39 to 47
. . . K9.

Shift registers 31, 32, 33, 34, 35, 36,
37 and 38 each have a capacity of 12 stages and 1 bit, 7
Stage●1 bit, 5 stage●1 bit, 7 stage●1 bit, 5 stage/1 bit, 4 stage●1
bit, 3 stages●1 bit, 5 stages●time division multiplexed signal T that has 1 bit and is driven by clock pulse φ and is input to the first shift register 31
The DMs are sequentially shifted to the subsequent shift registers 32 to 38. Therefore, the time division multiplexed signal TT)M input to the first stage of the shift register 31 at a certain bit time is outputted from the 12th stage of this shift register 31 after 12 bit times and is input to the first stage of the shift register 32 at the next stage. The signal DTDM (signal TDM delayed by 12 bit time) inputted to one stage and further inputted to this shift register 32 is output from the seventh stage after 7 bit time and is inputted to the shift register 33 of the next stage. Input to stage 1.

In this way, the signal TT)M is inputted to the coupler control circuit 30 and then processed by each shift register 31 to 38 for a predetermined period of time, that is, 12 bit time, 7 bit time, 5 bit time, 7 bit time, 5 bit time, The signals are outputted from each shift register 31 to 38 after being delayed by 4 bit times, 3 bit times, and 5 bit times. Here, the input terminal of the shift register 31 is a point A, and each output terminal of the shift registers 31 to 38 is B, C, D, E, F, G, H.
, and name it I point. 16 feet to point A (hereinafter referred to as
A weighting circuit 39 corresponding to 16" is connected to point B.
A weighting circuit 40 corresponding to the above is connected. Similarly, weighting circuits 41, 42, and 43 corresponding to points C, D, E, F, G, H, and I correspond to 55, 4'', 2, 7, 1, 15, and 1, respectively. , 44, 45, 46, and 47. Each of the weighting circuits 39 to 47 includes a slide type changeover switch 49, an encoder 50, and three AND gates 51, 52, and 53, and has the same configuration. In FIG. 2, only the configuration of the 16'' weighting circuit 39 is shown in detail, and the configurations of the other circuits 40 to 47 are omitted. In the weighting circuits 39, 40 to 47, the "゜1" signal is supplied to the common contact of the changeover switch 49, and the signals output from the eight changeover contacts 0 to 7 are input to the encoder 50. Yes.Encoder 50
outputs the signal corresponding to the position of each switching contact of the changeover switch 49 as 3-bit data, and outputs the signal corresponding to the position of each switching contact of the changeover switch 49,
It is configured to be input to each of the first input terminals 52 and 53, respectively. Further, the second input terminals of the AND gates 51, 52, and 53 are both connected to point A (point B to point I), and each output signal of the AND gates 51, 52, and 53 is 3-bit data Kl, k2 to K9. It is input to the adder 48 as . As a result, when the changeover contact of the changeover switch 49 is set to "5", for example, the encoder 50 outputs the 3-bit data "101J1" representing the numerical value "5" to the first input terminals of the AND gates 51 and 53. The ``1'' signal and the ``0'' signal are output to the first input terminal of the AND gate 51. As a result, only the AND gates 51 and 53 are opened, so if the time division multiplexed signal TDM input to the point A at this time is a "1" signal, the adder 48 receives the numerical value "5" from the weighting circuit 39. Data representing "10U" will be input. Drawers (knobs) for driving each changeover switch 49 provided in each weighting circuit 39 to 47 are arranged as shown in FIG. It is provided near the keyboard of the musical instrument (for example, on the panel surface above the keyboard).

Drawpers 541-549 are arranged corresponding to weighting circuits 39-47 in order from the left side in FIG. When each drawper 541 to 54 is slid in the vertical direction of the figure, numbers 1 to 8 appear at the visual position, and the number shown at the top position of each drawper 541 to 549 is determined by the drawper 541 to 56. It is designed to represent the changeover contact of the changeover switch 49 to be driven. In FIG. 6, for example, the changeover switch 49 of the 16'' weighting circuit 39 is set to the changeover contact "2". In this way, by appropriately operating the positions of the respective drawpers 541 to 549, the player can freely set the weighting of each foot. Further, the signal DTDM delayed and outputted from each shift register 31-38 is further weighted with a numerical value corresponding to the setting position of each drawper 541-549, and data k is output from weighting circuits 39-47 of each foot.
1 to K, and sent to the adder 48. The adder 48 adds these data k1 to K9 and outputs the added value as 6-bit data K to the multiplier 5 via the opening/closing control circuit 60. Next, the configuration of the opening/closing control circuit 60, which is the main part of the present invention, will be explained with reference to FIGS. 3 and 4.

The opening/closing control circuit 60 includes a level detection signal generation circuit 70 to which data representing the sine amplitude value S corresponding to the pitch of each key C1 to C6 and C# to ClO outputted from the sine table 21 is input; A gate circuit group 79 that allows the output data K of the adder 48 to pass only when the level detection signal D is output from the signal generation circuit 70, and a memory circuit (shift register) that receives and temporarily stores the output data K. Preparation from 80. FIG. 4 shows a specific example of the configuration of the level detection signal generation circuit 70 when the output data (sine amplitude value) S of the sine table 21 is expressed by sign/absolute value. In sign/absolute value display, the absolute value display portions of the same amplitude value on the plus side and minus side are exactly the same with respect to the reference level (“゜0゛ level, e.g. 0 volts) of the above output data (sine amplitude value) S. The positive side of the amplitude is the binary logic level ゜゜0.
- A sign of "1" is given to the minus side, and these are attached to the most significant bit (MSB) of the data S. Since the sine amplitude value S is represented by 12 bits of data in this example,
Its most significant bit MSB (1 based on the least significant bit)
The second bit) is the sign bit. Furthermore, since this level detection signal generation circuit 70 is a circuit that detects the vicinity of the reference level of the sine amplitude value S, the 11th, 10th, and 9th bits of the sine amplitude value S are Data is input to the NOR gate 71 (FIG. 4). Therefore, when the data of the 11th, 10th, and 9th bits are ゜゜0゛, that is, when the sine amplitude value S is a value near the reference level, the level detection signal D is output from the NOR gate 71.
The signal D is input to the first input terminal of each AND gate 731, 732, . . . , 737 (FIG. 3). Further, the level detection signal D is inverted by the inverter 72 and the AND gates 741, 742,
..., 74, is input to the first input terminal.

Each bit of the 6-bit data K output from the adder 48 (FIG. 2) is input to the second input terminal of each AND gate 731 to 737 in a corresponding manner. Further, at the second input terminal of each AND gate 741 to 747, each bit Rl, r2, . . , R6 are respectively input. The outputs of these AND gates 731 and 741 are sent to a shift register 80 via an OR gate 75.
is input to the corresponding bit of the first stage. Similarly, AND gates 732, 742, 733, and 743 (
(not shown), each output of 737 and 747 is connected to a corresponding OR gate 752, 753 (not shown),
757 to the corresponding bits of the first stage of the shift register 80. Also shift register 8
The output data of 0 is also input to the multiplier 5. With the above configuration, the signature table 21
When the sine amplitude value S of the key that is time-divisionally output from is not data near the reference level (“0 level”),
Since either the 11th, 1st or 9th bit of the data representing the sine amplitude value S is in the state of the ゜゜1゛ signal, the level detection signal D output from the NOR gate 71 (Fig. 4) is "0".
゛It is a signal. Therefore, the output of the inverter 72 becomes the ゜゜1゛ signal, and the AND gates 741 to 74 become operational, and the AND gates 731 to 7
3, is in an inactive state. On the other hand, as the key is pressed, the key switch scanning circuit 2 outputs the signal TDM, and the adder 48 starts outputting the added data K. However, the AND gate 7 does not function until the level detection signal D reaches "1" for the first time after the start of the key press operation.
31 to 73 are in an inactive state, the addition data K output during this period is not input to the shift register 80. Also, the contents of all stages of the shift register 80 (
Since the content held in the shift register 80 is ゜゜0゛ during this period, the input to the multiplier 5 is also ``0゛.Therefore, the level detection signal D is ゜゜ from the beginning of the key press operation. No musical tones are produced until it reaches 1゛.
Next, when the level detection signal D reaches "1" for the first time,
AND gates 731 to 737 become operable, and AND gates 741 to 747 become inoperative.
Therefore, from this point on, the addition data K begins to be sequentially input to the shift register 80, and the data input to the first stage of the shift register 80 is sequentially shifted to the subsequent stage. Then, when the addition data K input to the first stage of the shift register 80 is output from the 120th stage of the shift register 80, this addition data K is sent to the multiplier 5, and musical tones begin to be produced. That is, after the key press operation starts, the sine amplitude value S reaches the reference level (
The musical tone is not produced until the level reaches around "0" level, thereby preventing the generation of click noise.

Next, when the level detection signal changes from ゜゜1゛ to ``゜0゛'' while the key is being pressed, AND gates 731 to 737 become inactive, and AND gates 741 to 747 become active.As a result, until then the shift register Regarding the first bit r1 of the data K stored in $0, during this period, the AND gate 741 → OR gate 751 → 1 bit of each stage of the shift register 80 → AND gate 74
1 is formed. Similarly, for the second to sixth bits R2 to R6 of the above data, the AND gate 74. ~747 OR gates 752 to 757, 2nd to 6th bits of each stage of shift register 80, AND gate 74. A circulation circuit consisting of .about.747 is formed.
The shift register 80 is driven by the above-mentioned clock pulse φ, and sequentially shifts and circulates the data r1 to R6 backwards and stores and holds the data, and this held data K is sent to the multiplier 5 and generated. Of course, and gate 7
31 to 73 are in an inactive state, new addition data K is not input to the shift register 80. Then, when the level detection signal D becomes "1" again during this key depression, each AND gate 741-74 becomes inoperative, the above-described circulation circuit is released, and its memory is released (cleared). On the other hand, when the level detection signal D becomes the 6"R3 signal, each AND gate 731 to 737 becomes operable. Therefore, the new output data K of the adder 48 is simultaneously sucked into the shift register 80. This is sent to the multiplier 5. In this way, while the key is being pressed, the addition data K previously taken into the shift register 80 is stored and held by the circulation circuit during the period when the level detection signal D is 660''. At the same time, musical tones are generated based on the held data K. When the level detection signal D reaches ゜1゛, the added data K that has been cyclically held is cleared and new added data K is taken into the shift register 80.
With this new addition data K, musical tones continue to be produced while the key is being pressed. While the key is being pressed, the level detection signal D is 640+661990a099. ．． ．． ．． ．． ．． ．． ．． The above operation is repeated as the value changes. Even if the key is then released and the signal TDMC゜l゛) is no longer output, the sound continues to be generated based on the data K stored in the shift register 80 until the level detection signal D reaches ゜゜1゛. When the level detection signal D becomes ゜゛1゛ for the first time after the key is released, the signal TDM is ゜゛0゛ at this time, so the data K input to the shift register 80 becomes ゛゛0゛.
Therefore, the contents of the shift register 80 begin to be cleared, the contents of each stage become ゜゜0゛, and no sound is produced. In this way, even when the key is released, the sound continues until the level detection signal D reaches ゛1゛ after the key is released, thereby preventing the generation of unpleasant lick noise. adder 4
The output data K of 8 is multiplied by the sine amplitude value S near the reference level that is simultaneously output from the sine table 21, and the multiplied value (12-bit data) is sent to the adder 23 in the accumulator 6 (see Fig. 2). ) is input to the first input terminal A of the terminal A.

The output data of the 1-stage, 15-bit register 24 is input to the second input terminal B of the adder 23 via the gate circuit 22. The adder 23 adds the two-person force data,
The added value is input to the register 24 as 15-bit parallel data. This register 24 is driven by the aforementioned clock pulse φ, and outputs the read data to the gate circuit 22 and latch circuit 7 as 15-bit parallel data. The gate circuit 22 generates a signal obtained by inverting the signal SYC by an inverter 25 so that it is always open except at the end of one scanning period, that is, when the signal SYC is output. C
is input as a control signal. Furthermore, the latch circuit 7 is provided with a signal SYC as a data read signal.
Therefore, the adder 23 in the accumulator 6 is 1
From the start of the scanning period (when the content of the 1-addition counter is 0), the multiplication value output from the multiplier 5 starts to be cumulatively added, and when the content of the 12-addition counters 15 and 16 reaches 119, the adder 23 Perform the final addition. Then, when the content of the 1-acceleration counter reaches 119, the signal SYC is output, so that the latch circuit 7 latches the last accumulated value of the adder 23 (this accumulated value is stored in the shift register 24). The latched data is as explained in Figure 1.
Further, the signal is sent to a DA converter 8, an amplifier 9, and a speaker 10. Next, the operation of the electronic musical instrument configured as described above will be explained with reference to the operation waveform diagram shown in FIG.

It is now assumed that keys Cl, D2, and G## are pressed simultaneously within one scanning period. It is also assumed that each of the drawers 541 to 549 of the coupler control circuit 30 is set to the state shown in FIG. By the operation of the hexadecimal counter 15 and the pheasant counter 16 of the timing signal generation circuit 3, the operation for one scanning period starts when the content of the decimal counter constituted by these two counters 15 and 16 is 0. be done.

When the content of the pheasant counter 12 is between 0 and 11 (that is, the content of the w-adic counter 16 is O), the output signal 66r' of the decoder 11 of the key switch scanning circuit 2 is output only to the column line 11 of the key switch circuit 1. and each key C of the first octave
Key switches 1 to B1 are scanned.

During this time, the decoder 12 detects that the content of the hexadecimal counter 15 is 0.
As the value changes from 1 to 11, "1" signals are sequentially output from output terminals 01 to 012, and the corresponding AND gates 131 to 1312 are sequentially opened.In parallel with the above operation, the 120 counter is Output signal N1 to N4, Bl
~B4 sequentially specifies the addresses corresponding to each key C1~B1 in the frequency nanometer 18 of the time-division waveform generation circuit 4, and as a result, frequency numbers R corresponding to the pitches of the keys C1~ are sequentially output and added. The signal is input to the device 19.

The adder 19 repeats the operation of adding the output data of the shift register 20 and the frequency number R and outputting the added value to the shift register 20. Also, the upper 8 bits of the output data of the shift register 20 are stored in the sign table 2.
1, the sine amplitude values S corresponding to the keys C1 to C2 are sequentially and time-divisionally output from the sine table 21 during this period, and the multiplier 5 and the level detection signal generation circuit 7
It is input to 0. In this example, since the key C1 is pressed, the key C1 pressed at the start of this one scanning period
is detected first. Therefore, the output signal of the AND gate 131 of the key switch scanning circuit 2 becomes ゜゛1゛. Therefore, the time division multiplexed signal 'n)M becomes "r" when the content of the 112-can counter is O (the 7A).This signal T
DMc4r is input to the shift register 31, and AND gates 51 to 5 in the 16'' weighting circuit 39
3 to enable these AND gates 51 to 53 to operate. Since each switch 49 of the 16" weighting circuit 39 is set to contact 2 (see FIG. 6), data k1 "010" representing the numerical value 2 is output from the AND gates 51 to 53, and the data k1 "010" representing the numerical value 2 is outputted to the adder 48. Sent.
Shift registers 31 to 38 before this one scanning period starts
Assuming that the contents of are all O, the output signals of each of the shift registers 31 to 38 (that is, the output signal of point B-1) are all zero when the contents of the l (a)-adic counter are O. Therefore, the output data K of the adder 48 is 1 at this time.
Setting value 2 of the drawper 541 of the weighting circuit 39 of 6″
It is "010" which is equal to . The above signal TDMC゜l゛) due to the key C1 input to the shift register 31 is 12
After the bit time (when the content of the 1 (A) base counter is 12), it is output to point B and input to the shift register 32 (FIG. 7.B).

This signal is sequentially shifted to the subsequent shift registers 33 to 38 and output to point C-1 (Fig. 7 C-1).
1), the contents of the 12 can counters at that time are 1
9, 2 lines 31, 40s to 3, 43, 48 (see Figure 7). Similarly, the keys D2 and G# are detected when the contents of the 1 (A) counter are 14 and 56, respectively, and the time division multiplexed signal TDM becomes a "1" signal at this time.This signal TDMClr) is detected by the shift register. 31 to 38 are sequentially shifted. Therefore, signals as shown in FIG. 7 are sequentially output to each point A-1 within one scanning period. Then, a signal 66r3 is output to each point A to ■. Each time, the setting value of the changeover switch 49 (drawer 541 to 54,) in the corresponding weighting circuit 39 to 47 is output to the adder 48. Data k1~ output from circuits 39~47
K, and outputs the added data K to the opening/closing control circuit 60. On the other hand, the sine table 21 outputs the sine amplitude values S corresponding to the keys Q, D2, and G# within this one scanning period (hereinafter also referred to as the first scanning period), and the multiplier 5 opens and closes. It is sent to the level detection signal generation circuit 70 in the control circuit 60.

Then, the level detection signal generation circuit 70 detects whether the sine amplitude value S input at that time is near the reference level. Now, suppose that the sine amplitude value S for the key C1 output from the sine table 21 at the start of the first scanning period has a value near the reference level.
The sine amplitude values S for all other keys including the tsuba P2 and G# similarly have values near the reference level. In the case of the key C1, since the sine amplitude value S is close to the reference level, the level detection signal DC゜l゛ signal) is generated from the NOR gate 71 (Fig. 4), and the AND gates 731 to 737 operate. becomes possible, and the AND gates 741 to 747 become inoperable. Therefore, at the start of the above-mentioned one scanning period (when the content of the 12-bit counter is 0), each bit of the output data K1 of the adder 48, that is, the 6-bit data "000010" (binary representation) representing the numerical value 2. is the first of the shift register 80 through the corresponding AND gates 73, ~737, OR gates 751~75,
input to the stage. This data “000010”K
are then sequentially shifted within the shift register 80. Then, after 12 bit times, the time division multiplexed signal TDM for the key C1 is output from the shift register 31 of the coupler control circuit 30 (see FIG. 7B), so that the time division multiplexed signal TDM for the key C1 is set by the drawper 542 from the 8'' weighting circuit 40. Data K2=“5” (W-ary representation) is output and sent to the adder 48. As can be seen from FIG. 7, there is no data Kl, k, ~K9 that is simultaneously input to the adder 48 at this bit time (when the content of the 1 nod counter is 12), so the adder 48 at this time is The output data K is data “5”, that is, “00010U (binary representation), and this data “00010U” is sent to the opening/closing control circuit 60. Also, at this bit time (content 12 of the 120-decimal counter), the sign table 21 outputs the sine amplitude value S corresponding to the key C2 and inputs it to the level detection signal generation circuit 70, but the sine amplitude value S corresponding to the key C2 at this time is also a value near the reference level. Therefore, the level detection signal D for this key C2 is a "1" signal. Therefore, the above data "00010" is input to the first stage of the shift register 80 via the AND gates 731 to 737 and the OR gates 751 to 75.The data "000010" previously input to the shift register 80
K has now been shifted to the 13th stage of the shift register 80. Therefore, when the content of the 12-can counter is 12, the data K1 and k2 obtained by pressing the key C1 are stored in the first and thirteenth stages of the shift register 80. 12 (when the content of the 4 counter reaches 14, as shown in FIG. 7, the time division multiplexed signal TT corresponding to the collar P2) MC゜l゛ signal) is output, and the coupler control circuit 3
Sent to 0.

Furthermore, the level detection signal D of the "1" signal is also output for the sine amplitude value S corresponding to the key D2.Thereby, the data input to the adder 48 is transmitted to the weighting circuit 39 of 16".
The output data k1=“2” (displayed in W base).
This data "2", ie, "000010" (in binary notation), is input to the first stage of the shift register 80 in the same manner as described above. The two data “000010” and “00010U” previously input to the shift register 80
At this time, they have been shifted to the 15th stage and the 3rd stage, respectively. Moreover, at each bit time shown in FIG. The signal is input and then shifted within the shift register 80. It is obvious that each piece of data in the shift register 80 is shifted simultaneously at intervals corresponding to the input bit times. At the end of the first scanning period, the contents of the 12th counter return to O, and the next scanning period (hereinafter also referred to as the second scanning period) begins, the key is transferred from the 120th stage of the shift register 80. C
The data "000010" corresponding to 1 is output and sent to the multiplier 5.

At this time, the multiplier 5 has been sent the sine amplitude value S near the reference level corresponding to the speed, so the multiplier 5 multiplies the human force data and sends the multiplied value to the accumulator 6.
It is sent to the input terminal A of the adder 23 inside.

Since the input data at the input terminal B of the adder 23 is "0" (W-adic representation), the added value of the adder 23 at this time is the above-mentioned data "000010" plus the sine amplitude value S (Fll
ICl), and this data is stored in the adder 23-register 2 until the next data is input to the input A of the adder 23 (after 12 bit times in this example).
It is maintained by a circular circuit consisting of 4-gate circuit 22→adder 23. From the 120th stage of the shift register 80, each of the above-mentioned data is transferred to the shift register 80.
are sequentially output while maintaining the time interval input to the multiplier 5.
Each time, the multiplier 5 multiplies each data by the corresponding sine amplitude value S output from the sine table 21 (this sine amplitude value S has a value near the reference level, of course). , and sends the multiplied value to the input terminal A of the adder 23. The adder 23 adds the newly inputted multiplication value to the data previously held by the circulation circuit, and similarly stores and holds the added value in the circulation circuit.
In this way, the content of the 1 acceleration counter becomes 118, and the content of the shift register 24 immediately before the end of the second scanning period is the signal n output to each point A-1 after the start of the first scanning period. ) M, DTDMC "1") multiplied by the set value by the drawers 541 to 549 of the corresponding weighting circuits 39 to 47, and each value is further multiplied by the corresponding sine amplitude value S. This total amount is determined at the end of the second scanning period, that is, when the signal SY
When C is output, it is latched by the latch circuit 7, and further sent to the speaker 10, where a plurality of tones are produced simultaneously. The musical tones produced at this time did not contain any unpleasant lick noise since the sine amplitude value S for each key was around the reference level.On the other hand, each of the keys Q, D
2. When the G## key is pressed, that is, at the beginning of the first scanning period described above, if each sine amplitude value S output from the sine table 21 is not a value near the reference level, the level detection signal D described above is is the 60° signal.

Therefore, the output of the inverter 72 becomes the "゜1゛ signal, and the AND gates 741 to 74 become operable, and the AND gates 731 to 73 become inoperative. On the other hand, after the key is pressed, the When one scanning period starts, the seventh
The time division multiplexed signal TDM (“゜1゛ signal) corresponding to keys Cl, D2, G# in the order seen in the figure, this signal TDM
As described above, the signal DTl)MC"1") delayed from Execute the addition operation.When the level detection signal is “
Immediately before changing to the ゜1゛ signal, the added data K for each bit time of the adder 48 is not input to the shift register 80 because the level detection signal D is a ``0'' signal as described above. In other words, during the period after the start of the first scanning period until the level detection signal D becomes a "1" signal, the inputs to each bit of the first stage of the shift register 80 are all "0". Of course, the output of the shift register 80 (bits r1 to R6) is 6"0" until the level detection signal D becomes a "1" signal, so the sine amplitude value S input to the multiplier 5 during this period is It becomes invalid and no musical tone is produced.Next, for example, in the second scanning period, the level detection signal D changes from the ゜“0゛ signal to the ゜゛1゛ signal.
The AND gates 741 to 747 close and the circulation circuit is released, and the AND gate 73
When 1 to 737 are opened, the output data K of the adder 48 at that time is input to the first stage of the shift register 80, and the subsequent operation is exactly the same as that described above.
In this way, even if the sine amplitude value S output from the sine table 21 when a key is pressed is not near the reference level, according to the present invention, the sine amplitude value S is multiplied until it becomes a value near the reference level. Multiplying operations in the unit 5 are prohibited, so that calculation operations for creating musical tones that would generate unpleasant or lick noises are not performed.

Further, the prohibition time of this calculation operation is extremely short, and does not cause any trouble to the human auditory response. After musical tones begin to be produced by the above-mentioned key press operation, the sine amplitude values S corresponding to the keys Cl, D2, and G# that are pressed at the same time deviate from the value near the reference level, and a level detection signal is generated. When D becomes '40゛3, AND gate 731~
737 becomes inactive, and AND gates 741~
74, becomes operational.

For this reason, input of the addition data K output from the adder 48 to the shift register 80 is prohibited, and at the same time, the circulation circuit begins to operate.
The addition data K that has been input to is cyclically held. This cyclically held state is held until the level detection signal D becomes the “゜1゛” signal, for example, until the fifth scanning period, but this addition data K held during this period is also sent to the multiplier 5. , the multiplier 5 receives this added data K
is multiplied by the sine amplitude value S output from the sine table 21, and the musical tones are continuously produced. Next, the fifth scanning period is reached, and the level detection signal D changes from "0" to "1".
When this occurs, the AND gates 741 to 747 become inactive, and therefore the circulation circuit becomes inactive and the contents of the shift register 80 begin to be cleared, but at the same time, the AND gates 731 to 73 open and the data from the adder 48 is Since the addition data K begins to be input to the shift register 80, each stage of the shift register 80 is in a state where the addition data K is continuously stored even when the level detection signal D changes from ゜゜0゛ to ゜“1゛. Therefore, from now on, musical tones continue to be produced according to the operation described above.When the level detection signal D is "゜0゛", all keys Cl, D2
, G valves are released, musical tones continue to be produced by the addition data K stored in the shift register 80 while the circulation circuit is in operation, as described above. When the level detection signal D becomes ``1'' after the key is released, the circulation circuit closes and the shift register 80 begins to be cleared, and at the same time, the addition data K is input to the shift register 80.
The added data K at this time becomes "0" after the key is released (because after the key is released, the signals TDM, DTD
M is ゜゜0゛), shift register 8
Each stage of 0 is cleared after the level signal D reaches "1" after the key is released, and as a result, no sound is produced.In this way, even when the key is released, the level detection signal D remains "1".
Since the sound continues until the key reaches 1, no unpleasant lick noise occurs when the key is released. next,
The output data (sine amplitude value) S of the sine table 21 is 2
An example of the configuration of the level detection signal generation circuit 70 in the case of complementary representation will be explained with reference to FIG.

In the case of two's complement representation, the negative value of the sine amplitude value S is represented by the two's complement of the corresponding positive value.

The amplitude value on the plus side is the same as the amplitude value on the plus side based on the sign/absolute value display described above. Further, a sign bit is also attached to the most significant bit (MSB) of the data S in the same way as the sign/absolute value display. In FIG. 8, this level detection signal generation circuit 7' is composed of an exclusive OR gate group 90 to which the sine amplitude value S is input, a half adder 92 to which the output signal of this exclusive OR gate group 90 is input, and the output data of the half adder 92. It consists of a NOR gate 93 which receives the output signal of the upper three bits and outputs a level detection signal D. The exclusive OR gate group 90 includes 11 exclusive OR gates 911 provided corresponding to 11 bits excluding the sign bit out of the sine amplitude value S represented by 12 bits.
~9111. The sign bit is commonly input to the second input terminal of each of these exclusive OR gates 911 to 9111, and is also input to the half adder 92 as a carry input signal. With the above configuration, the sine amplitude value S expressed in two's complement is output from each bit of the half adder 92 via the exclusive OR gate group 90 as the sine amplitude value S expressed in sign/absolute value. ) Similarly, a level detection signal D is created. Other examples of the level detection signal generation circuit of the above embodiment include a case where the sine amplitude value S is displayed by minus 10 g or an analog signal; Explanation will be omitted.

Further, the number of keys is not limited to that of the above embodiment, but can be any number. Furthermore, in place of the above sign table,
A waveform memory that stores a desired musical sound waveform can be used.
Further, other configurations can be modified in various ways without departing from the spirit of the invention. As explained above, the present invention sequentially scans a plurality of key switches at a predetermined speed to generate a time-division multiplexed signal indicating the pressed state of each key, and also generates a time-division multiplexed signal indicating the key-pressing state of each key. In an electronic musical instrument that generates a corresponding waveform signal in a time-divisional manner and obtains a musical tone signal by multiplying this waveform signal and the above-mentioned time-division multiplexed signal, the absolute value of the amplitude value of the above-mentioned waveform signal is less than or equal to a predetermined value. For example, since the musical tone signal processing is started when the value is around the "゜0゛ level," when the absolute value of the amplitude value of the waveform signal is around the highest level, the musical tone signal can be formed. Therefore, there is an advantage that the occurrence of click noise when a key is pressed or released can be completely prevented.

Furthermore, in the case of electronic musical instruments equipped with a coupler control circuit, the timing of the rise (occurrence) and fall (extinction) of each partial tone obtained from the weighting circuit of each foot in the coupler control circuit is different, so the multi-stage key switch It also has the advantage of producing a pleasant attack effect similar to that found in Hammond organs.

[Brief explanation of the drawing]

1 to 7 show an embodiment of the electronic musical instrument of the present invention, FIG. 1 is a block diagram showing the overall configuration of the electronic musical instrument, and FIGS. 2 and 3 show main parts of the same example. Detailed circuit diagram: FIG. 4 is a detailed circuit diagram of the level detection signal generation circuit of the same example; FIG. 5 is a diagram showing the correspondence between one scanning period and each key of the same example;
7 is a diagram showing the general steady state of the drawper of the same example, FIG. 7 is an operation waveform diagram of the same example, and FIG. 8 is a diagram showing a modification of the level detection signal generating circuit. DESCRIPTION OF SYMBOLS 1... Key switch circuit, 2... Key switch scanning circuit, 3... Timing signal generation circuit, 4... Time division waveform generation circuit, 5...・・・・・・
Multiplier, 6... Accumulator, 7...
...Latch circuit, 11, 12...Decoder, 15, 16
... Counter, 18 ... Frequency number memory, 21 ... Sign table, 30 ...
Coupler control circuit, 31-38...Delay circuit (shift register), 39-47...Weighting circuit, 54...Drawer, 60...Opening/closing control circuit , 70, 7 '... Lebel detection signal generation circuit, 80... Memory circuit (shift register).

Claims (1)

[Claims] 1 A plurality of key switches are sequentially scanned at a predetermined speed to generate a time-division multiplexed signal indicating the pressed state of each key, and a waveform signal corresponding to each pitch is time-division multiplexed in synchronization with the key switch scanning. In an electronic musical instrument in which a musical tone signal is obtained by multiplying this waveform signal and the above-mentioned time division multiplexed signal, a level detection signal is generated when the absolute value of the amplitude value of the above-mentioned waveform signal is less than a predetermined value. It comprises a level detection signal generation circuit, and a storage circuit that inputs and stores a signal corresponding to the time division multiplexed signal when the level detection signal is generated, and stores the output signal of the storage circuit and the waveform signal. An electronic musical instrument characterized in that musical tone signals are obtained by multiplication.