JPS605959B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention obtains a large number of delayed signals by delaying a time division multiplexed signal indicating the pressed state of a plurality of keys by a predetermined period of time, and also obtains a waveform signal corresponding to the time division multiplexed signal and the delayed signal. Regarding an electronic musical instrument that generates a waveform signal in a time-divisional manner and multiplies this waveform signal with the above-mentioned time-division multiplexed signal and delayed signal to simultaneously produce a large number of musical tones, the present invention particularly corresponds to the drawbar setting state. The present invention relates to an electronic musical instrument that enables effective volume control.

This applicant previously provided an electronic musical instrument of the invention described in the specification of Tokkoshi No. 52-150895 entitled "Electronic Musical Sound."

To summarize, the present invention includes a plurality of key switches, a key switch scanning circuit that sequentially scans these key switches at a predetermined speed and outputs a time-division multiplexed signal indicating the pressed state of each key, and a time-division waveform generation circuit that generates waveforms corresponding to each key in a time-division manner; a coupler control circuit having a delay circuit that can delay the time-division multiplexed signal by a predetermined time and output the time-division multiplexed signal; The electronic musical instrument is characterized in that it includes a multiplier that multiplies the output signal of the waveform generation circuit and the output signal of the coupler control circuit, and that a musical tone signal is obtained from the output signal of the multiplier. Furthermore, the coupler control circuits of this electronic musical instrument each have a predetermined delay time, and are connected in series to each other, and are configured to sequentially delay the time division multiplexed signal by a predetermined time and output the delay time. The present invention is characterized in that it includes a plurality of circuits and a weighting circuit that weights and outputs each of the time division multiplexed signal and the output signal of the delay circuit. The weighting circuit described above is also connected to the drawbar, and the weighting circuit is connected to the drawbar. A signal is output that is given an arbitrary weight depending on the set position of the server. This electronic musical instrument has the excellent feature of being able to simultaneously produce a large number of musical tones due to the simple configuration described above. By the way, as mentioned above, each delay circuit of the coupler control circuit is provided with one drawbar, and each drawbar is provided with a plurality of (eight, for example) switching contacts, so that the volume can be switched in eight levels. It is made possible to do so.

Therefore, the difference in volume obtained depending on the number of drawbars inserted and the setting state (switching position state) of each drawbar becomes very large. For example, there will be a huge difference in volume between setting all the drawbar switching positions to the maximum position and setting one drawbar switching position to the minimum position and the other drawbar switching positions to zero. . Therefore, when changing the switching position of each drawbar to change the tone color, the volume adjustment knob must be operated to correct the volume at the same time. This invention was made in consideration of the above circumstances, and its purpose is to provide an electronic device that can obtain musical tones of optimal volume in accordance with the setting state of the drawbars connected to the coupler control circuit. The purpose is to provide musical instruments.

To achieve this object, the present invention includes a plurality of key switches and key switch scanning means for sequentially scanning each of these key switches at a predetermined speed to generate a time-division multiplexed signal indicating the pressed state of each key. , a delay means for delaying and outputting the time division multiplexed signal by a predetermined time, and weighting the output signals of the time division multiplexed signal and the delay means according to setting values set by respective operations of corresponding operators. a weighted signal generating means for outputting a weighted signal as a weighted signal; a waveform generating means for time-divisionally generating a waveform signal corresponding to each pitch in synchronization with the scanning of the key switch; and a control means for obtaining a musical tone signal by weighting the control means, and a calculation means for calculating a total value of the set values of each of the operators, and a calculation means for calculating the total value based on the total value. Means for suppressing and controlling the volume level of the above-mentioned musical tone signal as it becomes louder is provided.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, the electronic musical instrument of the present invention is roughly divided into a key switch circuit 1 having a large number of key switches arranged in a matrix and provided for each key on a keyboard (not shown); A key switch scanning circuit 2 that sequentially scans each key switch of the key switch circuit 1 and outputs a time division multiplexed signal TDM representing the open/closed state of each key switch, that is, the key pressed state; A timing signal generation circuit 3 generates a timing signal for controlling the operation of the time-division waveform generation circuit 4, etc., and a logarithm of the period corresponding to the pitch of each key is displayed in synchronization with the scanning of the key switch circuit 1. A time-division waveform generation circuit 4 generates a waveform signal (sound source signal or musical tone signal) in a time-division manner with logarithm (a≧・, S>0), and a time-division multiplexed signal TDM is inputted to generate the time-division multiplexed signal TDM. is delayed by a predetermined time by a plurality of delay circuits, and the time division multiplexed signal TDM and its delayed signal DTDM are input to the corresponding weighting circuits to obtain a weighted signal k. ,k2,
. . . and operator setting value data K,, K2, . . . related to the set position of each drawbar.
The above weighted signal k・, k2, --- output from 0
The sound volume control circuit 5 receives the above waveform signal 10 ga and controls the volume of the above waveform signal 10 according to the setting state of the drawbar connected to the coupler control circuit 30; The output signal of the control circuit 5 is input,
An accumulator 6 that cumulatively adds the output signals of the key switch circuit 1 within one scanning period from the start of one scan to the end of one scan, and a latch that receives and latches the contents of the accumulator 6 at the end of each scanning period. A circuit 7, a DA converter 8 that converts the output signal (digital signal) of the latch circuit 7 into an analog signal, an amplifier 9 that amplifies the output signal of the DA converter 8, and produces the output of the amplifier 9 as a musical tone. It is composed of a speaker 10 that allows Next, the configuration of each of the above-mentioned parts will be explained in detail with reference to FIGS. 2 to 5.

As we all know, one octave has 12 notes: C, C#, D,
.
, ..., B,), 12 of the second octave
keys C2, C#2, D2,...Kawa, B, 12 keys for each of the 3rd to 5th octaves following the same notation,
It is assumed that a total of 61 keys, including one key C6 of the sixth octave, are provided on the keyboard (the path shown in the figure).

The 61 key switches corresponding to these 61 keys are arranged in a matrix in the key switch circuit 1 as shown. That is, column lines 1 to 16 of the key switch circuit 1 correspond to the first to sixth octaves, respectively,
Also, the row lines L to L, 2 are each pitch name C, C#,...
・,B is supported. For example, on the intersection of column line 1 and row line -, key switch 0 of key E of the first octave is arranged. In addition, column line 1 in the figure
The circles placed on the intersections of ~16 and row lines L, ~L, and 2 indicate that the above-described key switch is connected in series with a forward diode between the corresponding column line and row line. Here, the configuration of the timing signal generation circuit 3 will be explained. Is this circuit 3 a clock pulse that is constantly output at a predetermined period? A 4-bit hexadecimal counter 15 driven by (the contents of this counter 15 is 0 "0000" to
1101'', 1-bore Hayabusa number display ``0'' to ``11'' (hereinafter expressed in IG Hayabusa number display; corresponds to each note name C to B, respectively), and the most significant bit of this decimal counter 15 A 4-bit decimal counter 16 (this counter 16
Contents “0000” to “0101”, IG Hayabusa number “0”
~ "6": hereinafter expressed as the number of 1G ships; corresponds to the 1st to 6th octaves, respectively), and the 1st, 2nd, and 4th bit output signals N, , N2 of the hexadecimal counter 15.
, N4 and the first and fourth bit output signals B,, B4 of the decimal counter 16 are directly input, and the third bit output signal N3 of the decimal counter 15 and the second and third bit output signals of the IG Hayabusa counter 6 are input directly. , and an AND gate 17 to which B3 is input via corresponding inverters 65, 66, and 67, respectively.

The output signal of this AND gate 17 is called a signal SYC, and one scanning period, which will be described later, is defined by this signal SYC. 1st to 4th bit output signal N of hexadecimal counter 15
, ~N4 are input to the decoder 2 in the key switch scanning circuit 2.

That is, the signals N, to N4 representing the contents of the counter 15
is decoded by the decoder 12, and the I
The signal is output as a "1" signal to any one of the Z output terminals ○, to ○, and 2. For example, if the content of the hexadecimal counter 15 is content 7 (IG Hayabusa number display) corresponding to the pitch name G, “1
"The signal is output. The first to fourth signals of the IQ Hayabusa counter 16
The bit output signals B to B4 are input to another decoder 11 within the key switch scanning circuit 2. That is, signals B, ~B4 representing the contents of the counter 16 are sent to the decoder 1.
1, and its output signal is output as a "1" signal to any one of the column lines 1 to 15 of the key switch circuit 1. For example, when the content of the counter 6 is content 2 representing the third octave (1-boad number display), a "1" signal is output only to the column line 13, and each key C3, C#3,・・・・・・
. . , & are configured to be scanned during this period. The output signals of the row lines L, .about.L,2 of the key switch circuit 1 are transmitted to the corresponding AND gates 13, .about.L, 2 in the key switch scanning circuit 2.
13 and 2 are respectively input to the first input terminals. The output signals ◯, ◯, and 2 of the output devices of the decoder 2 are input to the second input terminals of the AND gates 13 and 138, respectively. Further, the output signals of each AND gate 13, - 13, 2 are passed through an OR gate 14 to a time division multiplexed signal TD.
The above-mentioned coupler control circuit 3 is inputted as M. Since the timing signal generation circuit 3 and the key switch scanning circuit 2 are configured as described above, a 12-board Hayabusa counter is formed by both counters 15 and 16, and the output signals of this 12G ship counter N, ~N4, B, ~ & (representing content 0 to 119) defines one scanning period (FIG. 4) of the key switch circuit 1 consisting of 61 key switches.

That is, FIG. 4 shows the contents of the 120-decimal counter (each bit time) within one scanning period consisting of 120 bit times.
The correspondence between 0 to 119 and the type of key to be scanned is shown. Since the number of keys used in this invention is 61, 12
Key switch scanning is not actually executed during the period when the contents of the five-ship counter are 61 to 119. The decoder 12 to which the bit output signals N, ~N4 of the hexadecimal counter 15 is inputted is,
As described above, when the contents of the hexadecimal counter 15 are 0 to 11, "1" signals are sequentially output to the output terminals ○, ○, 2.

For this reason, when the content of the hexadecimal counter 5 is, for example, 0, the corresponding AND gate 13, is opened, and at this time, the keys C, , , corresponding to the note name C of any octave are
If keys C2, . . When one scanning period starts in this way,
The pressed states of the 61 keys C,,C#,...,B5,C6 are shown by the hexadecimal counter 15 and the IG Hayabusa counter 1.
When the contents of the 12G ship counter consisting of 6 sequentially change from 0 to 119, the keys are sequentially scanned starting from the first octave key. Also, from the AND gate 17, at the end of one scanning period,
That is, the signal SYC is output only when the content of the 12G ship counter is 119. This signal SYC is input to an accumulator 6 and a latch circuit 7, which will be described later. Furthermore, the first to fourth bit output signals N, ~N4 of the hexadecimal counter 15 in the timing signal generation circuit 3 and the first to fourth bit output signals B~& of the IG Hayabusa counter 16 are both generated by the time division waveform generation circuit. The frequency number memory 18 in 4 is input as an address designation signal.

As a result, the frequency number memory 18 is addressed in synchronization with the scanning of each key switch of the key switch circuit 1, and from this frequency number memory 18, a numerical value proportional to the frequency corresponding to the pitch of the key currently being scanned ( Hereinafter referred to as frequency number) R is output, and this frequency number R (1
(data represented by 7 bits) is input to the first input terminal A of the adder 19.

Note that keys C#6 to C, which are not actually provided in this frequency number memory 18. A frequency number R corresponding to (4 senden) is also stored. In other words, the time division multiplexed signal TDM output from the key switch scanning circuit 2 is input to and delayed by the shift registers 31 to 38 (48 stages in total) in the coupler control circuit 30, as will be described later. This is because it is necessary to give a corresponding frequency number R to the time division multiplexed signal DTDM to generate a corresponding waveform signal. Adder 1 above
The output data (20 bits) of the shift register 20, which will be described later, is input to the second input terminal B of the shift register 9. Therefore, the adder 19 adds the frequency number R and the output of the shift register 20, and obtains the added value. is input to the shift register 201 as 20-bit parallel data. The shift register 20 has 120 stages and a capacity of 20 bits per stage, and is driven by a clock pulse to sequentially shift the added value output from the adder 19. In other words, the adder 19 and the shift register 2 This means that the frequency numbers R corresponding to the pitches are independently and repeatedly added in sequence.The data of the upper 8 bits of the output data (120th stage output) sequentially output from the shift register 20 in a time-division manner is input to the signature table 21 as an address signal.This 8-bit data has content corresponding to the pitch of the key C, ~C6 that is being scanned at that time, as well as the above-mentioned keys C#6 ~C, o. The sine table 21 is a ROM, and contains the logarithm log of the reciprocal of the amplitude value data S representing each momentary amplitude value (instantaneous value) of the sine waveform. (a≧1・S>.) Each logarithm display data in the sign table 21 is stored in advance as a 12-bit data state and time, based on the output data of the shift register 20. is extracted in a time-division manner and sent to the input device A of the adder 73 (FIG. 3) in the volume control circuit 5.The coupler control circuit 30 has eight shift registers 31 to 38 connected in series, , nine weighting circuits 39 to 4 connected to the output side of the key switch scanning circuit and the output side of each shift register 31 to 38, respectively.
7, and an adder 48 that adds all weighting signals k, -k9 output from these weighting circuits 39-47.

As will be described later, each encoder provided in each weighting circuit 39 to 47 outputs operator setting value data K, to
K9 are output respectively, and these operator setting value data K
, ~K9 are input to the volume control circuit 5. Shift registers 31, 32, 33, 34, 35, 36, 37, and 38 each have a capacity of 12 stages/1 bit and 7 stages/1 bit.
Bit, 5 stages/1 bit, 7 stages/1 bit, 5 stages/1 bit, 4 stages/1 bit, 3 stages/1 bit, 5 stages. It has 1 bit and is driven by a clock pulse ◇, so that the time division multiplexed signal TDM input to the first shift register 31 is sequentially shifted to the subsequent shift registers 32 to 38.

Therefore, the time division multiplexed signal TDM input to the first stage of the shift register 31 at a certain bit time is output from the 12th stage of this shift register 31 after 12 bit times and input to the first stage of the next stage shift register 32. Furthermore, the signal DTDM (signal TDM delayed by 12 bit time) inputted to this shift register 32 is outputted from the seventh stage after 7 bit time and inputted to the first stage of the next stage shift register 33. Ru. In this way, the signal TOM is inputted to the coupler control circuit 30 and then transferred by each shift register 31 to 38 for a predetermined period of time, namely, 12 bit time, 7 bit time, 5 bit time, 7 bit time, 5 bit time, 4 bit time, and 3 bit time. The signals are outputted from each shift register 31 to 38 after being delayed by 5 bit times. Here, the input end of the shift register 31 is a point A, and the output ends of the shift registers 31 to 38 are B, C, D, E,
Name them F, G, Day, and one point. Point A is 16 feet (hereinafter, feet are indicated with a dash and written as 16).
A weighting circuit 39 corresponding to the above is connected. B
A weighting circuit 40 corresponding to 8' is connected to the point. Similarly, weighting circuits 41, 42, and 43 corresponding to C, D, B, F, G, day, and 1 point correspond to 5, 4', 2, 2,..., book, blue, and 1, respectively. ,44,45,46
, 47 are connected. Each of the weighting circuits 39 to 47 includes a slide type changeover switch 49 and an encoder 5.
It consists of three AND gates 51, 52, and 53, and has the same configuration. In FIG. 2, 16 weighting circuits 39
Only the configuration of the circuits 40 to 47 is shown in detail, and the configurations of the other circuits 40 to 47 are omitted. In the weighting circuits 39, 40 to 47, a "1" signal is supplied to the common contact of the changeover switch 49, and the signals output from the eight changeover contacts 0 to 7 are input to the encoder 501. . The encoder 50 outputs a signal corresponding to the position of each switching contact of the changeover switch 49 to the volume control circuit 5 as 3-bit operation value set value data K, and each bit signal of the data K is output to the AND gates 51 and 52. , 53, respectively. In addition, the second input terminals of the AND gates 51, 52, and 53 are all connected to point A (B
point to point 1), and furthermore, AND gates 51, 52,
Each of the 53 output signals is a 3-bit weighted signal k,,k2~
It is input to the adder 48 as k9. As a result, when the changeover contact of the changeover switch 49 is set to, for example, "5", the encoder 50 outputs 3 representing the numerical value "5".
Bit data “101”, that is, AND gate 51
, 53, a “1” signal is input to the first input terminal of the AND gate 52.
A "0" signal is output to the first input terminal of the . As a result, only AND gates 51 and 53 are opened, so at this time A
If the time division multiplexed signal TDM input to the point is a “1” signal, the adder 48 receives a numerical value “1” from the weighting circuit 39.
Data "101" representing "5" is input as the weighting signal k. Drawbars (knobs) for driving each changeover switch 49 provided in each weighting circuit 39 to 47 are arranged as shown in FIG. It is being Weighting circuits 39 to 39 in order from the left side in FIG.
Draw bars 541 to 549 are arranged corresponding to 47. When each drawbar 54, -549 is slid in the vertical direction of the figure, numbers 1 to 8 appear at the visual position, and the number shown in the top calendar of each drawbar 54, -549 is changed by that drawbar 54. It is designed to represent the changeover contact of the changeover switch 49 to be driven. In FIG. 5, for example, the changeover switch 49 of the 16 weighting circuits 39 is set to the changeover contact "2". In this way, the player can freely set the weighting of each foot by appropriately operating the setting positions of each of the drawbars 54, - 549. In addition, each shift register 31~
The signal DTDM outputted from the delayed time division multiplexed signal TDM from 38 is further weighted with a numerical value corresponding to the set position of each drawbar 54, ~549, and is outputted from the weighting circuit 39~47 of each foot as a weighting signal k, ~549. It is output as k9 and sent to adder 48. The adder 48 adds these weighting signals k, ~k9 and makes the added value 6.
The weighted signal of the bits is outputted to the volume control circuit 5 as total data K. Further, signals K and -K9 corresponding to the set positions of each of the drawbars 54 to 549 are constantly output, and these signals K and -K9 are also sent to the volume control circuit 5. Next, details of the volume control circuit 5, which is the main part of the present invention, will be explained with reference to FIG.

The signals K, ~& (3-bit linear data) that are constantly output are input to an adder 701 and summed, and the total value is outputted from the adder 70 as 6-bit operator setting value total data A. It is sent to input device A of adder 72.
Further, the output data (6-bit IJ near data) K of the adder 48 in the coupler control circuit 30 is converted into logarithmic display data (mass 10 reading value or paro coin reading value). The first converter (linear/lo
Hair conversion, converter) 71' Cut the input. This converted data is input to the input end B of the bag calculator 72.

Therefore, in the adder 72, the linear data A and the symmetrical display data log data are combined, and the data (7 bits) is sent to the input end B of the adder 73.

The input terminal A of the adder 73 receives the waveform signal 10 & outputted from the sine table 21 as a logarithmic display value (11 o rhombus display value). There are 7 books of adders that combine the power of the 8th grade signal, the power of the earth, and the power of the signal.

A second converter (log non-linear converter) outputs the calculated value log book as a 3-bit data and this pseudo data on the J near data calculation side. 74.

The output data of this second converter 74 is sent to the input A of the adder 23 in the accumulator 6. here one o
The g-display method will be briefly explained.

This notation method defines the maximum level as Goku-Ku, and lower levels are defined as, for example, 10.7 Mother Old, 11.9 Old, 1 Father Old, etc.
-12 letters, -2 letters B, etc., that is, each level is expressed by the amount of attenuation with respect to the maximum amplitude value (relative old). Also, assuming that the data is displayed in 6 bits, the least significant bit (BB) is -0.
．． 79 old, -1 in the second bit. &old, . . . -24 dB is assigned to the most significant bit (MSB, 6th bit). For example, only B is a binary logic level "1"
This represents a signal at a level of -0.79B. Further, when each bit is "1", that is, "111111", it is indicated that the level of the signal is the total value of each bit, that is, the minimum value of -47.2 ears. Also,
Sign table 21 that outputs symmetrical display data respectively
, the first converter 71, and the second converter 74 that converts logarithmic display data into linear data are both storage devices composed of ROM (read only memory) or the like, and accept input data as an address signal. It is configured to output data having a value corresponding to this input data. The output data of the register 24 of 15 bits per stage is inputted via the gate circuit 22 to the second input terminal B of the adder 23 of the accumulator 6, which is inputted to the input terminal A.

Adder 23 adds both input data, and the added value is 15
The above data is input to the register 24 as bit parallel data. This register 24 is driven by the aforementioned clock pulse and outputs the read data to the gate circuit 22 and latch circuit 7 as 15-bit parallel data. The gate circuit 22 operates at the end of one scanning period, that is, when the SYC
A signal SYC obtained by inverting the signal SYC by an inverter 25 is inputted as a control signal so that it is always open except when the signal SYC is output. Furthermore, the latch circuit 7 is provided with a signal SYC as a data programming signal. Therefore, at the start of one scanning period (
When the content of the 12G ship counter is 0), the noise control circuit 5 outputs the data and adds it up.When the content of the 12G ship counter reaches 118, the adder 23 performs the final addition.

When the content of Hayabusa counter 12 becomes 119, signal S
Since YC is output, the last accumulated value of the adder 23 (this accumulated value is stored in the shift register 24) is latched in the latch circuit 7. The latched data is further sent to the DA converter 8, amplifier 9, and speaker 101, as described with reference to FIG. The operation of the electronic musical instrument configured as described above will now be described with reference to the operation waveform diagrams shown in FIGS. 6 and 7.

Now, within one scanning period, keys C,,D2,G#5
It is assumed that the keys are pressed at the same time. It is also assumed that each of the drawbars 54, -549 of the coupler control circuit 30 is set to the state shown in FIG. By the operation of the hexadecimal counter 15 and the 1-bit counter 16 of the timing signal generation circuit 3, the operation for one scanning period is started from when the content of the hexadecimal counter constituted by these counters 15 and 16 is 0.

When the content of the 120-decimal counter is between 0 and 11 (that is, the content of the 1Q Hayabusa counter 16 is 0), the output signal “1” of the decoder 11 of the key switch scanning circuit 2 is output from the key switch circuit 1.
is output only to column line 1, and the key switches of each key C, ~B, of the first octave are scanned.

During this time, the decoder 12 detects that the content of the hexadecimal counter 15 is 0.
As the output terminals change sequentially from 0 to 11, the output terminals 0 . A "1" signal is sequentially output from ○ to 2, and the corresponding AND gates 13 to 138 are sequentially opened. In parallel with the above operation, the output signals of the 120-decimal counter N, ~N4, B~
By B4, the frequency number memory 18 of the time-division waveform generation circuit 4 is sequentially designated with addresses corresponding to each key C, ~B, and as a result, frequency numbers R corresponding to the pitches of keys C, ~B are sequentially output. and input to the adder 19.

The adder 19 adds the output data of the shift register 20 and the frequency number R, and sends the added value to the shift register 20.
Repeat the output operation. Also, since the upper 8 bits of the output data of the shift register 20 are input to the sign table 21, the logarithmically expressed sine amplitude value 10 corresponding to keys C, ~B is output from the sign table 21 during this period.
& is sequentially output in a time-division manner and input to the input terminal A of the adder 73 of the volume control circuit 5. In this example, since key C is pressed, key C, which is pressed at the start of this one scanning period, is detected first. Therefore, the output signal of the AND gate 13 of the key switch scanning circuit 2 is "1".
Therefore, the time division multiplex signal TDM becomes "1" when the content of the 12-go Hayabusa counter is 0 (FIG. 7A).
This signal TOM1'') is input to the shift register 31 and also to the AND gates 51 to 53 in the 16 weighting circuits 39.
to open. Since the changeover switch 49 of the 16 weighting circuits 39 is set to the contact 2 (see FIG. 5), data k representing the numerical value 2, "0" is output from the AND gates 51 to 53.
101'' is output and sent to the adder 48. Assuming that the contents of shift registers 31 to 38 are all 0 before the start of this one scanning period, the contents of the 12G ship counter are 0.
The output signals of the shift registers 31 to 38 (ie, the output signals of points B to 1) at the time point are all 0. Therefore, the output data K of the adder 48 is "0", which is equal to the set value 2 of the drawbars 54 of the 16 weighting circuits 39.
10". The key C input into the shift register 31,
The above signal TDM (“1”) is output to point B after 12 bit time (when the content of the 12Q Hayabusa counter is 12) and input to the shift register 32 (FIG. 7B).
.

This signal is sequentially shifted to the subsequent shift registers 33 to 38 and output to points C to 1 (see Fig. 7).
1), the contents of the 12G ship counter at that time are as follows:
19, 24, 31, 36, 40, 43, 48 (see Figure 7). Similarly, keys 2 and G#5 are detected when the contents of the 12G ship counters are 14 and 56, respectively.
At this time, the time division multiplex signal TDM becomes a ``1'' signal.
This signal TDM (“1”) is transmitted to shift registers 31 to 38.
are sequentially shifted. Therefore, signals as shown in FIG. 7 are sequentially output to each point A to 1 within one scanning period. Then, each time the signal "1" is output to each point A~1, the set value of the changeover switch 49 (drawbar 54-549) in the corresponding weighting circuit 39~47 changes to the signal k,
~k9 is output to the adder 48. The adder 48 adds data k, to k9 outputted from the weighting circuits 39 to 47 of each foot at that time to 0 for each bit time, and outputs the added data K to the first converter 71.
The first converter 71 converts the addition data K, which is linear data, into logarithmic display data/0&table, and outputs this converted data as an input data of Oyasu Hunger 72. In addition, the set values K, ~ for each drawbar 54, ~549, which are set in the state shown in Fig. 5, are
K9 is constantly sent to the adder 70 and summed from this adder 7, resulting in total value data A (in the case of Fig. 5, A=48).
is calculated and sent to input terminal A of adder 72.

Therefore, the adder 72 adds the linear data A and the logarithm display data log poison, and the added data 10 & foundation is (l
og is +loga Hiroshi) is output to the input terminal B of the adder 73. On the other hand, the sine table 21 outputs graded signals (the sine amplitude side has a logarithmic display value of 1.8) corresponding to each key C, ~C6, C#6 ~C, o for each bit time, and outputs it to the adder. It is sent to input terminal A of 73.

The ratio calculator 73' has a sine amplitude value of 1. The data input corresponding to the keys C, , D2, and G#5 that are currently being pressed are added to the log data of the second converter 7.
Send 41.

The second converter 74' is also different from the above. & the road is near de-
On the data side, this data is output to the input terminal A of the calculator 23.

Therefore, at the start of one scanning period mentioned above (when the content of the 12-point counter is 0), first, the data k corresponding to the key C is stored. This data is converted into log data by the converter 74' of the log data converter 2, and is input to the adder 23 of the accumulator 6.

Here, the data K is equal to the set value 2 of the drawbar 54, and the data A=48 (i.e., the converter 74
(The output data becomes the pot). This day, the entrance of Irifune B of Yagi Sakai 23 is defeated, and the female detainee is hated.

This data is circulated and stored in the false memory storage 6 until the 12th bit time (content 11 of the 120-decimal counter). At the 13th bit time (content 12 of the 120-decimal counter), the time division multiplexed signal TDM (“
1'' signal) is delayed and output from the shift register 31, so the signal k2 for this delayed signal DTDM is 8.
is output from the weighting circuit 41.

Since the set value of the drawbar 542 is 5, k2=5
, and thus the adder 73' yields starvation-takami 1. & Sparrow and false This result・Output data of the second converter 74
The adder 23 calculates the data that had been held up to that point and the upper and lower edges, and outputs the data.

This new data is held in the accumulator 6 until the time division multiplexed signal TDM for key 2 is output at the 5th bit time. Similarly, the seventh
Similar operations are performed for each signal shown in Figures A-1,
Immediately before the end of one scanning period (the content of the 12G Hayabusa counter is 118), the accumulator 6 is
This is the cumulative value of each data abundance for each strata in the area. When the signal SYC is output at the end of this one scanning period, this cumulative value is latched in the latch circuit 7, and further outputted to the speaker 1.
01 is sent and pronounced as a musical tone. If the set position of any of the drawbars is changed during the one scanning period, the added value A of the adder 70 will of course change accordingly. Furthermore, when the operation of one scanning period is completed, the operation of the next scanning period is started. By the way, the output data of the second converter 74 is the product of data KS' and data y.

As shown in Figure 6, the data sheep has drawbars 54,
~549 This is data that is inversely proportional to the number of inputs and its set value (that is, data A), and is data that decreases as the number of inputs and the set value (data A) increase. On the other hand, data KS is data approximately proportional to the number of keys pressed. For this reason, the output data kiln characteristic curve of the second converter 74, as shown in FIG. 6, depicts a saturation curve that saturates to a predetermined level as the data A increases. Therefore, according to the electronic musical instrument of the present invention, even if the number of input drawbars 54, to 549 and their set values are large, the function of the volume control circuit 5 allows
It can be seen that the volume of the musical tone is suppressed to a predetermined value or less. Next, a modification of the volume control circuit 5 in the above embodiment will be explained with reference to FIG.

This volume control circuit 5' differs from the circuit 5 described above in that the adder 72 in the circuit 5 is replaced with a subtracter 72' in the circuit 5'. For this purpose, the first converter 71' receives the input data K and generates the logarithm display side ogaK, and the subtracter 72
' is sent to input end B of '. Data A from the adder 70 is input to an input terminal A of the subtracter 72'. As a result, subtractor 7
2', a subtraction (logK-A) is performed and the value of the subtraction value is obtained. This data log hair is adder 73
, and the other input device A receives a logarithmically expressed waveform signal (sine amplitude value) lo&S output from the sine table 21'. As a result, adder 7
From 3 onwards, the second number 74'' was sent. According to the second count 74, the near data is touched, and this data is sent to the state where the nose accumulates.

In this way, in the case of circuit 5', the same data as circuit 5 is used.
The above-mentioned effects can be obtained in the same way.

Another modification of the volume control circuits 5, 5' will be described next. In this modification, the adder 70 provided in the circuits 5, 5' is omitted, and the coupler control circuit 3
This allows the adder 48 in 0 to be used in place of the adder 70 described above.

As mentioned above, one scanning period is 12 in the case of the above embodiment.
Although it is 0 bit time, the number of keys is 61, and the total delay time of shift registers 31 to 38 in the coupler control circuit is 48 bit times. Therefore, of the 0 to 119 bit times in one scanning period, the 109 to 118 bit times are not used for scanning the key switch or for the coupler function, and are an empty time period. Therefore, in FIG. 2, each point A~ in the coupler control circuit 30
1 is configured to apply a "1" signal simultaneously at any bit time in the above-mentioned vacant time slot, and at that time, the signals k, -k9 obtained from each weighting circuit 39-47 are applied to the adder 48. If the adder 70 of the volume control circuits 5 and 5' is omitted, the adder 70 of the volume control circuits 5 and 5' can be omitted, and the configuration can be further simplified. . As explained above, this invention adds a volume control circuit to the electronic musical instrument previously proposed by the applicant, so that the volume of generated musical tones can be automatically controlled to an optimal value according to the drawbar engagement state. Therefore, there is no need to manually adjust the volume every time the tone color is changed, which is extremely convenient, and the S/N ratio can be improved to generate high-quality musical tones.

In addition, the volume control circuit has an extremely simple configuration and can be integrated into an integrated circuit, contributing to the miniaturization of electronic musical instruments.
There are various advantages.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 to 7 show an embodiment of the electronic musical instrument of the present invention, FIG. 1 is a block diagram showing the overall configuration of the electronic musical instrument, and FIGS. 2 and 3 show an embodiment of the electronic musical instrument. 4 is a detailed circuit diagram of the main part of the same example, FIG. 4 is a diagram showing the correspondence between one scanning period and each key in the same example, and FIG.
This figure shows one set state of the drawbar of the same example, FIGS. 6 and 7 are explanatory diagrams of the operation of the same example, and FIG. 8 is a diagram showing a modification of the volume control circuit of the electronic musical instrument. 1... Key switch circuit, 2... Key switch scanning circuit, 3... Timing signal generation circuit, 4
...Time division waveform generation circuit, 5, 5'...Volume control circuit, 6...Accumulator, 7...
... Latch circuit, 11, 12 ... Decoder, 15,
16... Counter, 18... Frequency number memory,
21, 21'... Sign table, 30... Cobra control circuit, 31-38... Delay circuit (shift register), 39-47... Weighting circuit, 48...
... Adder, 54-549 ... Drawbar, 70
...Adder, 71, 71'...First converter, 72,
72', 73... Arithmetic circuit (adder, subtracter, adder)
, 74, 74'... second converter. Figure 1 Figure 3 Figure 4 Figure N Ship Figure 5 Figure 6 Figure 7〇Wisteria

Claims (1)

[Scope of Claims] 1. A plurality of key switches, key switch scanning means for sequentially scanning each of these key switches at a desired speed to generate a time-division multiplexed signal indicating the key depression state of each key, and the above-mentioned time-division multiplexing means. a delay means for outputting a signal delayed by a predetermined time; and a weighted signal by weighting the time division multiplexed signal and the output signal of the delay means according to setting values set by operating corresponding operators, respectively. a waveform generating means for time-divisionally generating a waveform signal corresponding to each pitch in synchronization with the scanning of the key switch, and weighting the waveform signal in accordance with the weighting signal. In the electronic musical instrument, the control means further includes arithmetic means for calculating a total value of the set values of each of the above-mentioned operators, and a calculation means for calculating a total value of the set values of each of the above-mentioned operators, and increasing the total value based on the above-mentioned total value. An electronic musical instrument characterized by comprising means for suppressing and controlling the volume level of the musical tone signal according to the above. 2. The waveform generation means generates, as the waveform signal, amplitude value logarithmic display data corresponding to amplitude value data S representing each amplitude value that changes from time to time of the waveform, and the control means an adder for adding operator setting value data representing a setting value by a child; a first conversion circuit for converting the weighted signal into logarithmic display data; a first arithmetic circuit that executes a predetermined arithmetic operation based on the converted output data; a second arithmetic circuit that executes a predetermined arithmetic operation based on the output data of the first arithmetic circuit and the amplitude value logarithm display data; 2. The electronic musical instrument according to claim 1, further comprising: a second conversion circuit that converts the output data of the second arithmetic circuit into linear display data. 3 The adder inputs the operator setting value data K_1, K
The first conversion circuit outputs added data A obtained by adding _2..., and the first conversion circuit outputs the weighted signals k_1, k
The addition data K obtained by adding _2... is logarithm display data lo
g_a1/K, and the first arithmetic circuit adds the logarithm display data log_a1/K and the addition data A to output data log_a(a^A)/K, The second arithmetic circuit adds the data log_a(a^A)/K and the amplitude value logarithm display data log_a1/S to obtain data log_a(a^A)/K.
A)/(KS), and the second conversion circuit outputs the data log_a(a^A)/(KS).
3. The electronic musical instrument according to claim 2, wherein the electronic musical instrument converts the data into data (KS)/(a^A). 4 The adder receives the operation setting value data K_1, K_
It outputs added data A obtained by adding 2...
The first conversion circuit converts the weighting signals k_1, k_
The addition data K obtained by adding 2, ... is logarithm display data lo
g_aK, and the first arithmetic circuit converts the logarithm display data log_aK and the addition data A
Add the data 1/A based on the data log_a
K/(a^A), and the second arithmetic circuit adds the data log_aK/(a^A) and the amplitude value logarithm display data log_aS to obtain data lo.
g_a(KS)/(a^A), and the second conversion circuit outputs the data log(KS)/(a
3. The electronic musical instrument according to claim 2, wherein the electronic musical instrument converts ^A) into data (KS)/(a^A).