JPS602674B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generates a time-division multiplex declaration signal indicating the pressed state of a plurality of keys, and also generates a waveform signal corresponding to the above-mentioned time-division multiplexed signal in a time-divisional manner. Regarding an electronic musical instrument that can simultaneously produce a large number of musical tones corresponding to the pressed keys by multiplying the signal and the above-mentioned time division multiplexed signal, in particular, the volume of the generated musical tones can be adjusted according to the number of keys being pressed. This invention relates to an electronic musical instrument that can be effectively controlled.

This applicant previously provided an electronic musical instrument of the invention described in the specification of Tokkyo No. 52-150895 (see Japanese Patent Publication No. 954-83419), the title of the invention being "electronic musical instrument." To summarize the invention, a plurality of key switches are sequentially scanned at a predetermined speed to generate a time-division multiplexed signal indicating the pressed state of each key, and a waveform corresponding to each pitch is generated in synchronization with the key switch scanning. An electronic musical instrument is characterized in that a signal is generated in a time-division manner, and a musical tone signal is obtained by multiplying this waveform signal and the above-mentioned time-division multiplexed signal. are sequentially scanned at a predetermined speed to indicate the pressed state of each key, and a signal obtained by delaying this time-division multiplexed signal by a predetermined time is used as a weighted signal that is weighted according to the setting position of the corresponding operator. At the same time, a waveform signal corresponding to each pitch height is generated in a time-division manner in synchronization with the scanning of the key switch, and a musical tone signal is obtained by multiplying this waveform signal and the above-mentioned erosion signal. This electronic musical instrument has the excellent feature of being able to simultaneously generate a large number of musical tones with such a simple configuration.Incidentally, even in the above-mentioned electronic musical instrument, sometimes a very large number of musical tones can be generated. key (for example 1
When a key (harder or higher) is pressed, the volume of the musical tone becomes enormous.

The invention of this application was made in consideration of the above circumstances,
The purpose is to provide an electronic musical instrument that can always produce musical tones of optimal volume depending on the number of keys pressed.

In the first invention of this application, the number of keys being pressed is detected, and the volume level of the waveform signal is controlled based on the detected data of the number of keys being pressed.

Further, in the second invention of this long-cherished desire, the number of keys being pressed is detected, and the volume level of the waveform signal is controlled based on the detection data of the number of keys being pressed and the weighting signal. As a result, the electronic musical instrument of the present invention can obtain a musical tone signal with an optimal volume corresponding to the number of keys pressed, and can automatically perform effective volume control, especially when a large number of keys are pressed at the same time. be. Hereinafter, specific examples of the invention of this application will be described with reference to the drawings.

In FIG. 1, the electronic musical instrument of the present invention is roughly divided into a key switch circuit 1 having a large number of key switches arranged in a matrix and provided for each key on a keyboard (not shown); A key switch scanning circuit 2 that sequentially scans each key switch of the key switch circuit 1 and outputs a time division multiplexed signal TDM representing the open/closed state of each key switch, that is, the key pressed state; A timing signal generation circuit 3 generates a timing signal for controlling the operation of the time-division waveform generation circuit 4, etc., and a logarithm of the period corresponding to the pitch of each key is displayed in synchronization with the scanning of the key switch circuit 1. A time-division waveform generation circuit 4 generates a waveform signal (sound source signal or musical tone signal) loga (a≧1, S>0) in a time-division manner, and a time-division multiplexed signal TDM is inputted to generate the time-division multiplexed signal TDM. are sequentially delayed by a plurality of delay circuits by a predetermined time, and the time-division multiplexed signal TDM and its delayed signal DTDM are input to the corresponding weighting circuits to obtain a weighted signal k, which is weighted with a predetermined weight.
~k9, and the weighting signals k, which are output from the coupler control circuit 30.
- Time division multiplexed signal TDM output from the k9 key switch scanning circuit 2, signal SYC to be described later, and the above waveform signal l
oga is input, the volume control circuit 5 outputs a musical tone signal whose volume is controlled according to the number of keys pressed, and the output signal of this volume control turner 5 is input, and one scan of the key switch circuit 1 starts. an accumulator 6 for cumulatively adding up the above output signals within one scanning period from time to end of scanning; a latch circuit 7 to which the contents of the accumulator 6 are input and latched at the end of each scanning period; and an output of this latch circuit 7. D4 converter 8 that converts a signal (digital signal) into an analog signal
, an amplifier 9 that amplifies the output signal of the D~ converter 8, and a speaker 10 that produces the output signal of the amplifier 9 as a musical tone.

Next, the configuration of each of the above-mentioned parts will be explained in detail with reference to FIGS. 2 to 5.

As we all know, one octave has 12 notes: C, C#, D,
...,B, but in this example, the 12 keys of the first octave (these keys are C,,C#,D,,...
, B), 12 keys C2 of the second octave,
C#, D2, ......, B2, 12 keys each in the 3rd to 5th octaves, and one key C6 in the 6th octave, which follows the same notation, making a total of 61 keys ( (not shown). The 61 key switches corresponding to these 61 keys are arranged in a matrix in the key switch circuit 1 as shown in the second figure. That is, the column lines 1, . It corresponds to For example, a key switch for the first octave key E is disposed at the intersection of the column line 1 and the row line 1. Note that the circles marked at the intersections of column lines 1, ~16 and row lines L, ~L, and 2 in the figure indicate that the above-mentioned key switch is connected in series with a forward diode between the corresponding column line and row line. Indicates that it is connected. Here, the configuration of the timing signal generation circuit 3 will be explained.

This circuit 3 consists of a 4-bit hexadecimal counter 1 that is driven by a small number of clock pulses that are constantly output at a predetermined period.
5 (Contents of this counter 15 “0000” to “1101”
C. 1G boat number display "0" to "IL; hereinafter expressed in 1-bo Hayabusa number display; corresponds to each pitch name C to B, respectively)
and a 1-bit Hayabusa counter 16 with a 4-bit configuration driven by the dot output signal N4 of the most significant bit (4th bit) of this hexadecimal counter 15 (the content of this counter 16 is "0").
00'' to ``101ha 15 ship number display ro'' to ``6''; hereinafter expressed in decimal notation; corresponds to the 1st to 6th octaves, respectively), and the 1st to 6th octaves of the decimal counter 5, 2, 4-bit output signals N, , N2, N4 and 1
1st and 4th bit output signals B,, & of G ship counter 16
is directly input, and the third one of the hexadecimal counter 15
The bit output signal N3 and the second bit output signal N3 of the one-way counter 16,
AND gate 1 to which the 3-bit output signal &, B3 is input via the corresponding inverters 65, 66, 67, respectively.
7.

The output signal of this AND gate 17 is called a signal SYC, and one scanning period, which will be described later, is defined by this signal SYC. 1st to 4th bit output signal N of hexadecimal counter 15
, ~N4 are input to the decoder 12 in the key switch scanning circuit 2.

That is, the signals N, to N4 representing the contents of the counter 5
is decoded by the decoder 12, and the I
To any of the Z output terminals ○, ~08,
, is output as a 1'' signal.For example, the content of the hexadecimal counter 15 is the content 7 corresponding to the pitch name G (IG Hayabusa number display)
In this case, a 1'' signal is output only from the output terminal 08 of the decoder 12.The first to fourth bit output signals B to B4 of the decimal counter 16 are output from the ground decoder 1 in the key switch scanning circuit 2. has been entered.

That is, signals B, ~B4 representing the contents of the counter 6
is decoded by the decoder 1, and its output signal is output as a 11'' signal to any one of the column lines 1 to 16 of the key switch circuit 1.For example, the contents of the counter 6 When is content 2 (in decimal notation) representing the third octave, the only 1'' signal is output to the column line 13, and each key C3,
C#, . . . , B3 are configured to be scanned during this period. The output signals of the row lines L, .about.L, 2 of the key switch circuit 1 are input to the first input terminals of the corresponding AND gates 13, .about.13, 2 in the key switch scanning circuit 2, respectively. The output signals of the output terminals ○, .about.0, 2 of the decoder 2 are input to the second input terminals of the AND gates 13, .about.13, 2, respectively. Also each and gate 1
The output signals of 3, .
and is input to the volume control circuit 5. Since the timing signal generation circuit 3 and the key switch scanning circuit 2 are configured as described above, a 12G ship counter is formed by both counters 15 and 16, and the output signals N,
~N4,B~& (representing content 0 to 119), 6
One scanning period (FIG. 4) of the key switch circuit 1 consisting of one key switch is defined.

That is, FIG. 4 shows the correspondence between the contents of the 12G Hayabusa counter (each bit time) 0 to 119 within one scanning period consisting of 120 bit times and the type of key to be scanned. Since the number of keys used in this invention is 61, 1
During the period in which the contents of the 20-decimal counter are 61 to 119, key switch scanning is not actually executed. The decoder 2 to which the bit output signals N, ~N4 of the hexadecimal counter 5 is input is configured such that the contents of the hexadecimal counter 15 are 0 to 11 as described above.
When , 1'' signals are outputted to the output terminals ○, to ○, 2 in sequence.

Therefore, when the content of the hexadecimal counter 5 is, for example, 0, the AND gate 13 is opened, and at this time, the key C,, C2, .
...If C6 is pressed, AND gate 13
, a key press signal is output, and this signal is further output via an OR gate 14 as a time division multiplexed signal TDM.
When one scanning period is started in this way, the pressed states of the 61 keys C,, C#, .
When the contents of the 2G Hayabusa counter change sequentially from 0 to 119, the keys are scanned sequentially starting from the first octave key.
The signal SYC is output only when the contents of the G ship counters 15 and 16 are 119. This signal SYC is input to an accumulator 6, a latch circuit 7, and a volume control circuit 5, which will be described later. Also, the first to fourth bit output signals N. of the hexadecimal counter 15 in the timing signal generation circuit 3 ~N4 and 1G ship counter 16 1st to 4th bit output signals old, ~
Both & are input to the frequency number memory 18 in the time division waveform generation circuit 4 as address designation signals.

As a result, the frequency number memory 18 is addressed in synchronization with the scanning of each key switch of the key switch circuit 1, and from this frequency number memory 18, a numerical value proportional to the frequency corresponding to the pitch of the key currently being scanned ( Hereinafter referred to as frequency number) R is output, and this frequency number R (1
(data represented by 7 bits) is input to the first input terminal A of the adder 19.

Note that this frequency number memory 18 includes keys C# to C, which are not actually provided. A frequency number memory R corresponding to (for 48 keys) is also stored. That is, the time division multiplexed signal TOM output from the key switch scanning circuit 2
As will be described later, is input to the shift registers 31 to 38 (48 stages in total) in the coupler control circuit 30 and is delayed, so the corresponding frequency number R is also given to this delayed signal DTDM. This is because it is necessary to generate a corresponding waveform signal. The second of the adder 19
The output data (20 bits) of the shift register 20, which will be described later, is input to the input terminal B. Therefore, the adder 19 adds the frequency number R and the output of the shift register 20, and the added value is sent to the shift register 2. This data is input as 20-bit parallel data. The shift register 20 has 120 stages and a capacity of 20 bits per stage, and is driven by a clock pulse to sequentially shift the added value output from the adder 19. That is, adder 1
9 and the shift register 20 independently and sequentially repeatedly add the frequency numbers R corresponding to each pitch. Of the output data (120th stage output) sequentially output from the shift register 20 in a time-division manner, the upper 8 bits of data are input to the sign table 21 as an address signal. This 8-bit data has contents corresponding to the pitches of the keys C, -C6 being scanned at that time, as well as contents corresponding to the pitches of the keys C# - C, o described above. The sine table 21 is a ROM, and the sine table 21 contains the log number of work areas of the shaking arm data S representing each amplitude value (instantaneous value) that changes from moment to moment of the sine waveform.
A words (a≧1, S>0) are stored in advance as 12-bit data.

Then, each logarithm display data loga in this sine table 21 is read out in a time-division manner based on the output data of the shift register 20, and the adder 7 in the volume control circuit 5
8 (FIG. 3). Coupler control circuit 3
0 is eight shift registers 31 to 38 connected in series.
and nine weighting circuits 39 to 47 connected to the output side of the key switch scanning circuit and the output side of each shift register 31 to 38, respectively, and these weighting circuits 39 to 47.
, and an adder 48 that adds all the output signals k, to k9.

Shift registers 31, 32, 33, 34, 35, 36,
37 and 38 each have a capacity of 12 stages. 1 bit, 7
stage. 1 bit, 5 stages. 1 bit, 7 stages. 1 bit, 5 stages. 1 bit, 4 stages. 1
Bit, 3 stages. 1 bit, 5 stages. 1 bit and is driven by clock pulse 01,
The time division multiplexed signal TOM input to the first shift register 31 is sequentially shifted to the subsequent shift register side (32 to 38).

Therefore, the time division multiplexed signal TDM input to the first stage of the shift register 31 at a certain bit time is output from the 12th stage of this shift register 31 after 12 bit times and input to the first stage of the next stage shift register 32. Furthermore, the signal DTDM (signal TDM delayed by 12 bit time) inputted to this shift register 32 is outputted from the seventh stage after 7 bit time and inputted to the first stage of the next stage shift register 33. Ru. In this way, the signal TOM is inputted to the coupler control circuit 30 and then transferred by each shift register 31 to 38 for a predetermined period of time, namely, 12 bit time, 7 bit time, 5 bit time, 7 bit time, 5 bit time, 4 bit time, The signals are outputted from each shift register 31 to 38 after being delayed by 3 bit times and 5 bit times. Here, the input end of the shift register 31 is connected to point A,
Each output terminal of shift registers 31 to 38 is connected to B, C, D, and E.
, F, G, day, and one point. A weighting circuit 39 corresponding to 16 feet (hereinafter, feet are indicated by a dash and expressed as 16') is connected to point A.
A weighting circuit 40 corresponding to 8' is connected to point B. In the same way, weighting circuits 41, 42, 43, 44 corresponding to points C, D, B, F, G, and 1 point, respectively, correspond to 5 g, 4', 2 winter 2', ・Mo・Hori, and 1 point. 45, 46, 4
7 is connected. Each of the weighting circuits 39 to 47 includes a slide type changeover switch 49, an encoder 50,
It consists of three AND gates 51, 52, and 53 and has the same configuration. In FIG. 2, only the configuration of the weighting circuit 39 16' is shown in detail, and the configurations of the other circuits 40 to 47 are omitted. In the weighting circuit 39 (40 to 47), the common contact of the changeover switch 49 is supplied with the , 1'' signal, and the signals output from the eight changeover contacts 0 to 7 are sent to the encoder 50. The encoder 50 outputs a signal corresponding to the position of each switching contact of the changeover switch 49 as 3-bit data, which is input to the first input terminals of AND gates 51, 52, and 53, respectively. Also, AND gates 51, 52
, 53 are both connected to point A (point B to point 1), and each output signal of AND gates 51, 52, and 53 is sent to adder 4 as 3-bit data k, (k2 to k9).
8 is input. As a result, when the switching contact of the selector switch 49 is set to "5", for example, the encoder 50 outputs 3-bit data "1" representing the numerical value "5".
01'', that is, the first input terminal of the AND gates 51 and 53, the 1'' signal, and the first input terminal of the AND gate 52, 0
” signal is output. This causes AND gates 51, 5
3 is opened, so if the time division multiplexed signal TDM input to point A at this time is a 1'' signal, data "101" representing the numerical value "5" is sent to the adder 8 from the weighting circuit 39. will be input. Each weighting circuit 3
The drawbars (knobs) for driving each of the cut-out switches 49 provided in the slots 9 to 47 are arranged as shown in FIG. There is. Draw bars 54 .corresponding to weighting circuits 39 to 47 in order from the left side in FIG. ~549 are arranged. When each drawbar 54 - 548 is slid in the vertical direction of the figure, numbers 1 - 8 appear at the visual position, and the number shown directly at the top of each drawbar 54 - 549 is the drawbar 54 - 548 . ~549
It is designed to represent the switching switch 49 driven by the switching switch 49. In FIG. 5, for example, the switching switch 49 of the weighting circuit 39 16' is set to the switching contact "2". In this way, each drawbar 54, ~
549, the player can freely set the weighting of each foot. Also, the signal DT which is delayed and outputted from each shift register 31 to 38
The DM is further weighted with a numerical value corresponding to the set position of each drawbar 54, ~549, and outputted as data k, ~k9 from weighting circuits 39~47 of each foot,
It is sent to adder 48. The adder 48 receives these data k,
~k9 is added and the added value is output to the volume control circuit 5 as 6-bit data K. Next, details of the volume control circuit 5, which is the main part of the present invention, will be explained with reference to FIG.

This circuit 5 is roughly divided into a key press number detection circuit 80 which receives the time division multiplexed signal TDM outputted from the key switch scanning circuit 2 as an input signal and is controlled by the signal SYC;
The output data K (linear value) of the adder 48 of the coupler control circuit 30 is outside the logarithmic display data. A first converter 76 that converts the number of pressed keys into actual data, the output data A (linear value) of the key press number detection circuit 80, and a calculator that calculates the output of the first converter 76 as -10ga barley. 7 and the addition output data l of this adder 77
The adder 78 calculates the logarithmically displayed waveform signal (sine amplitude value) output from the sine table 21 and the summation output of this adder 78. A second converter 79 converts the output signal into a musical tone signal.

In the key press number detection circuit 80', a signal SYC obtained by inverting the signal SYC from the inverter 7 is input as a control signal to the first input terminals of the AND gates 71 and 714.
Further, each of the second input terminals is connected to a register 74, which will be described later.
Each bit signal r, to r4 of output data (4 bits) is input. Therefore, the signal SYC=,,0″(2
value logic signal), the output signal SYC of the inverter 70
However, it becomes a 1'' signal and each AND gate 71, to 714
are in the operating state, and the bit signals r, ~r4 pass through them to the corresponding addition input terminals A,..., A3 of the adder 72.
, is input. Also, the carry input terminal C of the adder 72
The time division multiplexed signal TDM is input to i, so the adder 72 combines the signal TDM and the bit signals r, to r
4 bits of data represented by
2, S3, and the corresponding OR gate 73 output from S4,
~1 stage via 734. The signal is input to each bit of a register 74 having a 4-bit configuration. When the added value of the adder 72 becomes 15 (that is, "1111" in binary notation) or more, a signal of 1" (carry output) is output from the carry output terminal Co, and this 1" signal is transmitted to each of the or gates. −
The signals are input to each bit of the register 74 via ports 73 and 734. In other words, the number of simultaneous key presses within one scanning period is 15.
All of the above cases are considered to be 15, and the maximum value of the number A of pressed keys is defined as 15. The transfer register 74 is driven by a clock pulse and outputs the input data as signals r, ~ [4, and the AND gates 71, ~7
14 and latch circuit 75. The latch circuit 75 uses the signal SYC as a data read signal.
, 1'', that is, at the end of one scanning period, captures and stores the output data (r, to r4) in the register 74,
The data (r, ~r4) until the end of the next one scanning period
hold. The output data A of this latch circuit 75 (that is, the number of keys pressed simultaneously during the previous scanning period) is sent to the input terminal A of an adder 77, and the output data of the first converter 76 is sent to the input terminal B of this adder 77. Data loga poison is being sent. And adder 77's sword o calculation day 10ga Sharyu calculation 7
The output data loga of the sine table 21 is input to the input terminal A of the adder 78. Then, the output data of the adder 78 is converted into the data of the second converter side, and is sent to the input terminal A of the adder 23 in the accumulator 6.

Note that the numbers shown on each signal line in FIG. 3 represent the number of bits of data. With the above configuration, at the end of one scanning period (when the content of the 12G ship counter is 119), the signal SY
C(,,1″) is output and the output of the inverter 70 is
, 0'', each output of the AND gates 71, to 714 becomes 0'', and each output, 0'' is output from the adder 72.
is supplied to each input terminal A, ~A4 of. At this time, the signal T
DM is always 0'' (because the signal T
DM (,, 1″) is a signal that is output only when the contents of the 12G ship counter are between 0 and 60 within one scanning period),
The input to the carry input terminal Ci of the adder 72 is 0". Therefore, the signals output from each output terminal S, ~S4 of the adder 72 are both 0^. Therefore, the register 74 has data "0000'' is input at the end of one scanning period and its contents are cleared. 12 When the content of the counter becomes 0 and the next one scanning period starts, the outputs r, .about.r4 of the register 74 become "0000" and are supplied to the AND gates 71, .about.714. At this time, since the signal SYC is 0'', the output of the inverter 70 is 1'', and the AND gates 71, 714 remain in operation until the scanning period ends. The content "0000" of the register 74 is held as a shield until the signal TDM (ilr; this signal TDM is a signal corresponding to the pressed key) is output for the first time after this scanning period starts, and the content of the adder 72 is The inputs of each input terminal A, ~ are 0''. When the signal TDM (, 1'') is input to the carry input terminal i, the adder 72 adds this 1'' signal. Data "0001" is output from the output terminals S, -S4, and this data "0001" representing the number of pressed keys (1) is input to the register 74 and stored. Then, the data “000” is output until the signal TDM (,, 1″) corresponding to the next pressed key is output.
1" is held in circulation. Second signal TDM (i1″)
When this is output, data “0010” (data representing the number of pressed keys, 2) is output from the output terminals S, -S4 of the adder 72 and input into the register 74.

In this way, the signal TDM(,,r) corresponding to the pressed key is
Each time , the adder 72 adds this signal TDM (,, 1[) to the previously added data to calculate new added data, inputs this added data to the register 74, Data is held circularly. When the content of the 12G ship counter reaches 60, the last key (C6) is scanned, and addition data representing the actual number of pressed keys is input to the register 74.

This added data is held in circulation until the end of this scanning period. When the signal SYC (,, 1'') is output at the end of the scanning period, the data representing the number of key presses detected within this scanning period is latched into the latch circuit 75, and at the same time the contents of the register 74 are changed to the above-mentioned values. Data A representing the number of pressed keys latched in the latch circuit 75 is input to the input terminal A of the adder 77. Logarithmic display data loga table is input to the input terminal B of the adder 77. (I've been there)
The calculation data of adder 77 becomes logarithm display data (waveform signal) in adder 78.
It is added to ga.

Then, the result is the linear display data of the 79-meter linear display data of the 2nd grade of the Yanagi calculation and sent to the accumulator 6.

A sine table 21, a first converter 76, and a second converter 79 each outputting the various types of logarithmic display data described above.
Both are storage devices composed of ROM (read only memory) or the like, and are configured to accept input data as an address signal and output data having a value corresponding to the input data. Further, the logarithmic display values of the various logarithmic display data described above are generally referred to as the minus log display method.

In this display method, the maximum level is defined as a blank, and each level below the maximum level is represented by an amount of attenuation with respect to the maximum level (MB). For example, in the case of 6-bit logarithmic display data, the least significant bit (LSB) is -0.7B, the second bit is -1. & old, -x old to the 3rd bit, Ikko B to the 4th bit, -IZ old to the 5th bit, and -24 ship to the most significant bit (MSB), respectively. For example, when only the LSB is the il'' signal (i.e. data "000001"), the data is at a level of -0.7&B, and when the data is "111111", the total value of the levels represented by each bit -
47.2 This is the old (minimum value) level data. The output data of a 1-stage, 15-bit register 24 is input via a gate circuit 22 to the second input terminal B of the adder 23 of the accumulator 6.

Adder 23 adds both input data, and the added value is 15
The data is input to the transfer register 24 as bit parallel data. This register 24 is driven by the aforementioned clock pulse CI and outputs the read data to the gate circuit 22 and latch circuit 7 as 15-bit parallel data.
A signal SYC obtained by inverting the signal SYC by an inverter 25 is input to the gate circuit 22 as a control signal so that it is always open except at the end of one scanning period, that is, when the signal SYC is output. Furthermore, the latch circuit 7 is provided with a signal SYC as a data loading signal. therefore,
The adder 23 in the accumulator 6 accumulates and compares the data output from the volume control circuit 5 from the start of one scanning period (when the content of the 12-gun counter is 0). When the content of the 1 magnetic force counter reaches 119, the adder 23 performs the final addition. And the contents of the 12th ward Hayabusa counter evening are 11
When the signal SYC reaches 9, the latch circuit 7 latches the last accumulated value of the adder 23 (this accumulated value is stored in the shift register 24). As explained with reference to FIG. 1, the latched data is further sent to the DA converter 8, amplifier 9, and speaker 0'. Next, the operation of the electronic musical instrument configured as described above will be explained with reference to the operation waveform diagrams shown in FIGS. 6 and 7.

Now, it is assumed that keys C, D2, and G# are pressed simultaneously within a certain scanning period. Also, coupler control circuit 3
It is assumed that each of the drawbars 54 to 549 of 0 is set to the state shown in FIG. By the operation of the hexadecimal counter 15 and the IG Hayabusa counter 16 of the timing signal generation circuit 3, the content of the 12G ship counter constituted by these counters 5 and 16 is set to 0 for one scanning period (this scanning period is now the first period). The operation of one scanning period (referred to as one scanning period) is started.

When the content of the 12G ship counter is between 0 and 11 (that is, the content of the 1G Hayabusa counter 6 is 0), the output signal 1'' of the decoder 11 of the key switch scanning circuit 2 is applied to the column line 1 of the key switch circuit 1. only, and each key C of the first octave is output.
, ~B, are scanned.

During this time, the decoder 2 shows that the content of the hexadecimal counter 15 is 0.
As the output terminals sequentially change from ○ to 11, a 1'' signal is output from the output terminals ○, 0, 2, and the corresponding AND gates 13, to 13, 2 are sequentially opened. In parallel with the above operation. The output signal of the 12-man counter (N, ~N4
, B, ~B4), addresses corresponding to each key C, ~B are sequentially specified in the frequency number memory 18 of the time-division waveform generation circuit 4, and as a result, the frequency numbers corresponding to the pitches of keys C, ~B are sequentially specified. R is sequentially output and input to the adder 19.

The adder 19 repeats the operation of adding the output data of the shift register 20 and the frequency number R and outputting the added value to the shift register 20. Also, the upper 8 bits of the output data of the shift register 20 are stored in the sign table 2.
1, the sign table 21 inputs the key C.1 for this period. The logarithmic sine amplitude corresponding to ~B. g
The output signal A is outputted from the output side and inputted to the input device A of the adder 78 of the volume control circuit 5. In this example, since key C is pressed, key C, which is pressed at the start of this first scanning period, is first detected. Therefore, the output signal of the AND gate 13 of the key switch scanning circuit 2 is 1
Therefore, when the content of the 120-decimal counter is 0, the time division multiplex signal TDM becomes 0''. (Figure 7A
) This signal TDM (,, 1'') is input to the shift register 31 and also to the AND gates 51 to 53 in the weighting circuit 39 of 16'.
1 to 53 are opened. Since the open switch 49 of the weighting circuit 39 of 16' is now set to contact 2 (the fifth
(See figure) Data k representing the numerical value 2, "010" is output from the AND gates 51 to 53 and sent to the adder 48. The shift registers 31 to 31 before this first scanning period starts
Assuming that the contents of 38 are all 0, the output signals of each of the shift registers 31 to 38 (that is, the output signals of points B to 1) are all 0 when the contents of the 12G ship counter are 0. Therefore, the output data K of the adder 48 is "010" which is equal to the setting value 2 of the drawbar 54 of the weighting circuit 39 of 16'. The above signal TDM (,, 1″) due to the key C input into the shift register 31 is
After 12 bit time (when the content of the 12G Hayabusa counter is 12), it is output to point B and input to the shift register 32 (FIG. 7B). This signal is sequentially shifted to the subsequent shift registers 33 to 38 and output to points C to 1 (C to 1 in Figure 7), but the contents of the 12G ship counter at that time are 19 and 24, respectively. ,31,36,40,43
, 48 (see Figure 7). Similarly, keys D2, G#
is detected when the contents of the 12G ship counter are 14 and 56, respectively, and the time division multiplex signal TDM is 1'' at this time.
It becomes a signal (Fig. 7A). This signal TDM(,,1″)
are sequentially shifted by shift registers 31-38. Therefore, signals as shown in FIG. 7 are sequentially output to each point A to 1 within this first scanning period. And each point A
Each time the signal I1^ is output to ~1, the selector switch 49 (drawbar 5
4, ~549) are output to the adder 48 as signals k, ~k9. The adder 48 adds the data k, to k9 outputted from the weighting circuits 39 to 47 of each foot at each bit time, and calculates the added data K.
is output to the first converter 76 of the volume control circuit 5. Here, the operation of the key press number detection circuit 80 will be explained.

When the signal SYC (,, 1'') is output at the end of the previous one scanning period, the AND gate 711 is activated as described above.
~714 is inactive, and the signal TDM is 0.
'', the inputs of each input device A, . . . , carry input terminal Ci of the adder 72 are all 0''. Therefore, the output terminals S, ~S4 of the adder 72 output the addition data "0000".
” (binary number) is output, and this data “0000” is input to the register 74 via OR gates 73 and 734. As a result, the contents of the register 74 are cleared, and the bit signals r and -r4 both become 0''. At this time, the data A latched in the latch circuit 75 is set to 0.
Then, when the content of the 12Q ship counter becomes 0'' and the first scanning period starts, the AND gates 71, to 7
14 is in operation. At this time, as described above, the key C is scanned and the signal TDM(i1'') is outputted (FIG. 7A) and input to the carry input terminal Ci of the adder 72. Add the input data "0000" of the input terminals A, ~A4 and the signal TDM (word, , r),
Addition data "0001" (representing the number of pressed keys of 1) is outputted from the output terminals S, .about.S4, and inputted to the register 74 via the OR gates 73, .about.734. The above data “0001”
In this case, the content of the 12-button Hayabusa counter becomes 14, and the pressed key P2
is scanned and the second signal TDM (, 1'') is output (FIG. 7A).
1, ~714 ~ Adder 72 ~ OR gate 73, ~734
The data is held in circulation by a circulation circuit consisting of a register 74. When the signal TDM(,,1'') for the key D2 is output, the adder 72 adds ,1 to the previous data "0001".
'' is added, new addition data "0010" is calculated, and sent to the register 74. This data "0010" (representing the number of pressed keys 2) is circulated and held by the circulation circuit until the content of the 12G counter becomes 56 and the signal TDM, 1'' is output for the pressed key G#. .Then, the signal TDM (,, 1'') corresponding to the pressed key G# is output (
In the same way as in FIG. 7A), the adder 72 adds the previous data "0010" and "1", calculates new added data "0100" (representing the number of keys pressed 3), and stores it in the register. This data "0100", which is sent to 74, is held in circulation until the end of this scanning period. When the signal SYC (,, 1'') is output, the latch circuit 75 latches data "0100" representing the number of pressed keys, 3, detected within the first scanning period. At the same time, the contents of the register 74 are cleared. The data “0100-,” latched in the latch circuit 75 is transferred from the latch circuit 75 to “data A:3 (
is output as a decimal number) and supplied to the input terminal A of the adder 77. In the second scanning period, the above-described operations are similarly performed, and the signals TDM and DT shown in FIGS. 7A to 1 are
DM is output, and the operation of the key press number detection circuit 80 is also executed.

The second scanning period is started and the content of the 120-decimal counter is 0.
Then, as mentioned above, since the output data K=2 of the adder 48 at this point, the first converter 76 outputs the logarithmic display data corresponding to this data K=north, and the adder 48 outputs the data K=2. It is sent to input terminal B of 77.

The adder 77 adds this data loga and the output data A=3 of the circuit 80 that is input to the cutting edge A, and adds
The calculated data is outputted, and this data of 10 ga is sent to the input terminal B of the adder 78.

At this time, the input terminal A of the adder 78 has the sine table 2.
The sine amplitude value l corresponding to the key C, which is output from 1
Since the og a word is input, the adder 78 converts both data and outputs the skin calculation day state ga back, and the second converter 79
send to

The second converter 79 outputs the data log to the linear data conversion side, and this data is sent to the accumulator 6.
The data is sent to and held in circulation until the 12th bit time (content 11 of the 12G ship counter). 13th bit time (1
When the content of the 2G ship counter becomes 12), the time division multiplexed signal TDM (i1'' signal) of key C is transferred to the shift register 31.
Since this delayed signal DTDM is output after being delayed from
Data k2 for 8 is output from eight weighting circuits 40.

In this case, since the set value of the drawbar 542 is "5", k2=5. At this 13th bit time, there is no other data (k,, k3 to k9) that is similarly output, so the output data K of the adder 48 is also 5, and therefore the output data of the first converter 76 is the log word. becomes. This data is sent to the input terminal B of the log adder 77.
Since the number of pressed keys A = 3 is input to the input terminal A of the adder 77, the output data of the adder 77 increases by 1, and this data increases by a drop of the adder 78. It is input to input terminal B. The input terminal A of the adder 78 receives data corresponding to the key C2. Since the ga table is input, the output of hunger 78 is foreign a
It becomes a turtle and is sent to the second converter 79.

Therefore, the second converter 79 becomes a power data carrier, and this data is input to the adder 23 in the accumulator 6.
sent to.

Until now, the accumulator 6 has the key C. Holding the carp data Mine, Kosuna et al. Kato 23' Makoto calculated both data turtles and compared the value of the data (Ryojumu = Ryo) Line Mochi'.

This signal is held in the accumulator 6 until the time division multiplexed signal TDM for the first key D2 at the fifth bit time is output. The above-described operation is similarly repeated for each of the other signals shown in FIGS. 7A-1.

Immediately before the end of the second scanning period (content 118 of the 12G ship counter), the accumulator 6 holds the total number of column attendants for each of the above-mentioned songs.

This cumulative value is taken into the latch circuit 7 when the signal SYC is output at the end of the second scanning period, and is further input to the speaker 1.
Kawako is sent and pronounced as a musical tone. At the same time, the latch circuit 75 in the key press number detecting circuit 80 also fetches the key press number 3 detected within this second scanning period from the register 74, and its content becomes 3. By the way, the output data value of the second converter 79 is obtained by multiplying the data KS' by the data value.

As seen in FIG. 6, the data has a characteristic that it is inversely proportional to the number of pressed keys, and as the number A of pressed keys increases, the data decreases. On the other hand, it is data that follows the number A of data coral keys. Therefore, as shown in the diagram, the output of the second converter 79 shows a saturation curve that saturates to a predetermined level as the data A increases.

As described above, according to the electronic musical instrument of the present invention, even if a very large number of keys are pressed at the same time, the volume of the musical tone can be kept below a predetermined value by the function of the volume control circuit 5. Next, a modification of the volume control circuit 5 in the above embodiment will be explained with reference to FIG.

This volume control circuit 5' differs from the circuit 5 described above in that the adder 77 in the circuit 5 is replaced with a subtracter 77' in the circuit 5'. For this purpose, the first converter 76' receives the input data K and generates the logarithmic representation data loga K, which is sent to the input B of the subtractor 77'. Input terminal A of subtractor 77'
The output data A of the latch circuit 75 is input to the latch circuit 75 . As a result, the subtractor 77' subtracts (loga K-A)
is executed, and the subtracted data loga is obtained. This data bga is input to the input end B of the adder 78,
The other input terminal A receives a logarithmically displayed waveform signal (sine amplitude value) log a output from the sine table 21'.
S is input. As a result, the added data loga is calculated from the adder 78 and is applied to the second converter 79'. The transducer 79' (power) calculates near data from the skin, and this data is sent to the state.

In the case of the volume control circuit 5' constructed in this way, the same data oven as the armpit/brain circuit 5 can be obtained, so that the above-mentioned effects can be similarly obtained.

In addition, in the above-mentioned invention of this application, the key switch scanning circuit 2
The output signal TDM of is inputted to the coupler control circuit 30, a weighted signal is outputted from this coupler control circuit 30, and this weighted signal is inputted to the volume control circuit 5 to perform volume control. Other inventions of this application that have been deleted may also be provided. In the case of this other invention, since the coupler control circuit 30 is deleted from the above invention,
It is necessary to use other volume control circuits correspondingly modified from the volume control circuits of the invention shown in FIGS. 3 and 8, respectively. That is, in the case of FIG. 3, the first converter 76 and adder 77 are removed, and the output data A of the latch circuit 75 is input to the input terminal B of the adder 78. As a result, the key press number detection data A and the waveform signal loga detected within one scanning period are
The transducer 79 is twisted, and a musical tone whose volume is controlled in response to the push of the track is generated. In the case of Fig. 8, the first
The converter 76' and the subtracter 77' are deleted, and the output data A of the latch circuit 75 is input to the input terminal B of the adder 78.

As a result, the data from the key press number detection data A detected within one scanning period and the waveform signal loga S from the 'Komotozuki converter 79' are falsified, and the volume is controlled according to the number of keys pressed. A musical tone is pronounced. As explained above, this invention
By adding a volume control circuit to the electronic musical instrument previously submitted by this applicant, it is possible to automatically control the volume of generated musical tones to an optimal value according to the number of keys pressed simultaneously.

This invention is particularly effective when a large number of keys are pressed at the same time, since the maximum volume is kept below a predetermined level. Further, since the volume control circuit has an extremely simple configuration, it can be integrated into an integrated circuit, and therefore has various advantages, such as contributing to miniaturization of electronic musical instruments.

[Brief explanation of the drawing]

1 to 7 show a specific example of the electronic musical instrument of the invention of this application, FIG. 1 is a block diagram showing the overall configuration of the electronic musical instrument, and FIGS. 2 and 3 are main parts of the same example. 4 is a diagram showing the correspondence between one scanning period and each key in the same example,
Fig. 5 is a diagram showing one setting state of the drawbar of the same example, Fig. 6
7 and 7 are operation explanatory diagrams of the same example, and FIG. 8 is a diagram showing a modification of the volume control circuit of the electronic musical instrument. DESCRIPTION OF SYMBOLS 1... Key switch circuit, 2... Key switch scanning circuit, 3... Timing signal generation circuit, 4... Time division waveform generation circuit, 5. 5'...
・Volume control circuit, 6... Accumulator, 7...
Latch circuit, 11, 12... decoder, 15, 16...
Counter, 18... Frequency number memory, 21
, 21'...Sine table, 30...Coupler control circuit, 31-38...Delay circuit (shift register), 39-47...Weighting circuit, 48...
. . . Adder, 54 (54, to 549) . . . bar, 71. ~714...and gate, 73, ~7
34... Or Gate, 23, 48, 72, 77, 78・
... Adder, 24, 74 ... Register, 75
・・・． ...Latch circuit t76,76'...
First converter, 77'...Subtractor, 79, 79
′...Second converter, 80...Key press number detection circuit. Figure 1 Figure N Ship Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. A plurality of key switches are sequentially scanned at a predetermined speed to generate a time-division multiplexed signal indicating the key depression state of each key, and the signal is generated in synchronization with the scanning of the key switches to correspond to each pitch. In an electronic musical instrument that generates a waveform signal in a time-divisional manner and obtains a musical tone signal by multiplying the waveform signal and the above-mentioned time-division multiplexed signal, a pressed-key number detection circuit detects the number of keys being pressed. , means for controlling the volume level of the waveform signal based on the key depression number detection data A output from the detection circuit. 2. In the electronic musical instrument according to claim 1, amplitude value logarithmic display data corresponding to amplitude value data S representing each moment-changing amplitude value of a musical sound waveform is generated as the waveform signal, and The means includes an arithmetic circuit that performs a predetermined arithmetic operation based on the key depression number detection data A and the amplitude value logarithm display data, and a conversion circuit that converts the arithmetic output data of the arithmetic circuit into linear display data. An electronic musical instrument characterized by having. 3. In the electronic musical instrument according to claim 2, the arithmetic circuit may calculate the amplitude value logarithm display data loga1/
S and the key press number detection data A are added to obtain data log
a(a_A)/S, and the conversion circuit converts the data loga(a_A)/S into data S/(a
_A) An electronic musical instrument characterized by being a circuit for converting into _A). 4. In the electronic musical instrument according to claim 2, the arithmetic circuit may generate the amplitude value logarithm display data logaS,
and data 1/A based on the key press number detection data A to output data logaS/(a_A), and the conversion circuit outputs data logaS/(a_A).
An electronic musical instrument characterized by being a circuit that converts _A) into data S/(a_A). 5 A plurality of key switches are sequentially scanned at a predetermined speed to generate a time-division multiplexed signal indicating the key press state of each key, and a signal obtained by delaying this time-division multiplexed signal by a predetermined time, according to the set position of the corresponding operator. In addition to outputting the weighted signal as a weighted signal, a waveform signal corresponding to each pitch is generated in a time-sharing manner in synchronization with the scanning of the key switch, and this waveform signal is multiplied by the weighted signal to obtain an instrument signal. In the electronic musical instrument, the volume level of the waveform signal is controlled based on the key press number detection circuit that detects the number of keys being pressed, and the key press number detection data A output from this detection circuit and the weighting signal. An electronic musical instrument characterized by comprising means for. 6. In the electronic musical instrument according to claim 5, amplitude value logarithmic display data corresponding to amplitude value data S representing each moment-changing amplitude value of a musical sound waveform is generated as the waveform signal, and The means includes: a first conversion circuit that converts the weighted signal into logarithmic display data; a first arithmetic circuit that executes a predetermined calculation based on the converted logarithmic display data and the key press number detection data A; a second arithmetic circuit that performs a predetermined arithmetic operation based on the first arithmetic circuit output data and the amplitude value logarithm display data; and a second conversion circuit that converts the output data of the second arithmetic circuit into linear display data. An electronic musical instrument characterized by having a circuit. 7. In the electronic musical instrument according to claim 6, the first conversion circuit converts the weighting signals k_1, k_2 into
The data K obtained by adding ... is the logarithmic display data loga1/K
The first arithmetic circuit converts the logarithm display data loga1/K and the key press number detection data A
The second arithmetic circuit adds the data loga(a_A)/K and outputs the data loga(a_A)/K.
a(a_A)/K and the amplitude value logarithm display data loga
The second conversion circuit adds the data loga(a_A)/(KS) by 1/S and outputs the data loga(a_A)/(KS).
An electronic musical instrument characterized in that it converts into a_A). 8. In the electronic musical instrument according to claim 6, the first conversion circuit converts the weighting signals k_1, k_2 into
... is converted into logarithmic display data logaK, and the first arithmetic circuit adds the logarithmic display data logaK and data 1/A based on the key press number detection data A. Data logaK/(a_
A), and the second arithmetic circuit adds the data logaK/(a_A) and the amplitude value logarithm display data logaS to obtain data loga(KS).
/(a_A), and the second conversion circuit converts the data loga(KS)/(a_A) into data (KS)/(a_A). musical instrument. 9. In the electronic musical instrument according to claims 1 and 2, the key press number detection circuit includes a counting circuit that counts time division multiplexed signals output within one scanning period, and a counting circuit of this counting circuit. An electronic musical instrument comprising a memory circuit for storing and holding output within one scanning period.