JPS60719B2 - Pulse holding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse holding circuit, and particularly to a pulse holding circuit for holding pulse signals when a receiving function failure occurs in a remote monitoring system that performs distant monitoring by counting and counting the number of pulse signals received. This invention relates to a pulse holding circuit.

In a system that performs long-distance monitoring by capturing irregularly generated pulse signals into a retransmission device, sending them to a receiving device via a communication line, and counting the number of pulses on the receiving side,
Conventionally, when an accident such as a disconnection of the communication line or a power cut to the receiving device occurs, reception becomes impossible, and the pulse signals sent from the transmitting device are not counted by the receiving device, and after the accident is restored, the number of pulses sent from the transmitting device cannot be counted. However, the number of pulses counted by the receiving device deviated, and it was difficult to restore the number to an accurate value.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse holding circuit which eliminates the above-mentioned drawbacks and allows accurate pulse values to be restored immediately after the reception function is restored even if the reception function is impaired.

In order to achieve the above purpose, we have developed a function that stops sending pulse signals when the status signal indicating whether the reception function is normal or not indicates an abnormality, and also temporarily stores the number of pulses that will be input from now on. The pulse holding circuit of the present invention is configured to have a function of transmitting a pulse signal of the temporarily stored number of pulses when the reception function is restored and the status signal returns to normal. It is something to do.

Hereinafter, the details of the present invention will be explained with reference to Examples. FIG. 1 is a diagram showing an embodiment of the present invention. In Figure 1,
The irregular pulse signal is taken into the input terminal 1 and outputted from the AND gate 10 via the pulse signal input circuit 3 and flip-flops 6 and 7. All operations during this time are performed in synchronization with the clock waveform from the clock generation circuit 12, and the timing chart thereof is as shown in FIG. That is, even if the input pulse width is irregular, the output of the AND gate 10 is converted into a signal with a constant pulse width equivalent to the clock width. Updown counter 3 and 1
4 is a 4-bit counter that performs addition and storage when a trigger signal is input to its UP terminal, and performs subtraction and storage when a trigger signal is input to its DOWN terminal.

Therefore, all the output pulses of the AND gate 10 are added and stored in the up/down counter 13, and when the added value reaches 15, it becomes a full bit, and with the next pulse input, a pulse is output from the CY terminal and the upper digit of the up/down counter is stored. 14
This is the UP terminal input. The number of such counts that can be counted is determined by the number of up/down counters. As described above, the number of pulses taken into the input terminal 1 is added and stored in the up/down counters 13 and 14, and the presence or absence of stored pulses in these counters is determined by the output terminals A, B, C, and Or gate 15 that took or of D
The determination is made depending on whether the output is "1" or "0".

Next, a description will be given of how the pulse signal processing described above occurs depending on the state of the input signal to the input terminal 2. First, the signal input to the input terminal 2 is as follows. A device is provided on the transmitting side to constantly verify whether the receiving system is normal or not, and from the verification output, "1" is given to input terminal 2 when transmission is possible, and "0" is given to input terminal 2 when transmission is not possible. . The AND gate 5 calculates the AND of the state signal from the input terminal 2, the output of the OR gate 15, and the signal obtained by inverting the output of the pulse signal input circuit 3 by the inverter 4, and the output is sent to the flip-flop 8. , the up/down counter 1 via the AND gate 11, and the waveform shaping circuit 16.
3 and the pulse signal output terminal 17.

A clock signal is also input to the clock input terminal CLK of the flip-flop 8 and one input terminal of the AND gate 11. According to the circuit configuration described above, three conditions are met: the input to input terminal 2 is ready for transmission, the up/down counters 13 and 14 have stored pulses, and input terminal 1 is not receiving an input pulse signal. When it is full, a pulse synchronized with the clock signal is output from the AND gate 11. This output is output from the pulse signal output terminal 17 and at the same time triggers the DN terminal of the AND-down counter 13. Therefore, the number of pulses stored in the up/down counters 13, 14 is sensed by this trigger, and this operation continues until the stored pulses become zero. That is, if there are pulses counted by the counter in the transmittable state, they will be sent out from the terminal 17 while there is no input signal. On the other hand, when the transmission impossible state is input to the input terminal 2, the output condition of the AND gate 5 is not satisfied, the output of the AND gate 11 remains "0"), and the output from the pulse signal output terminal 17 is There is no output and terminal DN of the up/down counter is not triggered.

However, even at this time, the number of pulses input from the input terminal 1 is added and stored in the up/down counters 13 and 14, so that preparation can be made for the return of the receiving side. The above operation is shown in detail in the time chart of FIG.

As is clear from the above explanation, if the pulse holding circuit of the present invention is added to the transmitting side of a remote monitoring device that counts and monitors pulse signals, if the receiving function is normal, The pulse signal is counted and stored in a temporary memory circuit,
It is sent from the transmitting side at the next clock timing, and if an abnormality occurs in the receiving function, the count value during the abnormal period is stored and retained on the transmitting side, and is automatically stored when the receiving function is restored. The number of pulse signals equal to the count value is sent out, and the count value on the receiving side can be corrected to the correct value.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, FIG. 2 and FIG.
The figure is an operation time chart of the embodiment of FIG. 1. 1...Pulse signal input terminal, 2...Transmittable condition input terminal, 5, 11...AND gate,
13, 14...up/down counter, 17...pulse signal output terminal. Fune/Zuzu zzushu 3

Claims (1)

[Claims] 1 a memory circuit for counting and storing the number of input signal pulses; and: when a status signal indicating that the reception function of the receiving side is normal is inputted, while the input signal pulse is not inputted; A number of pulse signals equal to the count value stored in the storage circuit are sent to the reception side, and when a status signal indicating that there is an abnormality in the reception function is input, the storage circuit is sent to the reception side. An output control circuit for stopping the transmission of the counted value of the input signal, and thus retaining the number of input signal pulses even if there is a temporary abnormality on the receiving side, and stopping the transmission of the counted value after the abnormality is recovered. A pulse holding circuit characterized in that it has a function of sending out to the side.