JPS5826711B2 - Fuaximilino - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal tracking device used in facsimile communication, and more specifically, it detects an external synchronization signal supplied from a facsimile transmitter to temporarily synchronize a facsimile receiver. The present invention relates to a facsimile synchronization signal tracking device that completes a tracking operation by detecting at least once a coincidence signal between an internal synchronization signal and an external synchronization signal after temporary synchronization.

Facsimile communication generally involves connecting a transmitter and a receiver via a telephone line, and transmitting and reproducing images by operating the receiver in synchronization with a synchronization signal sent from the transmitter.

In this case, if it takes a long time to perform the synchronization operation, the transmission efficiency will decrease, and if the synchronization remains out of synchronization, the transmitted image will not be reproduced.

To this end, various synchronization signal tracking devices for facsimile communications have been proposed, but the conventional devices are extremely complex and have various drawbacks, such as often malfunctioning due to image signals.

In view of the above points, the present invention has been made in order to solve such problems and eliminate such drawbacks, and its purpose is to provide a facsimile synchronization signal tracking device that can perform reliable operation with a simple configuration. It's about doing.

In order to achieve such an object, the present invention provides a monitoring circuit that monitors the signal width of an external synchronization signal before temporary synchronization and the signal width of a coincidence signal between an internal synchronization signal and an external synchronization signal after temporary synchronization; The device includes a circuit that performs temporary synchronization only when the signal width of the external synchronization signal is within a specified value, and a reset circuit that resets the temporary synchronization when the signal width of the coincidence signal is outside the specified value. and a monitoring operation prohibition circuit that prohibits the operation of the monitoring circuit when the signal width of the external synchronization signal before temporary synchronization is equal to or greater than a specified value, and releases the prohibited operation when the external synchronization signal ends. Equipped with
In this case, the re-operation of the monitoring circuit is prohibited when the signal width of the external synchronization signal is long.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a facsimile synchronization signal tracking device according to the present invention.

In the figure, 1 is an input terminal to which an input signal, that is, a synchronization signal and an image signal, is supplied, 2 is an AND gate that finds a match between the above input signal and the output of an OR gate, which will be described later, and 3 is an input terminal of this AND gate 2. a detector which detects the fall of the output and sends out a pulse; 4 a counter which is set by the output of the AND gate 2 and which counts the first clock pulse; 5;
is a flip-flop triggered by the overflow output of the counter 4, and 6 is the flip-flop 5 triggered by the overflow output of the counter 4.
This counter 6 is set by the set output of , and counts the first clock pulse. This counter 6, together with the counter 4 and flip-flop 5, calculates the signal width of the external synchronization signal supplied from the facsimile transmitter before temporary synchronization, and the signal width of the external synchronization signal supplied from the facsimile transmitter after temporary synchronization. A monitoring circuit 1B is configured to monitor the signal width of the coincidence signal between the internal synchronization signal and the external synchronization signal.

Reference numeral 7 denotes a flip-flop which is triggered by the overflow output of the counter 6 and resets the counter 4 by its reset output. It constitutes a monitoring operation prohibition circuit that sometimes prohibits the operation of the monitoring circuit 18 and releases the prohibited operation upon termination of the external synchronization signal.

Reference numeral 8 denotes an ant gate that finds a match between the output of the detector 3 and the set output of the flip-flop 5, and this AND gate 8 performs temporary synchronization only when the signal width of the external synchronization signal is within a specified value. It constitutes a circuit.

9 is a flip-flop triggered by the output of this AND gate 8; 10 is a counter that counts the second clock pulse and is reset by the output of the AND gate 8; 11 is an overflow signal of this counter 10 and a synchronization check signal; An or gate whose input is 1
2 is an OR gate which takes the output of this OR gate 11 and the reset output of the flip-flop 9 as inputs and supplies the output to one input terminal of the AND gate 2; 13 is the output of the AND gate 8; The AND gate 14 which seeks coincidence with the set output of the flip-flop 9 is a flip-flop that is set by the output of the AND gate 13 and reset by the communication disconnection signal.

15 is an inverter for resetting the flip-flop 7 when there is no output from the AND gate 2; 16;
is the reset output of the flip-flop 14, and the detector 3
This AND gate 16 is an ant gate that uses four people to produce the output of , the set output of the flip-flop 9, and the reset output of the flip-flop 5. A reset circuit is configured to reset temporary synchronization when the width is outside the specified value.

Reference numeral 17 denotes an OR gate for resetting the flip-flop 9 by inputting the coincidence output of the AND gate 16 and a reset pulse.

Next, the operation of the embodiment shown in this figure will be explained.

First, when an input signal consisting of a synchronization signal and an image signal sent from a facsimile transmitter is supplied to input terminal 1, one input of AND gate 2 is supplied with the reset output of flip-flop 9. , the input signal is II
The output of ANDy-12 is sent out for a period of ln.

Then, a counter 4 is set by the rising output of the ant gate 2, thereby sequentially counting the first clock pulses.

In this case, when the counter 4 counts a value corresponding to the lower limit value of the width of the synchronizing signal, it sends out an overflow output and sets the flip-flop 5.

Further, the set output of the flip-flop 5 sets the counter 6 to sequentially count the first clock pulses.

In this case, when the counter 6 counts a value corresponding to the upper limit of the width of the synchronizing signal, it supplies an overflow output to the flip-flop 5 to reset it and set the flip-flop 7.

On the other hand, the detector 3 detects the fall of the output of the AND gate 2, that is, the fall of the input signal, and sends out a pulse. When this pulse matches the output of the flip-flop 5, the AND gate 8 outputs a pulse. is sent.

Therefore, since the flip-flop 5 continues to send a synchronizing signal between the lower limit and the upper limit of the width, when a pulse is sent from the AND gate 8, the input signal has the specified width. This indicates that the signal was a synchronization signal.

The output of the AND gate 8 sets the flip-flop 9 and supplies it to the receiver as an internal clock synchronization pulse to achieve temporary synchronization.

Next, when the temporarily synchronized internal synchronization signal is supplied as a synchronization check signal, this signal is supplied to one input terminal of the AND gate 2 via the OR gate 11 and the OR gate 12. The AND output is sent out only when synchronization with the synchronization signal supplied to is achieved.

When the output of AND gate 2 is sent out, counters 4 and 6
And the flip-flop tube 5 operates in the same manner as described above to check the width of the input signal.

Then, only when the width of this input synchronizing signal is within a specified value, an output pulse is sent out from the AND gate 8 as described above.

When the second pulse is sent from the antgame 8, since the flip-flop 9 is already in the set state, a coincidence output is sent from the AND gate 13 and the flip-flop 14 is set. The set output is sent as a synchronization OK signal.

In addition, in the monitoring circuit 18 composed of the counters 4 and 6 and the flip-flop 5, if the width of the input signal before temporary synchronization is less than a specified value, the flip-flop 5
The detector 3 detects the falling edge of the input signal and sends out a pulse before the input signal is set, and a matching output is not obtained from the AND gate 8, and the width of the input signal before temporary synchronization is the specified value. In the above case, the fall of the input signal is detected after the counter 6 sends an overflow output and resets the flip-flop 5, so the AND gate 8
A matching output cannot be obtained from the , and provisional synchronization cannot be achieved in any case.

On the other hand, if the width of the input synchronization signal after temporary synchronization is below the specified value or above the specified value, a matching output from the AND gate 8 cannot be obtained, and in this case, the reset output of the flip-flop 14, the detector 3, the set output of flip-flop 9, and the reset output of flip-flop 5 to 4.
The matching output of AND gate 16 which is manually operated is OR gate 1
7, and the flip-flop 9 is reset by the output of the OR gate 17 to re-track the correct synchronization signal.

Therefore, counters 4, 6 and flip-flop 5
specifies the allowable width of the synchronization signal.

Note that the flip-flop 7 is mainly used to prevent the counters 4 and 6 and the flip-flop 5 from operating again and sending out erroneous signals when the period of 1n of the input signal before temporary synchronization is long. , once the counter 6 operates, it continues to reset the counter 4 until the input signal reaches ll011 once.

In this case, since the width of the input synchronization signal does not become longer than the width of the internal synchronization signal after temporary synchronization, normally the flip-flop 7 is not set after temporary synchronization.

The counter 10 is a counter that detects synchronization deviation.

Generally, synchronization signals sent from facsimile transmitters are often skipped or delayed for some reason.

Therefore, synchronization may often be lost, but this is not synchronization loss.

A counter 10 is provided to solve this problem.

This counter 10 counts the synchronization signal sent from the receiver, that is, the second clock pulse, which is sent one pulse per line.

In this case, this counter 10 is configured to be reset by the output of the AND gate 8.

Therefore, it is reset every time synchronization is established, and if synchronization is lost consecutively, it is counted sequentially.

When the count value of the counter 10 reaches, for example, 6 and synchronization cannot be achieved over six lines or more, an overflow output is supplied to the OR gate 11 to re-track the synchronization signal.

As explained above, the facsimile synchronization signal tracking device according to the present invention checks the width of the input synchronization signal C and performs the synchronization tracking operation only when the width of the input synchronization signal C is within a specified value. Malfunctions can be prevented.

Furthermore, since the invention is configured to perform temporary synchronization and send out a synchronization completion signal when the internal synchronization signal matches the external synchronization signal sent, the synchronization signal and both signals are simultaneously transmitted. You can quickly synchronize among mixed signals.

In addition, only when synchronization cannot be achieved for a period longer than a predetermined value, it is determined that the synchronization is out of synchronization and re-tracking is performed, which has various excellent effects such as extremely reliable operation.

Further, according to the present invention, the monitoring circuit monitors the signal width of the coincidence signal between the external synchronization signal and the internal synchronization signal, and
This monitoring circuit is shared with the circuit that monitors the signal width of the external synchronization signal before temporary synchronization, and is configured to perform re-tracking even if the phases of both synchronization signals shift, resulting in extremely high precision. This is extremely effective in that high synchronization can be achieved and the circuit configuration can be simplified.

[Brief explanation of drawings]

The figure is a circuit diagram showing an embodiment of a facsimile synchronous tracking device according to the present invention. 2...And gate, 3...Detector,
4, 6...Counter, 5...Flip-flop, 7...Flip-flop (monitoring operation prohibition circuit), 8...And gate, 9...・・・
...Flip-flop, 10...Counter, 1
1, 12. 17... Or Gate, 13...
...And gate, 14...Flip-flop, 16...And gate, 18...Monitoring circuit.

Claims (1)

[Claims] 1. Temporary synchronization of the facsimile receiver is achieved by detecting an external synchronization signal supplied from the facsimile transmitter, and a coincidence signal between the internal synchronization signal and the external synchronization signal after the temporary synchronization is detected at least once. In a synchronization signal tracking device that completes a tracking operation by detecting, A facsimile machine comprising: a circuit that performs temporary synchronization only when the signal width is within a specified value; and a reset circuit that resets the temporary synchronization when the signal width of the coincidence signal is outside the specified value. Synchronous signal tracking device. 2. In the facsimile synchronization signal tracking device as set forth in claim 1, when the signal width of the external synchronization signal before temporary synchronization is equal to or greater than a specified value, the operation of the monitoring circuit is prohibited, and the Synchronous signal tracking for a facsimile machine, characterized in that it includes a monitoring operation prohibition circuit that cancels the prohibited operation upon termination of an external synchronization signal, and prohibits the monitoring circuit from operating again when the signal width of the external synchronization signal is long. Device.