JPS6072021A - Operating device - Google Patents

Abstract

PURPOSE:To shorten an operating time by executing an operation of a carry input ''1'' and ''0'' from a lower rank, counting a value of this result and reading ''0'' of a complement of each digit, respectively, and selecting it. CONSTITUTION:An arithmetic unit executes an operation of an absolute value and normalizes its result, and it is constituted of the first and the second operand store registers 1, 2, operators 3, 4 of a carry input ''1'' and ''0'', an invertor 5, selectors 6, 10, an operation result store register 7, reading ''0'' counting circuits 8, 9, and a count number holding register 11. As for this operation, the first operand A is stored in the register 1 as it is, and the second operand B stores its complement in the register 2, and it is added by the operators 3, 4, respectively. It is inputted to the selectors 6, 10, respectively, in accordance with whether a carry exists or not, and also through the reading ''0'' counting circuits 8, 9. Subsequently, in accordance with a carry output, both outputs are selected, stored in the register 7 and 11, and a result required for the processing is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device, and particularly to an arithmetic device for performing arithmetic operations on the mantissa part of floating point arithmetic operations.

Generally, a normalized floating-point number is composed of a sign indicating its sign, an exponent part, and a mantissa part having a normalized absolute value.

In such floating point number operations, it is often necessary to subtract the absolute value of one floating point number from the absolute value of another floating point number and normalize the result.

In this case, the mantissa of the number with the smaller exponent part is shifted to the right until the exponent of the number with the larger exponent part is equal to the exponent of the number with the smaller exponent part, and then the mantissa of the number with the smaller exponent part is shifted to the right. Performs subtraction in the specified order between the absolute values of the mantissas.

In this subtraction, the sign of the obtained result is determined, its absolute value is determined, and an operation is performed to normalize this absolute value.

To perform this normalization, %Q// (hereinafter referred to as leading O) from the most significant digit until the bit 1111 appears in the first digit of the number representing the absolute value resulting from the subtraction. It is necessary to count the number of

In the conventional device, as will be explained in detail later, the operation of counting the number of leading O's is started after the above-mentioned absolute value subtraction is completed and the absolute value of the result is uniquely determined. The disadvantage is that it takes a long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an arithmetic device which eliminates the above-mentioned conventional drawbacks.

The device of the present invention is an arithmetic device having a function of performing absolute value calculation and normalizing the result of the calculation, and calculates the carry power 1 from the lower order and calculates the leading value corresponding to the result of this calculation -〇〃. A circuit that counts, a circuit that calculates the carry input card Ol from the lower order and counts the complement of each digit of the value corresponding to the result of this calculation, and the output of either of these two circuits. and a selection circuit configured to select in response to a carry generated by the calculation result.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, a first operand storage register 1, a second operand storage register 2, and an arithmetic unit 3 with a carry manpower of %11 are used.
, carry human power 0〃 calculator 4, inverter 5, selector 6
, 10, an operation result storage register 7, a leading θ count circuit 8.9, and a count holding register 11.

Now, in this embodiment, subtraction of subtracting the second operand expressed in absolute value from the first operand expressed in absolute value is performed as follows.

Now, if the first operand is A and the first operand is B, then A〉, o:, B〉o.

The operations to be performed from now on are to perform subtraction A-B under the conditions of h>o, B>o, obtain information on the positive and negative of the result, and obtain the absolute value IA-Bl of the subtraction result. The purpose is to obtain the number of leading 0s appearing in this IA-Bl.

The first operand A is stored in the first operand storage register 1 as is. On the other hand, the second operand B is 11. The inverted version of l# and %Q#, that is, the complement of B, is stored in the second operand storage register 2.

A and ■ stored in register 1 and register 2 in this way are added by arithmetic unit 3 and arithmetic unit 4, respectively.

However, operation p-63 is the addition of A and B when there is a carry to the smallest digit (carry manpower 1%), 1A+B+1
Perform the addition of .

On the other hand, on the side of arithmetic unit 4, if there is no carry to the minimum digit (
Addition of A+B of the carry power SS Q If) and addition of A+E of the total number are performed, and the result of the addition is sent to the inverter 5. J, #, and NO# of each digit are inverted and their complements (i.e. Make (A0B).

Output 3000 to give A+B+1 obtained in this way
The power output 50oO giving
On the other hand, respectively, A+B+1 reaching 0″
? : Leading O counting circuit 8 for counting, and leading 0 counting circuit 9 for counting leading 0's of (A + Li), thus counting the number of leading O's of f'L and t respectively.
are guided by their respective inputs.

Now, when the arithmetic unit 4 performs the above-mentioned operation A+B and an overflow occurs and a carry is output from the upper digit, this carry output is led to the selectors 6 and 10 via the line 4 (100). , when a carry is output to the selector 6il-L carry output 4000, A+B+1 of the output 3000 of the arithmetic unit 3 is selected, and when a carry is not output to the single carry output 4000, the output 5000 from the inverter 5 is selected. (A+B) is selected, and the output of the selected one of these is stored in the calculation result storage register 7.

On the other hand, when a carry is output to the carry output 4000, the selector 10 outputs 'A+' from the count circuit 8.
Select the output that has counted the leading 0 of B+1, and if the carry is not output to the carry output 4000, select the output that has counted the leading 0 of (A + B) from the count circuit 9, and The selected output is stored in the count holding register 11.

Through the above processing, the carry output 4000 is the positive and negative information of the calculation of 8-B (if there is a carry output, it is positive,
If not, it outputs 0 or negative), and the output 00o of register 7 is the absolute value of the subtraction result I Am-B
The output 1100 of the summed register 11 outputs the leading zero of the absolute value IA-Bl of the subtraction result. In this way, all the results necessary for the subsequent processing are obtained in the subtraction of A-B.

If the above processing yields the desired result, <? The reason for the 4t is given in the following passage.

First, assume that A>B.

In the case of B〉0, the complement of B is SS 1 // taking all the digits of the function 3\, and /'c number (from now on, F'
``C'' minus B is equal to fc8<.

That is, in the case of B>0, 13F-B・old...old...fl). Therefore, A-1-B=A0F-B=F0(A-B), but A
-B) Since it is 0, it results in adding a positive number to F and A
Since +B always overflows and generates a carry, the output 4000 can be used as information indicating that the result is positive (01 is not negative).

Next, A-1-B=F+A-B =F+1-1 +A-B From this, A+8+1=1”+1+A-B However, since F+1 represents a carry from the top, A+B+1=A-B+from the top Carry...(2)
becomes.

That is, in the case of A>B, the output 4000 of the A+B dust calculator 4 always outputs a carry, and as a result, the selector 6
A + B + 1 of the output 3000 of the calculation 3 is selected,
This means that the absolute value of A-H is correctly output to A-B from IA-131 (the carry from the upper part of Q operator 3 is ignored).

At this time again? :L, A+B+1 by selector 10
Since the output 8000 on the counting circuit 8 side that counts the leading Oe of is selected, this also outputs the absolute leading zero of positive [7 A-B.

From the above, it can be seen that when A>B, the output is correct.

Next, assuming that A<B, the following results.

As before, using equation (1), we get: Hejukoku: A−+F−B A×B=]”−(B−A)・・・・・・(3).However, ( According to the above assumption, 1:1-A) is a positive number by 0, so subtracting (H-A) from F will not result in a carry.

Therefore, calculation in this case? The result of the operation A-1-B in 24 is a carry from the upper digit, and the output 4000 is 0'! 7' The information indicating that the cat is a koma is correctly output.

Next, if (B-A) is used instead of B in formula (]), (
B-A) = p-(B-A)...
(4) Using the relationship of formula (3), A-1-B= (B-A),', (A-1-B) = B-A= I A-B
It becomes 1. As mentioned above, the output 4000 does not output a carry, and therefore the selector 6 selects the output 5000 (A + B).
) is selected, but as is clear from the above equation, A−H
It correctly represents the absolute value of .

Also, at this time, the selector 10 selects the output of the count circuit 9 side that counts the leading 0 of (A + B), so this also correctly outputs the leading 0 of the absolute value of A-H. .

Thus, it can be seen that the above-described processing gives correct results both in the case of A>B and in the case of A<B.

Now, in this embodiment, the result of separately providing the count circuit 8 for counting the leading 0 of A0B+1 and the count circuit 9 for counting the leading 0 of (A0B), is the calculation of A0B+1. It is stupid to be able to perform the operation of and (A + B) in parallel (, the operation of A + B + 1 and the operation of A +
The operation of counting B+1 leading O's is overlapped with the operation 6 of counting the leading O's of the row, and the carry 4000 is carried from the arithmetic unit 4.
At the time of outputting , both the calculation of leading 0 by circuit 8 and the calculation of leading 0 by circuit 9 have progressed sufficiently, and by the time this carrier IJ-4000 is output,
It is not only possible to obtain IA-Bl in register 7, but also to obtain the result of counting the leading O's of IA-Bl in register 11 almost simultaneously.

This advantage of this embodiment becomes especially clear when compared with the conventional example.

FIG. 2 shows a conventional arithmetic unit that performs the same processing as in the above-described embodiment.

First operand storage register 1 with reference number 1' in Figure 2
' to reference numeral 7' perform the same operations as the corresponding reference numeral elements in the previous embodiment.

Therefore, as is clear from the above explanation, when the signal 'J-4000' is output from the arithmetic unit 4', the correct arithmetic result of IA-Bl is outputted to the arithmetic result storage register 7'.

After the value of IA-Bl is uniquely determined in this way, the leading 0 count circuit 12 starts counting the leading 0 of this IA-Bl, and outputs the count result to the count storage register 11'. .

As a result, in the conventional example, counting of the leading O is started only after the calculation of IA-Bl is completed and the correct result is uniquely given, and
The Bl operation and the leading 0 operation cannot overlap and are necessarily vertically coordinated operations.

Therefore, it is clear that the calculation time of the embodiment of the present invention is shorter.

Actually, in the conventional device, the leading O is counted after the calculation result of IA-Bl is determined, so two cycles are required: the calculation cycle and the leading O count cycle, but according to the embodiment of the present invention, one cycle is required. This can be done by making the cycle count up to the leading O.

Next, we will explain an example of overlapping operations between the arithmetic unit and the leading 0 count circuit on the arithmetic unit side with zero carry power (the arithmetic unit 4 inverter 5 and leading 0 count circuit 9 in Figure 1). The following is an example of the including side).

In this example, the bit width of the data to be calculated is divided into two (for example, in a 16-bit width calculation, the upper digit is divided into 8 bits and the lower digit is divided into 8 bits), and the lower digit is divided into two. The calculation on the side and the performance on the high-order digit side are performed in parallel j7 at the same time. However, for calculations on the high-order digits, both calculations when there is a carry from the low-order digits and operations when there is no carry from the low-order digits are performed regardless of whether there is a carry from the low-order digits. Do it in parallel beforehand? tree,
When a carry actually appears from the lower digit, the correct or incorrect one is selected depending on the presence or absence of an actual carry and is used as the final output. Such an orientation can significantly shorten the calculation time.

FIG. 3 shows the configuration of the arithmetic unit 4, inverter 5, and leading θ count circuit 9 that operate as described above. If there is no carry from the digit side, then the performance of the upper digit side when t is
When there is a carry from the lower digit side, the Kasada calculation unit 43 is used as the calculation unit and inverter 51, 52 . and 53 are arithmetic units 41, 42, . ．． The inverter and reach ink 0 current circuits 91 and 92, which take the complement of the output of 43, calculate the result of the calculation assuming that there is no carry from the lower digit in advance, and the calculation result when the calculation is performed assuming that there is a carry from the lower digit. Circuit to set leading 0, 1 switch 4, ■.

45 and 93 are respectively tL, carry 4 from the lower digit
If there is 100, select and output the results of the calculations on the side that was calculated in advance assuming that there is no carry, and if there is no carry 410o, select each operation This is a selector that outputs the

The operation of the portion shown in FIG. 3 will be easily understood by referring to the above explanation and FIG.

Note that in the above example, the total bit width of the data to be calculated is divided into two equal parts, and the upper digits are delineated in parallel in advance with and without carry from the lower digits. Instead of this, the number of divisions is further increased, and for digits other than the least significant digit, calculations are performed in advance in parallel for cases where there is a carry from the least significant digit and edge 1 match where there is no carry from the least significant digit. Depending on the output, the correct combination can be selected from among the results.

As described above, the present invention has the effect of reducing the calculation time for absolute value subtraction in an arithmetic device having the function of performing absolute value calculations and normalizing the results of the calculations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is a block diagram explaining a part of the embodiment in detail. In the figure, 1...first operand storage register, 2...
...K2 operand storage register, 3...Carry human power %11 arithmetic unit, 4...Carry human power ts Ott arithmetic unit, 6.10...Selector , 7... performance-pain A good luck storage register, 8.9.
...Reading O count circuit, 11...
・・Karan l holding register, 41, 42゜43・・・・
... Arithmetic unit, 51, 52.53... Inverter, 9
1.92...Leating θ count circuit, 4
'4.45.93...Selector. 1st pass 2 mouths

Claims (1)

[Claims] In an arithmetic device having a function of performing absolute value calculation and normalizing the result of the calculation, a calculation of the carry force 111 from the lower order is performed and the leading %0 of the value corresponding to the result of this calculation is counted. A circuit that calculates the carry human power OI from the lower order and counts the reading %01 of the complement of each digit of the value corresponding to the result of this calculation, and the output of either of these two circuits as the result of the calculation. and a selection circuit configured to make a selection in response to a carry occurring due to an error.