JPS607391B2 - solid state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an improvement of a solid-state imaging device, particularly an interline shift method in which a plurality of light receiving sections (corresponding to picture elements) are arranged in a zigzag pattern with respect to a vertical shift register section. related to.

First, in order to facilitate understanding of the present invention, a solid-state imaging device using an interline shift method in which the light receiving portion has a zigzag pattern will be described. FIG. 1 shows its basic configuration. Reference numeral 1 denotes a plurality of vertical shift registers each having a CCD (charge coupled device) structure on a common semiconductor substrate.
A plurality of light receiving sections 2, each serving as a picture element, are arranged in a zigzag pattern so as to share the corresponding vertical shift registers, and at one end of each shift register 1 there is a common horizontal shift register 3 having a CCD configuration. provided. In this case, since the plurality of light receiving sections 2 employs an interlaced scanning method, two light receiving sections 2 are arranged in a zigzag pattern as one set. The vertical shift register has a gate region (transfer section) provided on both sides of the register corresponding to each adjacent light-receiving section 2, and transfers minority carriers generated in each light-receiving section 2 according to the amount of light received to each vertical shift register. For each line, the carriers are transferred to the corresponding vertical shift register through the gate region, and in each shift register the carriers are shifted to the horizontal shift register 3, and the signal is sequentially transmitted from the output terminal t of this shift register 3 for each horizontal line It is designed to take out the Note that when an interlaced scanning method is adopted, a solid line arrow indicates transfer in an odd field, and a broken line arrow indicates transfer in an even field.
According to the group imaging device having such a configuration, the number of vertical shift registers 1 can be reduced to 1/2 or less of that of the subordinate solid-state imaging device, so the number of picture elements in the horizontal direction can be increased accordingly. Since the directional resolution can be increased and the area of the vertical shift register 1 can be expanded, there is an advantage that the carrier transfer efficiency can be significantly improved. FIGS. 2 to 4 show the specific structure of such a conventional solid-state imaging device, particularly the structure of a light receiving section, a vertical shift register, and a gate region. Fig. 2 is a plan view, Fig. 3 is a cross-sectional view taken along line mm, and Fig. 4 is a cross-sectional view taken along line N-W. The shift register 1 is shown, and the diagonally shaded area on the lower right side shows the channel stopper area 4. In addition, the areas A and SA2 indicated by the dashed diagonal lines are the light-receiving areas that become picture elements.
The areas SA and SA2 are arranged in a zigzag pattern as one set. The vertical shift register 1, channel stopper region 4, and light receiving portions SA, , S~ are formed on a common semiconductor substrate, for example, an N-type silicon semiconductor substrate 5. Light receiving part SA. and S~ are constructed by depositing a transparent electrode, that is, a sensor electrode 7, on a substrate 5 via an insulating layer of a predetermined thickness, for example, a Si02 layer 6a, and are separated from each other by a channel stopper region 4. . The channel stopper region 4 includes a main channel stopper region 4A that is substantially parallel to the vertical shift register, and an auxiliary channel stopper region 4B that extends from the main channel stopper region 4B and has a T-shaped planar shape.
This T-shaped auxiliary channel stopper region 4
The light-receiving parts SA and S are separated by B, and at the same time, the sides of the light-receiving parts SA and SA2 and the vertical shift register 1 are also separated. On the other hand, the vertical shift register section 1 has a number of transfer sections corresponding to the respective light receiving sections SA and S, and carriers are transferred in the direction of arrow a by, for example, two-phase clock pulses and ◇2. Each transfer section has a transfer gate area and a storage gate area. That is, the transfer section to which the clock pulse J is applied has transfer gate regions 0, T and storage gate regions 0, S, and the transfer section to which the clock pulse J is applied has transfer gate regions 2T and 2T and storage gate regions 0, S, respectively. Storage gate area? 2S. Here, storage gate area ma, S
and 02S have a thin insulating layer, for example, a Si02 layer 6b, under the electrode, and transfer gate mirrors,
T and? 2T is an insulating layer under each electrode, for example, a Si02 layer 6
c is a storage gate region, S, is formed thicker than 2S, and when a common clock pulse ◇ or 02 is applied, the potential well under S or 2S becomes a transfer gate region ◇. , T or Me2
is made to be deeper than the potential well under T (
(See Figure 3).

Then, each transfer section, that is, in the illustrated example, transfer gate area JIT and storage gate area 0, S and J2S.
is extended in the horizontal direction to the empty area created by the zigzag arrangement of the light receiving agents SA and SA2. Between each of the extended storage gate regions 0 and S and the light receiving section SA, carriers from the light receiving section SA are clock pulsed? A gate region ST for data transfer to the vertical shift register section 1 is provided, and each storage gate region ?
Between 2S and the light receiving part S, the carriers from the light receiving part S are clock pulsed. 2 vertical shift register section 1
A gate region ST2 is provided for transferring the data to. Furthermore, the storage gate area? , S and transfer gate region? , T and gate region ST, are formed by a common electrode 8, respectively, and the storage gate region ? 2S and transfer gate area? The electrodes of 2T and gate region SL are each formed by a common electrode 9. Further, overflow drain regions, regions OG and OG2, which are made of semiconductor regions of opposite conductivity type in the main channel stopper region 4A in the region 1, are located between the overflow drain region 10 and each of the light receiving parts SA and SA2, respectively. Excess carriers generated in the respective light receiving sections SA and SA2 are flowed into the overflow drain region 10 through the gate regions OG and OG2. Next, the operation of the camouflage layer having such a structure will be explained with reference to FIGS. s (for example, s=-10V) is given.

During the transfer period, two-phase clock pulses J are applied to terminals T and L.
, and 42 are applied, but now, for example, in an odd-numbered frame, at the start of the transfer, ◇, = -10V is applied to the terminal T, that is, the electrode 8, and 02 is applied to the terminal T2, that is, the electrode 9.
= OV, and on the other hand, the voltage of sensor electrode 7 is ? s=-5
Let it be V. In this way, a potential well as shown by the reference numeral 13 is formed, and the carriers accumulated under the light receiving part SA pass through the gate region ST and into the storage gate region ? , S. On the other hand, the signal charge 1 of the light receiving part SA2
2 is blocked by the potential barrier under the gate region SL and does not flow to the storage gate region 02S. In this way, the clock pulses applied to the terminals T and L are shifted in the vertical direction through the shift register section 1 and transferred to the horizontal shift register 3 by the clock pulses ◇ and ◇2. After the transfer of the carrier of the odd-numbered frame is completed, the carrier of the next even-numbered frame (0) of the light receiving section SA2 is transferred in the same manner. In FIG. 2, the flow of carriers in the light-receiving parent SA is shown by a solid line, and the flow of carriers in the light-receiving part SA2 is shown by a chain line. By the way, in the solid-state imaging device having such a configuration, the surface potentials of the gate regions ST and ST2 adjacent to the light receiving section SA and SA2 are the same as the transfer gate region of the vertical shift register section 1, respectively.
, T and is ideally similar to the surface potential under 2T, and for this purpose the insulating layer 6d of both
It is necessary to make the thicknesses of and 6b the same, and to make their surface charges Nss or threshold voltages Vth the same.

However, conventionally, the insulating layer 6d of the gate region ST and ST2 and the insulating layer 6c of T and 2T for the transfer gate region are formed in separate steps, and the insulating layer 6d of the gate region ST, the storage gate region ◇, S and the transfer gate are formed in separate steps. A common electrode 8 is formed on the insulating layers 6d, 6b and 6c of the regions ◇, T, and the gate region SL, storage gate region 2S and transfer gate region ? 2T insulating layers 6d, 6b
Since the common electrode 9 is formed on the gate regions ST and ST2, the insulating layer 6d of the gate regions ST and ST2 and the transfer gate regions 0, T and ? It is difficult to make the thickness of the insulating layer 6c of 2T exactly the same, and for this reason, the thickness of the gate region 6T
, and in ST2 and the transfer gate region, T and ?
It was difficult to equalize the surface charge Qss or threshold value voltage Vth of 2T.

FIG. 5 shows details of the conventional manufacturing method, particularly the manufacturing method in the gate region, storage gate region, and transfer gate region. Note that FIG. 5 shows a cross section taken along line A--A in FIG. 2. That is, as shown in FIG. 5A, after etching away the Sj02 layer on the entire surface of the semiconductor substrate 5 on which the channel stopper region, source and drain regions, etc. have been diffused in other parts, the substrate is A Sj02 layer 6 having a predetermined thickness selected as the thickness of the insulating layer of the gate region SL is deposited on the surface of the gate region ST2 (FIG. 5B), and then a Si02 layer 6d on the portion corresponding to the gate region ST2 is deposited. Leave other parts ie storage gate area? The Si02 layer 6 on the portions corresponding to 2S and transfer gate regions M and T is etched away to form a so-called gate window (see Fig. 5C).
), then a first gate oxidation is performed on the gate window hole 14 to form a thin Si02 layer 6b (FIG. 5D).
, then a thick Si02 layer 6d corresponding to the gate region ST2.
storage gate area? A common electrode 9 made of polycrystalline silicon is deposited on the thin SiQ layer 6b corresponding to 2S (FIG. 5E), and then a second gate oxidation is performed to form a transfer gate region on the portion corresponding to T. After depositing a Si02 layer 6c of a predetermined thickness (FIG. 5F), an electrode 8 made of polycrystalline silicon is deposited thereon to form a gate region ST2, a storage gate region 2S and a transfer gate. I was trying to form a chain of chains.

Note that in the gate region ST, and the storage gate region, S
and transfer gate area? 2T is similarly formed. According to this, gate regions ST and SL and transfer gate regions T and ? Si at 2T
It is difficult to make the 02 layers 6d and 6c have the same thickness, and there is also a risk of disconnection due to breakage during the formation of the electrodes 8 and 9. In view of the above points, the present invention selects the insulating layer under the transfer gate region and the insulating layer under the gate region to have the same thickness through the same process, so that the surface potentials of the transfer gate region and the gate region are made equal. Thus, it is an object of the present invention to provide a solid-state imaging device of this type with high reliability. The present invention will be described below with reference to FIGS. 6 to 10. FIG. 6 is a cross-sectional view of the gate region, storage gate region, and transfer gate region in the order of manufacturing steps, and FIG. 7 is a solid-state imaging device. 8 is a cross-sectional view on the skin-to-skin line, FIG. 9 is a cross-sectional view on the K-X line, and FIG. 10 is a cross-sectional view on the X-X line. Portions corresponding to those in FIGS. 4 to 4 are designated by the same reference numerals. In the solid-state imaging device according to the present invention, as shown in FIG. 7, the shape of the channel stopper region 4, the light receiving ratio SA. The arrangement of SA2, vertical shift register 1, etc. is similar to that shown in FIG.

That is, regarding the vertical shift register 1 in which a transfer section consisting of a storage gate area ◇, S and a transfer gate area 0, T, and a transfer section consisting of a storage gate area ◇ and a transfer gate area 2T are arranged alternately. Two light-receiving parts SA and SA2 are arranged as a set in a zigzag pattern, and each light-receiving part SA and SA2 are separated by a T-shaped auxiliary channel stopper region 4B extending from the main channel stopper region 4A. . Each transfer section of the vertical shift register 1 is extended in the horizontal direction to an area where no light receiving section is formed,
Gate regions ST and ST2 are provided between each light receiving section SA and storage gate regions 0 and S, and between each light receiving section SA2 and storage gate region 2S, respectively. Furthermore, an overflow drain region 10 made of a semiconductor region of the opposite conductivity type is provided in the main channel stopper region 4A, and the surplus carriers are transferred between this overflow drain region 10 and each of the light receiving sections SA and S. Gate regions OG and OG2 are formed to form a potential barrier for flowing into the overflow drain region. Therefore, in the present invention, in such a structure, the structure of the gate mirror area T, ST2 and the vertical shift register is improved in particular. As shown in FIG.
After etching away the two layers, a thin Si02 layer 6b corresponding to the thickness of the insulating layer under the storage gate region is formed by a first gate oxidation.

Next, storage gate regions ◇, S and ? on this thin Si02 layer 6b. Storage gate electrodes ◇, M and 2M made of polycrystalline silicon are deposited on portions corresponding to 2S, respectively. In this case, at the same time as the storage gate electrodes M, M and 2M are formed, each of the storage gate electrodes M, M and 2M are formed.
02M are connected to the respective common lead electrodes S, L and ◇
2L are formed in the left and right main channel stopper regions 4A, respectively. (See Figures 6C and 7 to 10) Next, a second gate oxidation is performed to cover the entire surface of the storage gate electrodes ◇, M, G2M and common lead electrodes 0, L and J2L with Si02. Layer 6 is formed under observation. By this second gate oxidation step, the portions corresponding to the gate regions ST and ST2 and the transfer gate mirrors, T and ? Si02 layers 6d and 6c having the same predetermined thickness are formed in portions corresponding to 2T (FIG. 6D). Next, gate region ST,
A common gate electrode M' is formed on the Si02 layer 6d corresponding to the storage gate region S and on the Si02 layer 6c corresponding to T in the transfer gate region so as to straddle the storage gate region S. Also, the Si02 layer 6 corresponding to the gate region ST2
d and transfer gate region ◇Si02 corresponding to 2T
A common gate electrode 2M' is formed on the layer 6c. And in this case too, the gate electrode? , M' and )2M' at the same time as each gate electrode? , M and? Common lead electrodes ◇, L' and 2L' to which 2M' are connected are respectively formed in the left and right main channel stopper regions 4A so as to correspond to the common lead electrodes ◇, L and 2L. (See Figure 6E and Figures 7 to 10) Next, as shown in Figures 8 to 10, the Si02 layer in the portions corresponding to the light receiving areas SA and SA2 is raised as usual. After coating this window hole with a thin Si02 layer 6' of a predetermined thickness, the entire surface is coated with S.
A transparent electrode 7, which serves as a sensor electrode, is formed by depositing an N02 film or a thin polycrystalline silicon layer, and a light-shielding layer made of, for example, an aluminum layer is formed on the transparent electrode 7 in areas other than the light-receiving area SA and S. 13 is deposited and formed.

Note that the common lead electrodes ◇, L and middle, L' are commonly connected at appropriate locations, and the storage gate area 0 is connected through them.
, S electrode? , M and the gate region ST, and the common electrode of T in the transfer gate region? ．． A clock pulse is applied to M', and the common lead electrode? 2
L and the middle 2L' are commonly connected at appropriate points, so that the clock pulse ◇2 is applied to the common electrode 2M of the storage gate region 2M and the common electrode 2M' of the gate region ST2 and the transfer gate region 2T through them. Eggplant. Since the operation of this configuration is exactly the same as that shown in FIG. 2, detailed explanation thereof will be omitted.

According to the present invention described above, in the interline shift type solid-state imaging device using a zigzag pattern, the gate region 6T and ST2 provided between the light receiving section and the storage gate region, and the transfer gate region J of the shift register section 1, Insulating layers 6d and 6 under T and 02T
c are formed simultaneously by the same oxidation process, both insulating layers 6d and 6c have the same thickness, and therefore the surface charge Qss in gate regions ST, SL and transfer gate regions 0, T, 2T Or, the threshold voltages V and V become equal, so that both mirrors, T, T and ST, . Since the surface potential under ST2 is at the same level, a highly reliable group imaging device can be obtained.

In addition, the manufacturing process itself is simplified, and since the first layer of polycrystalline silicon electrodes are formed on the flat Si02 layer, there are practical benefits such as eliminating disconnections due to step breaks.

[Brief explanation of drawings]

FIG. 1 is a basic layout diagram of a solid-state imaging layer with a zigzag pattern, FIG. 2 is a plan view of a conventional solid-state imaging device, and FIGS. 3 and 4 are cross-sectional views taken along line m-m in FIG. 5 is a process diagram showing the conventional manufacturing method; FIG. 6 is a process diagram showing the manufacturing method according to the present invention; FIG. 7 is a plan view of the solid-state bran imaging device of the present invention; 9 and 10 are a cross-sectional view on the blood-lateral line, a cross-sectional view on the K-X line, and
It is a cross-sectional view on one X-ray. 1 is a vertical shift register, 2 is a light receiving section, 3 is a horizontal shift register, 4 is a channel stopper area, SA,,S
A2 is the light receiving part, ST, SL are the gate regions, and T,?
2T is the transfer gate region, ? , S, ◇2S are storage gate areas, 6a, 6b, 6c, 6d, 6, 6'
are insulating layers, respectively. Figure 1 Figure 3 Figure 4 Figure 2 Figure 8 Figure 5 Figure 6 Figure 9 Figure 7 Figure 10

Claims (1)

[Claims] 1. A shift register section in which transfer gate sections and storage gate sections are arranged alternately; a light receiving section in which two of each of the shift register sections are arranged in a zigzag pattern; and the storage gate section and the light receiving section. What is claimed is: 1. A solid-state imaging device having a gate region provided between the portions, wherein an insulating layer under the transfer gate and an insulating layer under the gate region are selected to have the same thickness through the same oxidation process.