JPS6118902B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a TV receiver using a thin film electroluminescent panel (hereinafter referred to as thin film ELP). The present invention relates to a control method for selectively displaying still images using characteristics.

First, the structure and characteristics of thin film ELP will be explained. In FIG. 1, striped transparent electrodes 2 are arranged in parallel on a glass substrate 1, and on this, for example,
A dielectric material layer 3 such as Y ₂ O ₃ doped with e.g. Mn
A fluorescent material layer 4 such as ZnS and the same dielectric material layer 3' as described above are formed into a three-layer structure using a thin film production technique such as vapor deposition sputtering, and a striped structure perpendicular to the transparent electrode 2 is disposed thereon. transparent electrodes 5 are arranged in parallel. In such a structure, when an appropriate AC voltage is applied to one of the first electrode group 2 and one of the second electrode group 5, only the minute area where both electrodes intersect will emit light. Become,
This corresponds to one picture element on the screen.

When the applied voltage remains unchanged, light is emitted with constant brightness each time the applied voltage is applied, but when the applied voltage changes, the brightness exhibits hysteresis characteristics. This hysteresis characteristic will be explained with reference to FIG. When a pulse with a voltage amplitude V ₁ as shown in FIG. 2a is first applied, the brightness is at the level B ₁ as shown in FIGS. 2b and 2c. Here, if the luminescence threshold voltage is V _th , then V ₁ satisfies V ₁ >V _th . When an appropriate write voltage V ₂ is applied to this, the brightness increases all at once to B ₃ , and even after the voltage value is returned to the maintenance voltage V ₁ again, the brightness remains higher than B ₁ .
I settled on B ₂ . When the erase voltage V ₃ is applied to this, the brightness level decreases rapidly, and when it is returned to the sustain voltage V ₁ again, the brightness settles down to B ₁ . These temporal relationships are shown by making the symbols t ₁ , t ₃ , . . . t ₂₁ attached to FIG. 2a correspond to the positions of the same symbols in FIG. 2c. Such hysteresis phenomenon occurs depending on the amplitude or pulse width of the write voltage as shown in Fig. 2b.
Since any small loop can be taken as shown by the thin line, halftone display is also possible.

When displaying a TV image using a thin film ELP having the above-mentioned hysteresis characteristic, electrodes are arranged in a matrix of n rows and m columns, as shown in _FIG . A binary or multi-gradation display signal is applied to Xm, and a control signal for a write signal and an erase signal as well as a sustain signal for sustaining the write state or erase state is applied to the other electrode group, for example, the row electrodes Y ₁ to Yn.

Now, among the picture elements composed of n rows and m columns of electrodes as shown in Fig. 3, the picture element (i.j) that intersects with the i-th column electrode Xi and the j-th row electrode Yj. , a time chart of the voltage waveforms Vxi, Vyj, Vc (i/j) applied to the electrodes Xi, Xj and picture elements (i/j) when a display signal is written, emitted for a while, and then erased. Shown in Figures 4a, b, and c. FIG. 4d shows the light emission waveform of the picture elements (i and j) corresponding to the above applied voltage. In FIG. 4, A is a write pulse, B is a sustain pulse, C is an erase pulse, D is a display signal pulse applied to a column electrode, and E is a row selection pulse. Further, the write pulse I is a pulse generated between the electrodes due to the potential difference between the display signal pulse D and the row selection pulse E.

The present invention uses the above-mentioned thin film ELP light emission control method to control the light emission period and non-light emission period by the timing of application of the write pulse and erase pulse, and also to stop the application of the write pulse and erase pulse and to apply the sustain pulse. The object of the present invention is to provide a display control method that can display a still image by simply continuing to apply only the voltage.

Furthermore, the present invention provides that the relationship between the brightness B of the display and the critical fusion frequency CFF at which the human eye perceives flickering, which is one of the human visual characteristics, is determined by the afterglow time τ of the display as shown in FIG. Considering that the longer the afterglow time is, the lower the critical fusion frequency is for the same brightness, and the larger the area where no flicker is felt, the light emitting period TB relative to the non-emitting period Tn
The objective is to provide a video display method that is bright and has less flicker by increasing the ratio of .

Hereinafter, an embodiment of the present invention for switching between moving image display and still image display using interlaced scanning will be described in detail.

FIG. 6 shows a circuit block diagram of an embodiment of the present invention.

The composite video signal introduced into the video signal input terminal 6 is separated into a video signal and a synchronization signal by a signal separation circuit 7, and each is guided to a signal processing circuit 8 and a timing control circuit 9. The signal processing circuit 8 is composed of a sample and hold circuit and an A-D converter, and sequentially samples the video signal based on a clock signal and converts the video signal into, for example, 8 gradations of luminance level.
It is converted into a 3-bit digital signal representing B ₀ , B ₁ , . . . , B ₇ . The signal holding circuit 10 is a shift register that holds the 3-bit luminance signal corresponding to each of the X column electrode groups X ₁ -Xm of the matrix display panel 18. The display signal pulse generator 11 is a circuit that generates a display signal pulse whose pulse width is modulated in accordance with the above-mentioned digital luminance signal, and FIG. 7 shows an example of the circuit related to an integrated electrode line. In FIG. 7, 19 is a pulse generation circuit that outputs pulses with different pulse widths;
Eight types of pulses with different pulse widths as shown in the figure are output to each output line t ₀ , t ₁ , ..., t ₇ , and 20 is a multiplexer that outputs 3-bit luminance signals Ai,
Outputs pulses from the output terminal according to the contents of Bi and Ci. The X electrode drive circuit 12 is a circuit that drives the electrode groups X ₁ , X ₂ , . . . , Xm of the panel 18 using display signal pulses, and a specific example of the circuit is shown in FIG. On the other hand, the sustain pulse emitter 14, the erase pulse generator 15, and the row selection pulse generator 16 generate the sustain pulse, erase pulse, and row selection pulse explained in conjunction with FIG. These pulses are applied to the electrode groups Y ₁ , Y ₂ , . . . , Yn through the Y row electrode drive circuit 17 . The timing at which these pulses are applied will be described later. The timing control circuit 9 generates various control signals based on the clock signal from the clock generation circuit 13 and the TV synchronization signal, but the most important ones are the field control signal generation section and the video/still image switching control section. Department.

The field control signal generation section sequentially generates four field signals in one frame: an odd field erase period signal EFO, an odd field write period signal WFO, an even field erase period signal EFE, and an even field write period signal WFE based on the synchronization signal. A specific example of the circuit is shown in FIG. In the figure, 21 is a vertical synchronizing pulse input terminal, 22 and 23 are D flip-flops, and 2
4, 25, 26, and 27 are AND gates.

The moving/still image switching control section controls the output of erasing pulses and writing pulses at predetermined timings in accordance with the operation of the switching button, and a specific circuit example thereof is shown in FIG. 9. In the figure, 28 is a changeover operation switch, 29 is an RS flip-flop that memorizes that the still image display has been selected, and 30 is the above-mentioned erasing period signal EFE or
OR gate that detects that EFO is output, 3
1 is the OR gate 3 after the still image display is selected.
A D flip-flop inverts in synchronization with the output of 0, 32 is an AND gate that controls the output of the erase pulse, and 33 controls the output of the row selection pulse.
AND gate 34 is an AND gate that controls the output of the display signal pulse. AND gate 32,3
In addition to the output signal of the D flip-flop 31, the erase pulse timing signal T _VE , the row selection pulse timing signal T _VP , and the display signal pulse timing signal T _VW are input to the input terminals 3 and 34, respectively. The AND gate 32 is arranged at the input end of the erase pulse generator 15, the AND gate 33 is arranged at the input end of the row selection pulse generator 16, and the AND gate 34 is arranged at the output end of the signal processing circuit 8.

Next, the effect will be explained. Note that the moving image display state is called dynamic mode (abbreviated as DM), and the still image display state is called static mode (abbreviated as SM), and the operation of DM will be explained first.

For convenience of explaining the case of interlaced scanning in the embodiment, Y ₁ , Y ₂ , ..., Yn in FIG.
As shown in Figure 1, the odd numbered electrode lines Y ₀₁ , Y ₀₂ ,...
..., Y ₀ N and even-numbered electrode lines YE ₁ , YE ₂ ,
..., YEN and change the signal display separately. That is, Y ₁ = Y ₀₁ , Y ₂ = YE ₁ , Y ₃ = Y ₀₂ , ..., Yn
- ₁ = Y ₀ N, Yn = YEN, and n = 2N.

In the case of normal TV broadcasting, an odd field and an even field are constructed every 1/60 second, and the fields are scanned using a 2:1 interlaced scanning method, so one screen is formed at a speed of 30 frames per second. On the other hand, in the embodiment of the present invention, this writing speed is set to 15 frames per second,
Each field is composed of a write field WF and an erase field EF.

Figure 12 shows the four fields explained in Figure 8.
Shows EFO, WFO, EFE, WFE, and the light emission period and non-light emission period of each row. In the figure, the ◯ marks indicate the timing at which the write pulse is applied, and the x marks indicate the timing at which the erase pulse is applied. Further, the solid line indicates the light emitting period TB, and the dotted line indicates the non-light emitting period TN. First, the horizontal scanning period of WFO during the odd field write period (1H = 63.5μ
s), the contents of the sampled video signals X ₁ to Xm are stored one after another in the signal holding circuit 10, and when the sampling for 1H is completed, the electrodes X ₁ , X ₂ ,...
..., Xm are given display signal pulses all at once, and in synchronization with this, a row selection pulse is given from scanning electrode Y _01. Therefore, by the cooperative action of both pulses, m picture elements on scanning electrode Y ₀₁ A write pulse is applied to the input signal to emit light with a brightness corresponding to the input signal. In the subsequent horizontal scanning period, the video signal related to Y ₀₂ is sampled and stored in the signal holding circuit, and the picture element on the scanning electrode Y ₀₂ emits light. In this way, the scanning electrodes are sequentially selected up to Y ₀ N and emit light. Once a write pulse is applied to these picture elements, their light emission is sustained by a sustain pulse until an erase pulse is applied thereafter. Odd-numbered scanning electrode Y ₀₁ ,
Erasing pulses are given to Y ₀₂ , ..., Y ₀ N during the odd field write period WFO to 3×1/6
It is the next odd field erase period EFO after 0 seconds, and in this period, as in the case of writing described above, erasure is performed by row selection in the order of Y ₀₁ , Y ₀₂ , ..., Y ₀ N. . The odd field write period WFO during which the erased odd-numbered scan electrodes Y ₀₁ , Y ₀₂ , ..., Y ₀ N emit light according to the next image signal is the field immediately after the erase period EFO, that is, 1/60.
seconds later, the pixels associated with the odd-numbered scanning electrodes will emit light for 3 x 1/60 seconds and disappear for 1/60 seconds, repeating this operation at a cycle of 1/15 seconds. The frames of the image will advance.
On the other hand, even-numbered scanning electrodes YE ₁ , YE ₂ , ...,
Writing is performed on YEN during the even field write period WFE, and the light emission is maintained for 3 x 1/60 seconds, and then erase is performed during the even field erase period EFE, and after the erasure is maintained for 1/60 seconds, the next The next image is written in the even field write period WFE. In this way, all picture elements alternately repeat three fields of light emitting periods and one field of non-light emitting periods.

Next, the effect when switching from DM to SM will be explained. In the circuit shown in FIG. 9, when the viewer selects still image display, the switch 28 is turned on, the RS flip-flop 29 is immediately set, and the D input of the D flip-flop 31 becomes H level, entering a set standby state. In this state, when the odd field erase period signal EFO or the even field erase period signal EFE is output, the D flip-flop 31 is triggered and the output is high.
Inverts from level to L level. Therefore, AND
Each output of gates 32, 33, and 34 is inhibited,
Timing signal T _V from AND gates 32 and 33
Row electrodes Y ₀₁ to YEN receiving and applying _E and T _VP
The image signals introduced into the signal holding circuit 10 in response to the erase pulse and write pulse of , and the timing signal T _VW from the AND gate 34 are EFO and EFE.
The row electrode Y ₀₁ is cut off synchronously with the beginning of the period of
Only the sustain pulse is continuously applied to _YEN . In such a state, as is clear from the action explanatory diagram of FIG. 4, the display contents of the matrix panel 18 are maintained only by the sustain pulse.

Fig. 13a shows the state in which DM→SM is switched when the viewer performs DM→SM instruction S ₁ or S ₂ in the field period EFO or WFO, and Fig. 13b
shows a state in which DM→SM is switched when DM→SM instruction S ₃ or S ₄ is performed in field period EFE or WFE. By performing such control, display contents are frozen when writing of each picture element on the odd-numbered or even-numbered scanning electrodes is completed, so that a good still image can always be obtained.

Conversely, when switching from SM to DM, it is preferable to similarly switch back to DM at the beginning of the field period EFO or EFE. The first reason is that it prevents the screen from being disrupted even for a short period of time, and the second reason is that DM
This is because a common circuit configuration can be used for switching control from to SM. However, it does not necessarily have to be a synchronous type, and even in the case of an asynchronous type, the passing time is about several tens of milliseconds, so the viewer can barely detect this disturbance, which impedes practicality. There isn't.

As is clear from the above description, according to the present invention, good still images can be displayed with an extremely simple device without providing any external memory.

[Brief explanation of the drawing]

1A and 1B are a partially cutaway perspective view and a sectional view of the thin film ELP, FIG. 2 is an explanatory diagram showing the history phenomenon of the applied voltage versus luminance of the thin film ELP, and FIG. 3 is a configuration diagram of the matrix electrode. Figure 4 is an explanatory diagram showing the relationship between the electrode applied voltage waveform and the emission waveform of thin film ELP.
The figure is a human visual characteristic diagram, FIG. 6 is a circuit block diagram of an embodiment of the present invention, and FIG. 7 is a display signal pulse generator 11 and an electrode drive circuit 1 in the above embodiment.
2, FIG. 8 is a circuit example showing the field control signal generation section in the timing control circuit 9 in the above embodiment, and FIG. 9 is a circuit example showing the video/still image switching control section in the timing control circuit 9 in the above embodiment. 10 is an explanatory diagram of the operation of the display signal pulse system of the X ₁ to Xm electrodes of the above embodiment, FIG. 11 is an explanatory diagram of interlaced scanning of the matrix panel of the above embodiment, and FIG. 12 is an explanatory diagram of the interlaced scanning of the matrix panel of the above embodiment. FIG. 13 is an explanatory diagram of the operation regarding the field control of the above embodiment. FIG. 13 is an explanatory diagram of the switching timing from a moving image to a still image of the above embodiment. 7... Signal separation circuit, 8... Signal processing circuit, 9
...Timing control circuit, 10...Holding circuit, 1
1...Display signal pulse generator, 12...X column electrode drive circuit, 13...Clock generation circuit, 14...
Sustain pulse generator, 15... Erase pulse generator,
16...Write pulse generator, 17...Y row electrode drive circuit, 18...Matrix panel, 28...
...Image change switch.

Claims (1)

[Claims] 1. In a device that displays TV images using a thin-film electroluminescent panel that exhibits a hysteresis phenomenon in the relationship between applied voltage and luminance, a write field period and an erase field period are provided alternately and synchronized with the start of the erase field period. 1. A television receiver, characterized in that the television receiver is configured to obtain a still image by suppressing erasing pulses and writing pulses after the first one.